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Design & Test, IEEE

Issue 5 • Date Oct. 2013

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Displaying Results 1 - 24 of 24
  • Front Cover

    Publication Year: 2013 , Page(s): C1
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  • Cover 2

    Publication Year: 2013 , Page(s): C2
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  • Masthead

    Publication Year: 2013 , Page(s): 1
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  • Table of Contents

    Publication Year: 2013 , Page(s): 2
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  • Table of contents

    Publication Year: 2013 , Page(s): 3
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  • A Look at IEEE P1687 Internal JTAG (IJTAG)

    Publication Year: 2013 , Page(s): 4 - 5
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  • FPGA-Based Embedded Tester with a P1687 Command, Control, and Observe-System

    Publication Year: 2013 , Page(s): 6 - 14
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (875 KB)  

    This article discusses the embedding of a tester on an FPGA, which uses IJTAG to enable flexible and dynamic access to test configurations of the on-chip instruments. View full abstract»

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  • Executing IJTAG: Are Vectors Enough?

    Publication Year: 2013 , Page(s): 15 - 25
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (1604 KB)  

    This article highlights the challenge of making dynamic IJTAG operational. While the PDL allows flexibility, it generates problems for the back-end, which is how IJTAG operations are combined and executed. View full abstract»

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  • Effective Scalable IEEE 1687 Instrumentation Network for Fault Management

    Publication Year: 2013 , Page(s): 26 - 35
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (783 KB)  

    The infrastructure of IJTAG can be utilized during operation to detect errors and make appropriate fault handling. This article describes an architecture where error latency and automation are important requirements. View full abstract»

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  • Thinking About Adopting IEEE P1687?

    Publication Year: 2013 , Page(s): 36 - 43
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (609 KB)  

    This article discusses challenges related to providing EDA tools for IJTAG through three use scenarios adaptation of test flows, including need for IP providers, pattern reuse, and gluing all different cores together. View full abstract»

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  • Identifying Systematic Failures on Semiconductor Wafers Using ADCAS

    Publication Year: 2013 , Page(s): 44 - 53
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    Product engineers are often called upon to use their unique mix of expertise and intuition to solve yield puzzles. Any tool that can help ease and automate the process is a welcome one. Industrial case studies demonstrate a new tool's potential to provide automatically accurate, and potentially early, indications of underlying root cause for low-yielding wafers. View full abstract»

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  • Off-Chip Memory Encryption and Integrity Protection Based on AES-GCM in Embedded Systems

    Publication Year: 2013 , Page(s): 54 - 62
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (486 KB)  

    To ensure the overall security of embedded systems with off-chip memories, it is essential to safeguard the confidentiality and integrity of the data that travels between the system-on-chip part of the embedded system and the off-chip memory. This article presents a novel low-overhead architecture to achieve this goal. View full abstract»

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  • A Fault Analysis Perspective for Testing of Secured SoC Cores

    Publication Year: 2013 , Page(s): 63 - 73
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    Can the inputs of a cryptocore be stressed to leak the secret key? This article demonstrates such a vulnerability challenging secure integration of these cores in a system-on-chip design. View full abstract»

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  • A Sensor-Assisted Self-Authentication Framework for Hardware Trojan Detection

    Publication Year: 2013 , Page(s): 74 - 82
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (626 KB)  

    Detecting hardware Trojan attacks often rely on availability of pre-verified golden chips. In this article, authors propose an efficient Trojan detection approach using sequence of path delay traces that eliminate such a need. View full abstract»

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  • “Our Original 3D Idea Still Has To Happen; And It Will”

    Publication Year: 2013 , Page(s): 83 - 88
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  • IEEE Phaser Data

    Publication Year: 2013 , Page(s): 89
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  • Test Technology TC Newsletter

    Publication Year: 2013 , Page(s): 90 - 91
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  • IEEE Was Here

    Publication Year: 2013 , Page(s): 92
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  • CEDA Currents

    Publication Year: 2013 , Page(s): 93 - 94
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  • IEEE Semantic Technology

    Publication Year: 2013 , Page(s): 95
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  • Faculty Position in Distributed Computing Systems Engineering

    Publication Year: 2013 , Page(s): 94
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  • Privacy Through Obscurity

    Publication Year: 2013 , Page(s): 96
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  • Cover 3

    Publication Year: 2013 , Page(s): 97
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  • Cover 4

    Publication Year: 2013 , Page(s): 98
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Aims & Scope

IEEE Design & Test offers original works describing the models, methods and tools used to design and test microelectronic systems from devices and circuits to complete systems-on-chip and embedded software. The magazine focuses on current and near-future practice, and includes tutorials, how-to articles, and real-world case studies. The magazine seeks to bring to its readers not only important technology advances but also technology leaders, their perspectives through its columns, interviews and roundtable discussions. Topics include semiconductor IC design, semiconductor intellectual property blocks, design, verification and test technology, design for manufacturing and yield, embedded software and systems, low-power and energy efficient design, electronic design automation tools, practical technology, and standards.  

It was published as IEEE Design & Test of Computers between 1984 and 2012.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief
Andre Ivanov
Department of Electrical and Computer Engineering, UBC