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IEEE Computer Architecture Letters

Issue 2 • July-Dec. 2013

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Displaying Results 1 - 15 of 15
  • Cover1

    Publication Year: 2013, Page(s): c1
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  • Cover2

    Publication Year: 2013, Page(s): c2
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  • Editorial

    Publication Year: 2013, Page(s):37 - 38
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  • High Performance, Energy Efficient Chipkill Correct Memory with Multidimensional Parity

    Publication Year: 2013, Page(s):39 - 42
    Cited by:  Papers (2)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (257 KB) | HTML iconHTML

    It is well-known that a significant fraction of server power is consumed in memory; this is especially the case for servers with chipkill correct memories. We propose a new chipkill correct memory organization that decouples correction of errors due to local faults that affect a single symbol in a word from correction of errors due to device-level faults that affect an entire column, sub-bank, or ... View full abstract»

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  • Data Dependent Sparing to Manage Better-Than-Bad Blocks

    Publication Year: 2013, Page(s):43 - 46
    Cited by:  Papers (2)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (310 KB)

    We forecast that proper handling of unreliable storage blocks (e.g., "bad block management" in solid-state drives) will remain critical for future systems built with advanced and emerging memory technologies. This paper argues that the conventional block retirement and sparing approach--a block is retired as soon as it shows faulty behavior--is overly conservative and inefficient. We observe that ... View full abstract»

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  • Clumsy Flow Control for High-Throughput Bufferless On-Chip Networks

    Publication Year: 2013, Page(s):47 - 50
    Cited by:  Papers (11)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (252 KB) | HTML iconHTML

    Bufferless on-chip networks are an alternative type of on-chip network organization that can improve the cost-efficiency of an on-chip network by removing router input buffers. However, bufferless on-chip network performance degrades at high load because of the increased network contention and large number of deflected packets. The energy benefit of bufferless network is also reduced because of th... View full abstract»

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  • GreenRouter: Reducing Power by Innovating Router's Architecture

    Publication Year: 2013, Page(s):51 - 54
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (504 KB)

    High speed routers in Internet are becoming more powerful, as well as more energy hungry. In this paper, we present a new architecture of router named GreenRouter which separates a line-card into two parts: network interface card (DB) and packet processing card (MB), connected by a two-stage switch fabric in traffic flows' ingress and egress direction respectively. Traffic from all DBs shares all ... View full abstract»

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  • A Hybrid PRAM and STT-RAM Cache Architecture for Extending the Lifetime of PRAM Caches

    Publication Year: 2013, Page(s):55 - 58
    Cited by:  Papers (12)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (332 KB) | HTML iconHTML

    To extend the lifetime of phase change RAM (PRAM) caches, we propose a hybrid cache architecture that integrates a relatively small capacity of spin transfer torque RAM (STT-RAM) write buffer with a PRAM cache. Our hybrid cache improves the endurance limitation of the PRAM cache by judiciously redirecting the write traffic from an upper memory layer to the STT-RAM write buffer. We have demonstrate... View full abstract»

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  • Multicore Model from Abstract Single Core Inputs

    Publication Year: 2013, Page(s):59 - 62
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (234 KB)

    This paper describes a first order multicore model to project a tighter upper bound on performance than previous Amdahl's Law based approaches. The speedup over a known baseline is a function of the core performance, microarchitectural features, application parameters, chip organization, and multicore topology. The model is flexible enough to consider both CPU and GPU like organizations as well as... View full abstract»

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  • Demystifying multicore throughput metrics

    Publication Year: 2013, Page(s):63 - 66
    Cited by:  Papers (13)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (256 KB)

    Several different metrics have been proposed for quantifying the throughput of multicore processors. There is no clear consensus about which metric should be used. Some studies even use several throughput metrics. We show that there exists a relation between single-thread average performance metrics and throughput metrics, and that throughput metrics inherit the meaning or lack of meaning of the c... View full abstract»

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  • SMT Switch: Software Mechanisms for Power Shifting

    Publication Year: 2013, Page(s):67 - 70
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (120 KB) | HTML iconHTML

    Simultaneous multithreading (SMT) as a processor design to achieve higher levels of system and application throughput is a well-accepted and deployed technique in most desktop and server processors. We study the power implications of varying SMT levels i.e., thread counts per core for various multi-threaded applications on a real SMT multicore platform, and introduce a novel software mechanism of ... View full abstract»

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  • IEEE Open Access Publishing

    Publication Year: 2013, Page(s): 71
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    Freely Available from IEEE
  • Stay Connected to the IEEE Computer Society

    Publication Year: 2013, Page(s): 72
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  • Cover3

    Publication Year: 2013, Page(s): c3
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  • Cover4

    Publication Year: 2013, Page(s): c4
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Aims & Scope

IEEE Computer Architecture Letters is a rigorously peer-reviewed forum for publishing early, high-impact results in the areas of uni- and multiprocessor computer systems, computer architecture, microarchitecture, workload characterization, performance evaluation and simulation techniques, and power-aware computing. 

Full Aims & Scope

Meet Our Editors

Editor-in-Chief
Daniel J. Sorin
Duke University
Electrical & Computer Engineering
PO Box 90291
Durham, NC 27708
e-mail: sorin@ee.duke.edu