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Components, Packaging and Manufacturing Technology, IEEE Transactions on

Issue 12 • Date Dec. 2013

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  • [Front cover]

    Publication Year: 2013 , Page(s): C1
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  • IEEE Transactions on Components, Packaging and Manufacturing Technology publication information

    Publication Year: 2013 , Page(s): C2
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  • Table of contents

    Publication Year: 2013 , Page(s): 1989 - 1990
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  • Our Thanks to Reviewers IEEE Transactions on Components, Packaging and Manufacturing Technology

    Publication Year: 2013 , Page(s): 1991 - 1993
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  • Thermally Conductive MgO-Filled Epoxy Molding Compounds

    Publication Year: 2013 , Page(s): 1994 - 2005
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (3264 KB) |  | HTML iconHTML  

    The use of magnesium oxide (MgO) as a filler in an epoxy molding compound (EMC) was considered to identify the maximum thermal conductivity that could be achieved without compromising rheological or processing control and processing flexibility. MgO is an attractive candidate filler for EMCs used in automotive and other applications because MgO is inexpensive, electrically insulative, has relatively high thermal conductivity, is nontoxic, and is a relatively soft filler material meaning it will be less abrasive to surfaces it contacts during its processing and shape molding. A maximum bulk thermal conductivity of 3 W/mK was achieved with a 56% volume fraction of MgO filler. This 56 vol% MgO-filled EMC has a thermal conductivity approximately twice that of traditional silica-filled EMCs with the same volume fraction of filler and has equivalent electrical insulative, thermal expansion, and water absorption characteristics. It is concluded that if a thermal conductivity greater than 3 W/mK is needed in an EMC, then a much more expensive filler material than MgO must be used. View full abstract»

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  • Fabrication of Micro-Polymer Lenses With Spacers Using Low-Cost Wafer-Level Glass-Silicon Molds

    Publication Year: 2013 , Page(s): 2006 - 2013
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (837 KB) |  | HTML iconHTML  

    A novel low-cost molding process to prepare polymer-based micro-lens arrays with spacers for optical applications was investigated in this paper. The process consists of the following steps: 1) hemispherical glass bubble arrays, used as the upper part of the molds, was prepared by combining a hot-forming process and a chemical-foaming process; 2) the silicon mold, used as the lower part of the molds, was fabricated by etching; 3) an anti-stick layer was coated on the concave surface of the glass mold; and 4) the lens material, UV-curable glue, was dispensed into the concave molds, followed by curing and de-molding. The optical properties of the lens were characterized by a profile meter and a beam analyzer. The results showed that the micro-polymer lens arrays with spacers were successfully prepared using the low-cost wafer-level glass-silicon mold. The results indicate that the micro-lenses have hemispherical structures and smooth surface. View full abstract»

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  • Performance Comparison of Flip-Chip-Assembled 5-GHz 0.18- \mu{\rm m} CMOS Power Amplifiers on Different Packaging Substrates

    Publication Year: 2013 , Page(s): 2014 - 2021
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    In this paper, three 5-GHz power amplifiers (PAs) are presented, which were implemented in 0.18- μm CMOS technology on different package substrates using flip-chip assembly. To make a fair comparison, the three PAs use the same circuit topology and transistor peripherals. The first case is a fully on-chip integrated CMOS PA with on-chip inductors. The second case uses low-temperature cofired ceramic (LTCC) inductors for the matching network, and the CMOS die is flip-chip-assembled on the LTCC substrate. For the last case, the CMOS bare die is assembled on the ceramic integrated passive device (CIPD) substrate, also by the flip-chip technique, and CIPD inductors are used as the matching network. Moreover, the PA performances with respect to the quality factor of inductors are discussed and verified with the experimental results. The fully on-chip integrated CMOS PA performs at 25.2 dB gain and 22.5 dBm OPSAT with a peak PAE of 22%. The system-in-package (SiP) CMOS PA on LTCC demonstrates 27 dB gain and 23.5 dBm OPSAT with a peak PAE of 27.5%, and the SiP CMOS PA on CIPD performs with 26.8 dB gain and 24 dBm of OPSAT with a peak PAE of 30%. With low-loss inductors on LTCC or CIPD, the maximum improvements of gain and PAE at PSAT can be up to 1.5 dB and 8 percentage Points, compared to the fully on-chip PA. To our knowledge, this is the first comprehensive PA performance comparison for different SiP approaches. View full abstract»

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  • Wafer-Level Packaging Design With Through Substrate Grooves as Interconnection for GaAs-Based Image Sensor

    Publication Year: 2013 , Page(s): 2022 - 2028
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    A wafer-level packaging design for GaAs-based image sensor is presented. Key processes, such as GaAs/glass wafer bonding, GaAs substrate thinning, through substrate grooves (TSGs) fabrication, redistribution layer formation, polymer passivation, and laser jet bumping, are examined and characterized. GaAs image sensor package with 64 leads is successfully fabricated on 4-in thinned GaAs/glass test vehicle wafer. In the package, two long TSGs are wet etched as the interconnection path. Process parameters are systematically studied and given. Then, fabrication results of these processes were discussed. Finally, electrical tests show that ohmic contact is obtained with a resistance of around 30 Ω between two nearby interconnections. View full abstract»

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  • Explaining Nondestructive Bond Stress Data From High-Temperature Testing of Au-Al Wire Bonds

    Publication Year: 2013 , Page(s): 2029 - 2036
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2419 KB) |  | HTML iconHTML  

    The application of an alternative method of bond monitoring during high-temperature aging is reported using a custom made test chip with piezoresistive integrated CMOS microsensors located around test bond pads. The sensor detects radial stresses originating from the bond pad and can resolve changes because of intermetallic compound (IMC) formation, voiding, or crack formation at the bond interface. Optimized Au ball bonds are aged for over 2000 h at 175 °C. It is found that stress sensors next to the bonds are capable of showing the stages of IMC growth, consumption of pad Al layers, and monitoring the formation of low-density and Al-rich IMC (AuAl2) which shows an advanced stage of aging. In particular, a first stress signal increase corresponds to the conversion of all Al above the diffusion barrier into IMCs. The second increase in stress signal after a period of stability corresponds to conversion of all Al below the barrier into IMCs. The IMC formation in these periods causes shear strength increase. After complete bond Al consumption, the bond, however, reaches maximum strength. As bond degradation starts, e.g., by lateral IMC formation, voiding, and oxide formation, as well as because of lateral pad Al transformation to IMC, the signal exhibits a strong decrease. The findings are corroborated by results obtained from classical methods such as interruptive or destructive testing including visual inspection, shear testing, cross sectioning, and by bond resistance monitoring. View full abstract»

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  • Interconnect Reliability Characterization of a High-Density 3-D Chip-on-Chip Interconnect Technology

    Publication Year: 2013 , Page(s): 2037 - 2047
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2075 KB) |  | HTML iconHTML  

    This paper investigates the solder interconnect reliability of a high-density 3-D chip-on-chip technology under an accelerated thermal cycling (ATC) test condition through finite element (FE) modeling and experimental validation. The fabrication of the 3-D chip-on-chip technology is accomplished with a two-step gap control bonding process to minimize the solder squeezing phenomenon. The alternative goal of this paper is placed on the influences of underfill on the interconnect failure mechanism and reliability. With the calculated plastic strain, the thermal fatigue life of the most critical solder interconnect can be estimated through an empirical Coffin-Manson fatigue life prediction model. The effectiveness of the proposed FE modeling is demonstrated through ATC tests. Finally, to identify the parameters most affecting the lead-free solder interconnect reliability, both parametric FE analysis and a simulation-based experimental design scheme based on a response surface methodology are carried out with the validated FE model. Both the numerical and experimental results that underfill can not only change the interconnect failure mechanism from an interfacial crack between the Al pad and the copper (Cu) layer of the under bump metallurgy to a cohesive solder failure, but also greatly improve the solder interconnect thermal fatigue life by as much as 2.5 times. Furthermore, the experimental design demonstrates that both the Young's modulus of intermetallic compound and thermal expansion coefficient of underfill are identified as the parameters most affecting the solder interconnect reliability of the 3-D chip-on-chip technology. View full abstract»

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  • Reduced Power Precision Temperature Control Using Variable Conductance Heat Pipes

    Publication Year: 2013 , Page(s): 2048 - 2058
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    This paper assesses the use of variable conductance heat pipes (VCHPs) for reduced-power precision temperature control of photonics components. When subambient cooling is not required we consider only a VCHP and where it is required we consider a VCHP-thermoelectric module (TEM) assembly. In the former case, the setpoint of the component mounted to the VCHP is 70°C and a range of heat loads (0 to 12 W) and ambient temperatures (-5°C to 65°C), representative of a photonics component in a telecommunications environment, are imposed on the system. In passive operation, the VCHP provided good temperature control for varying heat load, but not for varying ambient temperature. In active operation, i.e., when the reservoir of noncondensable gas on the VCHP is heated, good temperature control is achieved for ambient temperatures from 10°C to 65°C. The experimental measurements are compared with the theoretical predictions of the flat front model. For the TEM-VCHP assembly experiments, the component is maintained at a representative setpoint temperature, 63±1°C, for heat loads from 2 to 7 W and ambient temperatures from 0°C to 60°C, such that a TEM is essential. The TEM-VCHP assembly power consumption is quantified and compared with a TEM-constant conductance heat pipe assembly. The maximum TEM power consumption for the TEM-VCHP assembly is over 40% lower. View full abstract»

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  • Prospects of Thin-Film Thermoelectric Devices for Hot-Spot Cooling and On-Chip Energy Harvesting

    Publication Year: 2013 , Page(s): 2059 - 2067
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    Advances in thin-film thermoelectric (TE) materials have created opportunities for using TE devices in high heat flux applications such as hot-spot (H-S) cooling and on-chip energy harvesting. In this paper, we compare the performance of TE modules integrated directly on the silicon die with those that are attached to the heat spreader of the chip package. We make use of the Bi2Te3/Sb2Te3 super lattice material to explore tradeoffs between the two integration options for H-S cooling and energy-harvesting applications. Package level finite element simulations show that on-chip energy harvesting can yield up to 30 mW of power from an H-S with a heat flux of 200 W/cm2, or the same H-S can be cooled as much as 19°C in the cooling mode. In addition, the TE module integrated on the die is shown to have a disadvantage due to the higher thermal resistance from the hot side of the module to the ambient. View full abstract»

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  • The Study of the Polydispersivity Effect on the Thermal Conductivity of Particulate Thermal Interface Materials by Finite Element Method

    Publication Year: 2013 , Page(s): 2068 - 2074
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    Thermal interface materials (TIMs) are particulate composite materials widely used in the microelectronics industry to reduce the thermal resistance between the device and the heat sink. Predictive modeling using fundamental physical principles is critical to developing new TIMs, since it can be used to quantify the effect of polydispersivity, volume fraction and arrangements on the effective thermal conductivity. A random network model that can efficiently capture the near-percolation transport in these particle-filled systems was developed by the authors, which can take into account the interparticle interactions and random size distributions. In this paper, a Java-based code is used to generate the microstructures at different volume fraction and different particle-size distribution (PSD). COMSOL was used to investigate the impact of polydispersivity on the effective thermal conductivity of particulate TIMs. The log-normal distribution was used to capture the filler PSD. From the simulation results, there exists an optimum value of the polydispersivity which has the largest thermal conductivity for a given volume fraction. View full abstract»

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  • Study of Response Surface Methodology in Thermal Optimization Design of Multichip Modules

    Publication Year: 2013 , Page(s): 2075 - 2080
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1229 KB) |  | HTML iconHTML  

    A 3-D model of multichip module (MCM) is built with ANSYS and the temperature field distribution is studied. A regression equation describing the relationship of structure parameters and material properties with the maximum chip junction temperature of MCM is made, which integrates the response surface methodology and ANSYS. Quantitative analysis of the effect of four design parameters on the maximum chip junction temperature of MCM is studied. The four design parameters are the thickness of the substrate, thermal conductivity of the substrate, thermal conductivity of the thermal grease, and convection heat transfer coefficient, respectively. The accuracy and validity of the regression equation are validated by simulation with ANSYS. In addition, the maximum error between the calculation value of the regression equation and the simulation value with ANSYS is 0.541°C. With the regression equation, the thermal optimization design results of the four parameters are Ktg = 5 W/m°C, δ = 2.5 mm, Ks = 290 W/m°C, and h = 55 W/m2°C, which lead to the maximum chip junction temperature Tjmax = 89.172°C as the minimum value. View full abstract»

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  • Signal Integrity-Aware Virtual Prototyping of Field Bus-Based Embedded Systems

    Publication Year: 2013 , Page(s): 2081 - 2091
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (3719 KB) |  | HTML iconHTML  

    In this paper, we introduce a modeling methodology for field bus-based embedded systems that allows dynamic evaluation of their signal integrity characteristics at the virtual prototyping step. Our methodology is based on the following criteria: 1) a signal integrity-aware I/O interface mixed model; 2) a physical model of transmission lines to estimate signal degradation caused by the bus lines; and 3) an ICEM model to estimate the impact of a chip's internal activity on its power voltage or its I/O. Through simulations and experimental validations, we show that our methodology allows functional validation of the design and can also evaluate some low-level effects such as the influence of an embedded software instruction on the voltage drops in the power rails. View full abstract»

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  • Localized Planar EBG Structure of CSRR for Ultrawideband SSN Mitigation and Signal Integrity Improvement in Mixed-Signal Systems

    Publication Year: 2013 , Page(s): 2092 - 2100
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (4148 KB) |  | HTML iconHTML  

    In this paper, a power plane with localized planar electromagnetic bandgap (EBG) structure is designed for suppressing simultaneous switching noise (SSN) in mixed-signal systems. Nonbianisotropic complementary split ring resonator with a bandgap behavior is used to constitute the EBG cells, which are partially located on the power plane to prohibit the noise propagation within the board. An equivalent circuit model is proposed to predict the lower cutoff frequency of the transmission behavior. From the measured results, an ultrawideband mitigation of SSN from 0.26 to 25 GHz is achieved with a high suppression level of -50 dB. Furthermore, signal integrity problem is investigated, and it is found that partial discontinuities of the proposed design can reduce the influence on signal quality compared with the traditional global EBG structure. In addition, the proposed design can lower the electromagnetic interference radiation from edges of the board. View full abstract»

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  • Parallel Transient Simulation of Package/Board Power Distribution Networks Based on a 2-D Overlapping Partitioning Methodology

    Publication Year: 2013 , Page(s): 2101 - 2112
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1439 KB) |  | HTML iconHTML  

    Typical SPICE models for characterization of package/board power distribution networks (PDNs) are based on a 2-D discretization of the Helmholtz wave equation and hence require high computational costs. In this paper, a novel waveform relaxation (WR) algorithm for the parallelizable simulation of PDNs is presented. The key feature of this paper is the development of a 2-D partitioning methodology with overlapping, which addresses the slow convergence of conventional nonoverlapping-based WR algorithms for PDNs. In addition, a hybrid iterative technique is proposed that can provide additional exchange of information between the overlapping subcircuits to further improve the convergence of traditional Gauss-Jacobi-based relaxation iterations. The overall algorithm is highly parallelizable and exhibits good scaling with both the size of the circuit matrices involved and the number of CPUs available. Numerical examples are presented to illustrate the validity and efficiency of the proposed paper. View full abstract»

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  • Theoretical Study on the Rank of Integral Operators for Broadband Electromagnetic Modeling From Static to Electrodynamic Frequencies

    Publication Year: 2013 , Page(s): 2113 - 2126
    Cited by:  Papers (4)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1741 KB) |  | HTML iconHTML  

    To facilitate the broadband modeling of integrated electronic and photonic systems from static to electrodynamic frequencies, we propose an analytical approach to study the rank of the integral operator for electromagnetic analysis, which is valid for an arbitrarily shaped object with an arbitrary electric size. With this analytical approach, we theoretically prove that for a prescribed error bound, the minimal rank of the interaction between two separated geometry blocks in an integral operator, asymptotically, is a constant for 1-D distributions of source and observation points, grows very slowly with electric size as square root of the logarithm for 2-D distributions, and scales linearly with the electric size of the block diameter for 3-D distributions. We thus prove the existence of an error-bounded low-rank representation of both surface- and volume-based integral operators for electromagnetic analysis, irrespective of electric size and object shape. Numerical experiments validated the proposed analytical approach and the resultant findings on the rank of integral operators. This paper provides a theoretical basis for employing and further developing low-rank matrix algebra for accelerating the integral-equation-based electromagnetic analysis from static to electrodynamic frequencies. View full abstract»

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  • Loss Performance of Planar Interconnects on FR-4 Up to 67 GHz

    Publication Year: 2013 , Page(s): 2127 - 2133
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (707 KB) |  | HTML iconHTML  

    This paper shows the performance of planar transmission lines (TLs) on a multilayer stack-up with a flame resistant-4 (FR-4)-based core up to 67 GHz. These lines will be used as interconnects to integrate a CMOS circuit with an antenna fabricated on FR-4 for a low-cost system-in-package solution. The attenuation characteristics of coplanar waveguide (CPW), grounded coplanar waveguide (GCPW), and microstrip lines with different configurations are investigated. The peak attenuation varies from 0.15 to 0.45 dB/mm at 60 GHz, depending on the line type and geometry. In addition, the effective permittivity and loss tangent of the multilayer stack-up are determined using CPW TLs. The overall results show that FR-4-based materials are viable candidates for packaging at the millimeter-wave frequency range if suitable line lengths are utilized. View full abstract»

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  • Capacitance Calculation for Via Structures Using an Integral Equation Method Based on Partial Capacitance

    Publication Year: 2013 , Page(s): 2134 - 2146
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1123 KB) |  | HTML iconHTML  

    In this paper, a new integral equation formulation for via structures is developed for the capacitance extraction between vias and planes. The formulation is initially developed for axially symmetric geometries and then extended to axially asymmetric geometries by changing the circular ring cells to arc cells. The extended method can be used to calculate the shared-antipad via structure, which is widely used in high-speed differential signal interconnects. In addition, the image theory is used to handle inhomogeneous media, and a new technique is given to reduce computational costs for via-to-plane structures based on properties of the capacitance-matrix elements. The proposed method is validated with a commercial finite element method-based tool for several practical via structures. The extracted capacitance is also incorporated into the physics-based via model and validated with full-wave simulations. View full abstract»

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  • Broadband Microwave Frequency Characterization of 3-D Printed Materials

    Publication Year: 2013 , Page(s): 2147 - 2155
    Cited by:  Papers (4)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (3082 KB) |  | HTML iconHTML  

    3-D printing allows increased design flexibility in the fabrication of microwave circuits and devices and is reaching a level of maturity that allows for functional parts. Little is known about the RF and microwave properties of the standard materials that have been developed for 3-D printing. This paper measures a wide variety of materials over a broad spectrum of frequencies from 1 MHz to 10 GHz using a variety of well-established measurement methods. View full abstract»

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  • Ultrasonic-Assisted Thermocompression Bonding Method of Solder Anisotropic Conductive Film Joints for Reliable Camera Module Packaging

    Publication Year: 2013 , Page(s): 2156 - 2163
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1793 KB) |  | HTML iconHTML  

    In this paper, to improve the reliability of anisotropic conductive film (ACF) joints in the camera module packaging without any mechanical damages, ultrasonic-assisted thermocompression (TC) bonding was investigated using solder ACFs. This technology uses small lateral-direction ultrasonic vibration during the TC ACF bonding to break solder oxide layers for sufficient solder wetting on the electrodes at ACF joints. Bonded solder ACF joints were investigated in terms of solder ACF joint morphology, resistance, adhesion strengths, and reliabilities. In addition, the stability of camera module components after bonding process was also observed. Ultrasonic-assisted TC bonded solder ACF joints showed excellent solder wetting compared with conventional TC bonded solder ACF joints due to broken solder oxide layers by applied ultrasonic vibration. The Au contents diffused from electroless nickel immersion gold-finished Cu pads to solders was about 12 atomic% in the ultrasonic-assisted TC bonding. The Au contents were three times higher than that of the solders in the conventional TC bonding. In the ultrasonic-assisted TC bonding, ultrasonic amplitude was optimized. At the optimized amplitude, solders were well wetted and showed no mechanical damages of camera module components. Adhesion strength of ultrasonic-assisted TC bonded solder ACF joints was almost the same as that of TC bonded ACF joints due to fully cured resins in these samples. During the unbiased autoclave test (121 °, 2 atm, 100%RH), ultrasonic-assisted TC bonded ACF joints showed no open-circuit failure compared with conventional TC bonded Ni ACF joints due to metallurgical alloy joints between solder balls and electrodes by sufficient solder wetting. These results prove that ultrasonic-assisted TC bonding using solder ACFs can be applied for highly reliable ACF assembly in the camera module packaging without any mechanical damages. View full abstract»

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  • Joint Quality Affected by Electrode Contact Condition During Resistance Spot Welding

    Publication Year: 2013 , Page(s): 2164 - 2173
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1971 KB) |  | HTML iconHTML  

    The effects of electrical resistance at the workpiece-electrode contact surface or the electrode face on the joint quality, characterized by nugget shape, temperature, cooling rate, and solute concentration responsible for microstructure of the fusion zone during resistance spot welding (RSW), are systematically investigated. The model accounts for electromagnetic force, heat generation due to contact resistance at the faying surface and electrode face, and bulk resistance in the workpieces. Contact resistances composed of different features of constriction and film resistances are functions of hardness, temperature, electrode force, and surface condition. The computed results show that nugget growth and transport processes are independent of the film resistance at the electrode face. An increase in constriction resistance at the electrode face, however, decreases the onset time for nugget formation, cooling rates, and axial and radial heat transfer, and increases the electrode temperature. The workpiece is susceptible to surface melting if the parameter governing constriction resistance at the electrode face is high. Solute concentration and flow patterns affected by constriction resistance at the electrode face are also presented. View full abstract»

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  • Microelectromechanical Systems (MEMS) Resistive Heaters as Circuit Protection Devices

    Publication Year: 2013 , Page(s): 2174 - 2179
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1048 KB) |  | HTML iconHTML  

    With increased opportunities for the exploitation (i.e., reverse engineering) of vulnerable electronic components and systems, circuit protection has become a critical issue. Circuit protection techniques are generally software-based and include cryptography (encryption/decryption), obfuscation of codes, and software guards. Examples of hardware-based circuit protection include protective coatings on integrated circuits, trusted foundries, and macro-sized components that self-destruct, thus destroying critical components. This paper is the first to investigate the use of microelectromechanical systems (MEMS) to provide hardware-based protection of critical electronic components to prevent reverse engineering or other exploitation attempts. Specifically, surface-micromachined polycrystalline silicon to be used as meandering resistive heaters were designed analytically and fabricated using a commercially available MEMS prototyping service (i.e., PolyMUMPs), and integrated with representative components potentially at risk for exploitation, in this case pseudomorphic high-electron mobility transistors (pHEMTs). The MEMS heaters were initiated to self-destruct, destroying a critical circuit component and thwart a reverse engineering attempt. Tests revealed reliable self-destruction of the MEMS heaters with approximately 25 V applied, resulting in either complete operational failure or severely altering the pHEMT device physics. The prevalent failure mechanism was metallurgical, in that the material on the surface of the device was changed, and the specific failure mode was the creation of a short-circuit. Another failure mode was degraded device operation due to permanently altered device physics related to either dopant diffusion or ohmic contact degradation. The results, in terms of the failure of a targeted electronic component, demonstrate the utility of using MEMS devices to protect critical components which are otherwise vulnerable to exploitation. View full abstract»

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  • 2013 Index IEEE Transactions on Components, Packaging and Manufacturing Technology Vol. 3

    Publication Year: 2013 , Page(s): 2180 - 2220
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    Freely Available from IEEE

Aims & Scope

IEEE Transactions on Components, Packaging, and Manufacturing Technology publishes research and application articles on modeling, design, building blocks, technical infrastructure, and analysis underpinning electronic, photonic and MEMS packaging.

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Meet Our Editors

Managing Editor
R. Wayne Johnson
Auburn University