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Electron Device Letters, IEEE

Issue 12 • Date Dec. 2013

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Displaying Results 1 - 25 of 49
  • Table of contents

    Publication Year: 2013 , Page(s): C1 - 1450
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  • IEEE Electron Device Letters publication information

    Publication Year: 2013 , Page(s): C2
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  • Editorial: Kudos to our reviewers

    Publication Year: 2013 , Page(s): 1451
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  • Golden List of Reviewers for 2013

    Publication Year: 2013 , Page(s): 1452 - 1475
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  • Ultrafast AC–DC NBTI Characterization of Deep IL Scaled HKMG p-MOSFETs

    Publication Year: 2013 , Page(s): 1476 - 1478
    Cited by:  Papers (5)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1155 KB) |  | HTML iconHTML  

    Ultrafast DC and AC negative bias temperature instability (NBTI) measurements are done in high-k metal gate p-MOSFETs having deeply scaled interlayer. Time evolution of degradation during and after DC and AC stress at different duty cycle and frequency are characterized. Impact of last pulse cycle duration (half or full) and pulse low bias on AC stress are studied. Equivalence of measured data from large and small area devices are shown. Experimental results are qualitatively explained using known NBTI physical mechanism. View full abstract»

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  • First Demonstration of Junctionless Accumulation-Mode Bulk FinFETs With Robust Junction Isolation

    Publication Year: 2013 , Page(s): 1479 - 1481
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (959 KB) |  | HTML iconHTML  

    A junctionless-accumulation-mode (JAM) p-channel MOSFET is successfully implemented based on a junction-isolated bulk FinFET for the first time. The JAM devices with a fin width of 16 nm show outstanding transfer characteristics: 1) subthreshold swing (SSmin) = 68 mV/dec; 2) drain-induced-barrier-lowering is 9 mV/V; and 3) ION/IOFF ratio >1 × 106. The JAM devices with smaller fin widths or longer gate lengths give superior short-channel characteristics and higher threshold voltages (Vth) due to their enhanced gate electrostatic controllability. The reverse back bias modulates Vth and SS favorably by virtue of a body-tied device, maintaining the substrate current due to junction leakage of <;1 × 10-11 A. View full abstract»

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  • Performance Enhancement of Nanowire Tunnel Field-Effect Transistor With Asymmetry-Gate Based on Different Screening Length

    Publication Year: 2013 , Page(s): 1482 - 1484
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (820 KB) |  | HTML iconHTML  

    This letter describes an asymmetric gate tunnel field-effect transistor (AG-TFET) with a gate-all-around (GAA) structure in the source and a planar structure in the drain. It has a low OFF-state current (6.55 ×10-16 A/μm) and a high ON-state current (2.47 ×10-5 A/μm) because the screening length λ of a GAA nanowire structure is half that of the planar structure. Simulations reveal that a subthreshold swing as low as 42 mV/decade and an ON/OFF current ratio as high as 1010 are realized. The AG-TFET is easily fabricated as an actual device by simply changing the layout of gate in a general TFET fabrication. View full abstract»

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  • Investigation of Fixed Oxide Charge and Fin Profile Effects on Bulk FinFET Device Characteristics

    Publication Year: 2013 , Page(s): 1485 - 1487
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (503 KB) |  | HTML iconHTML  

    The effect of positive fixed oxide charge (Qf) on the electrical characteristics of bulk FinFET devices is investigated and newly addressed as a Fin scaling detractor. The aggressively scaled Fin width leads to abnormal subthreshold slope (SS) degradation in nMOS devices even with a long channel length, while pMOS is free of such degradation. This observation is reproduced and analyzed by a well-calibrated TCAD simulation deck with Qf introduced. A new Fin profile suppressing the Qf effect is proposed, and the benefits of the new profile are predicted in terms of variability reduction and mobility improvement, as well as Qf immunity. View full abstract»

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  • Impact of TaN as Wet Etch Stop Layer on Device Characteristics for Dual-Metal HKMG Last Integration CMOSFETs

    Publication Year: 2013 , Page(s): 1488 - 1490
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2396 KB) |  | HTML iconHTML  

    TaN as wet etch stop layer is implemented in dual-metal high- k/metal gate last integration CMOSFETs. Impacts of TaN on device characteristics are investigated. With thicker TaN, flat-band voltages (Vfb) of both n- and p-FETs shift to zero value position. Sensitivities of TaN thickness on Vfb are obtained with 81 and -114 mV/nm for n- and p-FETs, respectively. It could be served as an important enhancement tuning factor for threshold voltage (Vth) adjustment in CMOSFETs due to contributions of TaN on Vth values are in the same direction. With CMOS technology moving to below 22-nm node, it is crucial to control amount of wet etch of TaN layer, otherwise device characteristics would be impacted and double hump happens. View full abstract»

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  • Development of an Electrostatic Discharge Protection Solution in GaN Technology

    Publication Year: 2013 , Page(s): 1491 - 1493
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (411 KB) |  | HTML iconHTML  

    In this letter, a robust and effective gallium nitride (GaN)-pHEMT-based electrostatic discharge (ESD) protection structure is developed for the first time. The structure consists of a depletion-mode GaN pHEMT, a trigger diode chain, a pinchoff diode chain, and a current limiter. Results pertinent to critical ESD parameters, such as the trigger voltage, leakage current, on-state resistance, and robustness, are measured using the transmission line pulsing (TLP) tester. It is demonstrated that such an ESD clamp can sustain a TLP stress of up to 3 A. The two diode chains are found to play critical roles in determining the trigger voltage and leakage current. Increasing the trigger diode number increases the trigger voltage. On the other hand, adding more pinchoff diodes also increases the trigger voltage and simultaneously reduces the leakage current. The design tradeoffs for the proposed ESD clamp are also discussed. View full abstract»

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  • Impact of Channel Hot Electrons on Current Collapse in AlGaN/GaN HEMTs

    Publication Year: 2013 , Page(s): 1494 - 1496
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (917 KB) |  | HTML iconHTML  

    This letter studies the current collapse phenomenon during switching in p-GaN gate AlGaN/GaN high-electron-mobility transistors. It is found that channel hot electrons play a major role in increasing the current collapse and that adding a field plate significantly reduces the effect. By stressing the device with OFF-state pulses of 100 μs× 10 μs with a VGS rise/fall time of 10 ns at Vdc 400 V, compared to the ON-resistance before stress, the ON-resistance was 78 times larger after stress without field plates. With a field plate, it was only 1.8 times larger. View full abstract»

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  • High-Quality Interface in {\rm Al}_{2}{\rm O}_{3}/{\rm GaN}/{\rm GaN}/{\rm AlGaN}/{\rm GaN} MIS Structures With In Situ Pre-Gate Plasma Nitridation

    Publication Year: 2013 , Page(s): 1497 - 1499
    Cited by:  Papers (9)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (4018 KB) |  | HTML iconHTML  

    We report an in situ low-damage pre-gate treatment technology in an atomic layer deposition (ALD) system prior to the ALD- Al2O3 deposition, to realize high-quality Al2O3/III-nitride (III-N) interface. The technology effectively removes the poor quality native oxide on the III-N surface while forming an ultrathin monocrystal-like nitridation interlayer (NIL) between Al2O3 and III-N surface. With the pre-gate treatment technology, high-performance Al2O3(NIL)/GaN/AlGaN/GaN metal-insulator-semiconductor high-electron-mobility transistors are demonstrated, exhibiting well-behaved electrical characteristics including suppressed gate leakage current, a small subthreshold slope of ~64 mV/dec, and a small hysteresis of ~0.09 V. View full abstract»

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  • Impact of Gate-Aperture Overlap on the Channel-Pinch Off in InGaAs/InGaN-Based Bonded Aperture Vertical Electron Transistor

    Publication Year: 2013 , Page(s): 1500 - 1502
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (877 KB) |  | HTML iconHTML  

    A unipolar transistor consisting of an In0.53Ga0.47As (InGaAs) channel and a III-Nitride (III-N)-based drain-region with a maximum on-current of 192 mA/mm is reported. This unique device is realized by employing wafer-bonding to a current aperture vertical electron transistor and is referred to as a wafer-bonded aperture vertical electron transistor (BAVET). An In0.52Al0.48As/InGaAs layer-stack is used for the gate-barrier and channel regions, while the aperture, current-blocking-layer (CBL) and drift regions are part of the III-N layer structure. This letter investigates the factors affecting the off-characteristics of a BAVET by varying the overlaps of the gate-CBL (LGO) and gate-aperture (LGA) regions. A dual-functionality of modulating the channel and providing a field-plate effect is realized using the LGO and LGA parts of the gate, respectively. We report that the improvement in channel-pinch off is a stronger function of LGA than it is of LGO. A weak pinch off in the InGaAs channel is shown to be the consequence of impact-ionization leading to channel-breakdown, and using a gate-aperture overlap dramatically improves both the pinch off and off-state-breakdown in BAVETs. View full abstract»

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  • {\rm In}_{0.53}{\rm Ga}_{0.47}{\rm As}/{\rm GaAs}_{0.5}{\rm Sb}_{0.5} Quantum-Well Tunnel-FETs With Tunable Backward Diode Characteristics

    Publication Year: 2013 , Page(s): 1503 - 1505
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (754 KB) |  | HTML iconHTML  

    Vertical quantum-well (QW) tunnel-FETs are fabricated based on an ultrathin In0.53Ga0.47As/GaAs0.5Sb0.5 staggered gap (type-II) heterostructure lattice matched to InP. Area-dependent QW-to-QW tunneling current is demonstrated. Devices with HfO2 high- k gate dielectric (EOT ~ 1.3 nm) exhibit minimum subthreshold swings of 140 mV/decade at 300 K, with an ON-current density of 0.5 μA/μm2 at VDD=0.5 V. Sharp negative differential resistance is observed in the output characteristics. For the first time, gate-tunable backward diode characteristics are demonstrated in this material system, with peak curvature coefficient of 30 V-1 near VDS=0 V. These results show the potential of vertical TFETs in hybrid IC applications. View full abstract»

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  • Memristive Properties of Transparent ({\rm La},,{\rm Sr}){\rm MnO}_{3} Thin Films Deposited on ITO Glass at Room Temperature

    Publication Year: 2013 , Page(s): 1506 - 1508
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1028 KB) |  | HTML iconHTML  

    Amorphous La1-xSrxMnO3 (a-LSMO) thin films were deposited on indium tin oxide (ITO) glass at room temperature by radio frequency magnetron sputtering. The transmittance of a-LSMO (10 nm)/ITO/glass is 75% at 600 nm, which is promising for transparent memristors. The Ag/a-LSMO (10 nm)/ITO/glass memristor exhibits nonvolatile bipolar resistive switching properties with a resistance ratio , stable write/erase endurance , and long retention. The memristor can exhibit pinched hysteresis loops under high-frequency voltage excitations. These memristive properties are ascribed to diameter changes of the Ag nanofilament in the a-LSMO. View full abstract»

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  • Half-MOS Based Single-Poly EEPROM Cell With Program and Erase Bit Granularity

    Publication Year: 2013 , Page(s): 1509 - 1511
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (808 KB) |  | HTML iconHTML  

    A single-poly electrically erasable programmable ROM (EEPROM) cell compatible with standard CMOS process is proposed. With respect to the classical embedded NOR cell, it can be programmed and erased by Fowler-Nordheim tunneling with single-bit granularity. The memory cell is based on a novel writing-inhibition scheme enabled by the combination of the body effect with multiple half-MOS devices. Experimental results on programming, erasing, inhibition, reading, and cycling endurance are provided using a 0.13 μm standard CMOS process. View full abstract»

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  • Vertically Stacked ReRAM Composed of a Bidirectional Selector and CB-RAM for Cross-Point Array Applications

    Publication Year: 2013 , Page(s): 1512 - 1514
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    In this letter, we discuss our technique for fabricating a vertically stacked ReRAM device composed of one selector and one resistor (1S-1R). We demonstrate that the nanoscale via-hole structure and 1-kb array architecture of selector device exhibit higher current density ( ~ 107 A/cm2) and reliability, and we introduce bipolar resistive switching element-a conductive-bridge RAM that can be stacked on top of the selector device. The resulting integrated 1S-1R device performs robust bipolar switching operations and significantly reduces the leakage current in cross-point applications. View full abstract»

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  • Highly Reliable Resistive Switching Without an Initial Forming Operation by Defect Engineering

    Publication Year: 2013 , Page(s): 1515 - 1517
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1482 KB) |  | HTML iconHTML  

    The effects of stack and defect engineering of metal-oxide layers on resistive switching uniformity were investigated to obtain resistive random access memory (ReRAM) with excellent switching reliability. Uniform switching, parameters, such as set voltage (Vset), reset voltage (Vreset), low-resistance state, high-resistance state, and retention characteristics, were significantly improved by stack and defect engineering. Furthermore, the initial forming operation, which is a nuisance, was removed to realize cross-point ReRAM. View full abstract»

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  • One-Time Programmable Memory Based on {\rm ZrTiO}_{x} Antifuse for Crossbar Memory Application Featuring High Speed Operation and Low Power Consumption

    Publication Year: 2013 , Page(s): 1518 - 1520
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (625 KB) |  | HTML iconHTML  

    TaN/ZrTiOx/Pt metal-insulator-metal structure was employed as the platform to evaluate the eligibility for antifuse one-time programmable (OTP) memory applications, and the impact of O2 plasma on device performance was also discussed. Owing to the oxygen radicals that enhance the dielectric integrity, the voltage for state switching increases with O2 plasma treatment. Memory cells without plasma treatment demonstrate promising characteristics for OTP memory applications in terms of a low dc switching voltage of 2 V, high programming speed of 60 ns, high read endurance up to 106 reading cycles, and desirable retention time and low switching power density of 6.4 mW/cm2. The memory cell technology not only exhibits the prominent performance which is advantageous over other dielectrics reported in the literature, but it also possesses the capability to from stackable 3-D architecture. View full abstract»

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  • Fully Transfer Characteristic-Based Technique for Surface Potential and Subgap Density of States in p-Channel Polymer-Based TFTs

    Publication Year: 2013 , Page(s): 1521 - 1523
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (611 KB) |  | HTML iconHTML  

    We report a fully subthreshold current-based technique for characterization of subgap density of states [DOS:g(E)] with consistent mapping of the surface potential (ψS) in p-channel polymer-based thin-film transistors (PTFTS). Initially, we propose a technique for extraction of the DOS over the bandgap using the gate voltage (VGS)-dependent ideality factor [m(VGS)] from the transfer characteristics of the PTFTs under subthreshold operation. We also propose a technique for a consistent nonlinear mapping of VGS to the subgap energy level by converting m(VGS) to ψS. Through combining the two methods, the exponential tail and deep g(E) are obtained to be NTD=1·1×1017 [eV-1·cm-3], kTTD=0·035 [eV], NDD=9·8×1016 [eV-1·cm-3], and kTDD=0·80 [eV] over the bandgap. View full abstract»

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  • Single-Scan Monochromatic Photonic Capacitance-Voltage Technique for Extraction of Subgap DOS Over the Bandgap in Amorphous Semiconductor TFTs

    Publication Year: 2013 , Page(s): 1524 - 1526
    Cited by:  Papers (4)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1021 KB) |  | HTML iconHTML  

    We report a novel technique for simultaneous extraction of subgap donor- and acceptor-like density of states [gD(E) and gA(E)] over the subgap energy range (EV <;E<;EC) using a single-scan monochromatic photonic capacitance-voltage technique in n-channel amorphous indium-gallium-zinc-oxide thin-film transistors. In the proposed technique, we applied two different equivalent circuit models for the photoresponsive carriers excited from gD(E) and gA(E) under depletion (VGS <; VFB) and accumulation (VGS <; VFB) bias by employing a sub-bandgap optical source that includes a relation between photon energy (Eph) and bandgap energy (Eg) as hv = Eph <; Eg. View full abstract»

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  • NOT and NOR Logic Circuits Using Passivation Dielectric Involved Dual Gate in a-InGaZnO TFTs

    Publication Year: 2013 , Page(s): 1527 - 1529
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (776 KB) |  | HTML iconHTML  

    Dual-gate amorphous (a)-InGaZnO thin-film transistors (TFTs) are simply realized using the passivation layer of already fabricated bottom-gate TFTs as top-gate dielectric, so that an electrical biasing of either top or bottom gate may control the threshold behavior of the device. By applying a voltage to the top gate of a TFT that is serially connected to the next adjacent TFT, we could form a logic inverter with a decent voltage gain and desirable transition voltage, while a NOR logic circuit was also achieved by independent control of the dual gates. On the one hand, when both of the top and bottom gates are simultaneously controlled by single bias, our dual-gate TFT displays an excellent subthreshold swing property that leads to an excellent voltage gain in an inverter. View full abstract»

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  • Cost-Effective Integration of an a-Si:H Solar Cell and a ZnO TFT Ring Oscillator—Toward an Autonomously Powered Circuit

    Publication Year: 2013 , Page(s): 1530 - 1532
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (519 KB) |  | HTML iconHTML  

    Cost-effective integration of a-Si:H solar cells and oxide-based thin-film transistor (TFT) circuits may lead to broader battery-free device applications. We demonstrate a n-i-p a-Si:H 15-series connected solar cell that supplies power to a ZnO-based ring oscillator. The ring oscillator can operate at 28 kHz at 6 V, corresponding to ≈100 mW/cm2 illumination. This letter describes the integration and compact fabrication of the a-Si:H solar cell and ZnO TFT ring oscillator. The fabrication process includes several mask steps to reduce the number of processing steps. View full abstract»

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  • Bulk Accumulation a-IGZO TFT for High Current and Turn-On Voltage Uniformity

    Publication Year: 2013 , Page(s): 1533 - 1535
    Cited by:  Papers (7)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1109 KB) |  | HTML iconHTML  

    We present here an amorphous indium-gallium-zinc-oxide (a-IGZO) thin-film transistor (TFT) in which the accumulation layer is not only confined to the a-IGZO/gate-insulator interface, but extends the entire depth of the a-IGZO. This bulk accumulation TFT is achieved by the use of top- and bottom-gate, that are electrically tied together, resulting in drain current that is over seven times higher than that of a single-gate device, for an a-IGZO thickness of 10 nm. Thus, high drive current is achieved for a relatively small channel width due to bulk accumulation. Furthermore, being independent of carrier scattering at the interface and owing to the bulk accumulation/depletion, the subthreshold swing is always small and turn-on voltage around zero volts with device-to-device uniformity that is much better than that of single-gate TFTs. View full abstract»

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  • Low-Temperature All-Solution-Derived Amorphous Oxide Thin-Film Transistors

    Publication Year: 2013 , Page(s): 1536 - 1538
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2313 KB) |  | HTML iconHTML  

    We prepared thin-film transistors (TFTs) in which all the layers were fabricated using simple chemical solution-processed, vacuum-free routes, followed by thermal annealing at 400°C. A ruthenium oxide film prepared via low-temperature processing was used for both gate and source/drain electrodes. Amorphous lanthanum-zirconium oxide and zirconium-indium-zinc oxide films were used as the gate insulator and channel layer, respectively, which enabled the fabrication of a TFT with the desired performance at a sufficiently low temperature. The ultraviolet-ozone treatment was adopted to channel layer to facilitate precursor decomposition and condensation processes. As a result, the obtained ON/OFF ratio, subthreshold swing voltage, and channel mobility were ~ 6×105, 250 mV/decade, and 5.80 cm2V1 s-1, respectively. This result contributes to the development of sustainable completely printed inorganic electronics. View full abstract»

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IEEE Electron Device Letters publishes original and significant contributions relating to the theory, modeling, design, performance and reliability of electron devices.

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Amitava Chatterjee