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# IEEE Transactions on Electron Devices

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Displaying Results 1 - 25 of 56

Publication Year: 2013, Page(s):C1 - 3934
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• ### IEEE Transactions on Electron Devices publication information

Publication Year: 2013, Page(s): C2
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• ### An Anniversary to Celebrate!

Publication Year: 2013, Page(s):3935 - 3943
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• ### Kudos To Our Reviewers

Publication Year: 2013, Page(s): 3944
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• ### Golden List of Reviewers for 2013

Publication Year: 2013, Page(s):3945 - 3971
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• ### T-ED Retiring Editor

Publication Year: 2013, Page(s): 3972
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• ### Electroabsorption Modeling in Hydrogenated Amorphous Silicon

Publication Year: 2013, Page(s):3973 - 3978
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Measurements of electroabsorption in intrinsic hydrogenated amorphous silicon at electric fields up to 190 kV/cm in the photon energy range between 1.45 and 2.15 eV are performed, using two different methods-by measuring transmission with and without an applied dc electric field and with the use of a lock-in amplifier. A numerical model of the electroabsorption is developed, which is based on the ... View full abstract»

• ### A Phase-Change Via-Reconfigurable CMOS $LC$ VCO

Publication Year: 2013, Page(s):3979 - 3988
Cited by:  Papers (11)
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This paper demonstrates the efficacy of phase-change (PC) vias in reconfiguring RF front-end circuits for multiband/multi-standard operation. Constructed using two series-connected (SC) GeTe vias, a PC switch can be reversibly transformed between a high ROFF state and a low RON state within 1 μs. Using such PC switches to switch the inductor in a resonator, two LC voltage-controlled oscilla... View full abstract»

• ### Effect of Damage in Source and Drain on the Endurance of a 65-nm-Node NOR Flash Memory

Publication Year: 2013, Page(s):3989 - 3995
Cited by:  Papers (4)
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On 12-in wafers of 65-nm-node floating gate NOR flash memory, charge pumping measurements show that compared to those on the edge dies (type A), the devices on the central dies (type B) have more severe damage in the source (S) and drain (D) regions. In type-B devices, the worse damage is due to the generation of interface traps in the S/channel overlapping region and the generation of bulk traps ... View full abstract»

• ### Quantitative Extraction of Electric Flux in the Buried-Oxide Layer and Investigation of Its Effects on MOSFET Characteristics

Publication Year: 2013, Page(s):3996 - 4001
Cited by:  Papers (3)
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Silicon-on-insulator (SOI) MOSFETs have advantages over conventional bulk MOSFETs in terms of their electrical characteristics, but also have inherent disadvantages due to the presence of their buried-oxide (BOX) layers. In this paper, focus was placed on drain electric flux passing via the BOX layer to the body region as an influence that induces disadvantages such as drain-induced barrier loweri... View full abstract»

• ### Channel Hot Carrier Degradation Mechanism in Long/Short Channel $n$-FinFETs

Publication Year: 2013, Page(s):4002 - 4007
Cited by:  Papers (24)
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The channel hot carrier degradation mechanisms in n-FinFET devices are studied. In long channel devices, interface degradation by hot carriers mainly degrades the device at the maximum impact ionization condition (VG ~ VD/2). At higher VG closer to VD, cold and hot carrier injection to the oxide bulk defect increases and dominates at the VG=V<... View full abstract»

• ### 3-D Statistical Simulation Comparison of Oxide Reliability of Planar MOSFETs and FinFET

Publication Year: 2013, Page(s):4008 - 4013
Cited by:  Papers (14)
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New transistor architectures such as fully depleted silicon on insulator (FDSoI) MOSFETs and FinFETs have been introduced in advanced CMOS technology generations to boost performance and to reduce statistical variability (SV). In this paper, the robustness of these architectures to random telegraph noise and bias temperature instability issues is investigated using comprehensive 3-D numerical simu... View full abstract»

• ### A TCAD and Spectroscopy Study of Dark Count Mechanisms in Single-Photon Avalanche Diodes

Publication Year: 2013, Page(s):4014 - 4019
Cited by:  Papers (5)
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It is shown through dark count rate spectroscopy (DCRS) and TCAD-simulations that in single-photon avalanche diodes (SPADs), the majority of low dark count rate (DCR) devices in modern CMOS arrays are free of deep-level traps and that DCR can therefore be explained by saturation current and band-to-band tunneling (BTBT). The DCRS performed on the Megaframe 32 × 32 show that the activation e... View full abstract»

• ### Overcoming Temperature Limitations in Phase Change Memories With Optimized ${rm Ge}_{rm x}{rm Sb}_{rm y}{rm Te}_{rm z}$

Publication Year: 2013, Page(s):4020 - 4026
Cited by:  Papers (20)
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Phase change memory (PCM) is the most mature among the novel memory concepts. Embedded PCM technology can be a real breakthrough for process cost saving and performances. Nevertheless, for specific applications some improvement in high temperature data retention characteristics is needed. In this paper, we present an optimized GexSbyTez phase change material, able ... View full abstract»

• ### Realization and Scaling of ${rm Ge}{hbox{--}}{rm Si}_{1{hbox{-}}{rm x}}{rm Ge}_{rm x}$ Core-Shell Nanowire $n$-FETs

Publication Year: 2013, Page(s):4027 - 4033
Cited by:  Papers (1)
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We present the realization and scaling properties of germanium-silicon-germanium (Ge-Si1-xGex) core-shell nanowire (NW) n-type, Ω-gate field-effect transistors (FETs). The devices show superior performance to the counterparts without the Si1-xGex shell. With a channel length (Lch) of 380 nm and a diameter of 40 nm, we demonstrate a subt... View full abstract»

• ### Trans-Capacitance Modeling in Junctionless Symmetric Double-Gate MOSFETs

Publication Year: 2013, Page(s):4034 - 4040
Cited by:  Papers (9)
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We have developed a closed-form solution for trans-capacitances in long-channel junctionless double-gate (JL DG) MOSFET. This approach, which is derived from a coherent charge-based model, was fully validated with technology computer-aided design simulations. According to this paper, a complete intrinsic capacitance network is obtained, which represents an essential step toward ac analysis of circ... View full abstract»

• ### Cu/Low-$k$ Interconnect Technology Design and Benchmarking for Future Technology Nodes

Publication Year: 2013, Page(s):4041 - 4047
Cited by:  Papers (1)
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This paper investigates the performances of conventional Cu/low- k multilevel interconnect networks (MINs) for FinFETs at the 20-, 16-, 14-, 10-, and 7-nm technology nodes corresponding to the even years between 2012 and 2020, respectively. This paper captures the impacts of interconnect variables, such as size effect parameters, barrier/liner bilayer thickness, and aspect ratio on the design and ... View full abstract»

• ### Germanium–Tin P-Channel Tunneling Field-Effect Transistor: Device Design and Technology Demonstration

Publication Year: 2013, Page(s):4048 - 4056
Cited by:  Papers (27)
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We report the demonstration of germanium-tin (GeSn) p-channel tunneling field-effect transistor (p-TFET) with good device performance in terms of on-state current (Ion). With the incorporation of Sn, the conduction band minima at Γ-point of GeSn alloy shift down, increasing the direct band-to-band tunneling (BTBT) generation rate at the source-channel tunneling junction in TFET. ... View full abstract»

• ### Part I: Impact of Field-Induced Quantum Confinement on the Subthreshold Swing Behavior of Line TFETs

Publication Year: 2013, Page(s):4057 - 4064
Cited by:  Papers (22)
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Trap-assisted tunneling (TAT) is a major hurdle in achieving a sub-60-mV/decade subthreshold swing (SS) in tunnel field-effect transistors (TFETs). This paper presents an insight into the TAT process in the presence of field-induced quantum confinement (FIQC) in line TFETs. We show that the SS degradation in line TFETs is mainly caused by TAT through traps located in the bulk of the semiconductor ... View full abstract»

• ### Part II: Investigation of Subthreshold Swing in Line Tunnel FETs Using Bias Stress Measurements

Publication Year: 2013, Page(s):4065 - 4072
Cited by:  Papers (10)
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The role of trap-assisted tunneling (TAT) in the degradation of the subthreshold swing (SS) in n-type line tunnel field-effect transistors (TFETs) is investigated through the experiments and simulations. A two to fourfold increase in the interface state density is achieved by applying a positive or a negative stress between the gate and the source. The negative stress shows no impact on the SS in ... View full abstract»

• ### Effect of Surface Texture on Al–Y Codoped ZnO/n-Si Heterojunction Solar Cells

Publication Year: 2013, Page(s):4073 - 4078
Cited by:  Papers (6)
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This study fabricates Al-Y codoped ZnO (AZOY)/n-Si heterojunction (HJ) solar cells using direct current magnetron sputtering and investigates the effect of etching time (from 30 to 120 s) on photovoltaic cell properties. To explore the effects of etching time on the optoelectrical properties of AZOY thin films, the films are deposited on glass substrate and then measured using a field-emission sca... View full abstract»

• ### Experimental Investigation of the Tunneling Injection Boosters for Enhanced $I_{ON}$ ETSOI Tunnel FET

Publication Year: 2013, Page(s):4079 - 4084
Cited by:  Papers (8)
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We compare the performance of planar fully depleted silicon-on-insulator tunnel FETs (TFETs) with different tunneling boosters. The effectiveness of each of the following boosters is studied independently: low-bandgap channel or source-drain material as well as abrupt junction and ultrathin body. These boosters lead to an increase in the tunneling rate, and thus to enhanced ON current. The IO... View full abstract»

• ### Size-Dependent Effects on the Temperature Coefficient of Resistance of Carbon Nanotube Vias

Publication Year: 2013, Page(s):4085 - 4089
Cited by:  Papers (11)
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Carbon nanotube (CNT) vias were fabricated at 500 °C with different widths and lengths. The electrical resistance of the CNT vias was measured using four-point probe structures at temperatures between 25 °C and 190 °C. It was found that the temperature coefficient of resistance (TCR) of the CNT vias changes with both length and width. Most of t... View full abstract»

• ### A Physics-Based Compact Model of Metal-Oxide-Based RRAM DC and AC Operations

Publication Year: 2013, Page(s):4090 - 4097
Cited by:  Papers (47)
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A physics-based compact model of metal-oxide-based resistive-switching random access memory (RRAM) cell under dc and ac operation modes is presented. In this model, the conductive filament evolution corresponding to the resistive switching process is modeled by considering the transport behaviors of oxygen vacancies and oxygen ions together with the temperature effect. Both the metallic-like and e... View full abstract»

• ### ${rm Si}_{rm x}{rm Ge}_{1hbox{-}{rm x}}$ Epitaxial Tunnel Layer Structure for P-Channel Tunnel FET Improvement

Publication Year: 2013, Page(s):4098 - 4104
Cited by:  Papers (10)
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The tunnel field-effect transistor (FET) is a promising candidate for use in ultralow-power applications because of its distinct operation principle, namely, band to band tunneling (BTBT). However, the ON-state current of the tunnel device is extremely low because of the poor tunneling efficiency of the BTBT. In this paper, a novel epitaxial tunnel layer (ETL) structure combining vertical tunnelin... View full abstract»

## Aims & Scope

IEEE Transactions on Electron Devices publishes original and significant contributions relating to the theory, modeling, design, performance and reliability of electron and ion integrated circuit devices and interconnects.

Full Aims & Scope

## Meet Our Editors

Editor-in-Chief

Giovanni Ghione
Politecnico di Torino,
10129 Torino, Italy