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Circuits and Systems II: Express Briefs, IEEE Transactions on

Issue 11 • Date Nov. 2013

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Displaying Results 1 - 25 of 27
  • Table of contents

    Page(s): C1 - C4
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  • IEEE Transactions on Circuits and Systems—II: Express Briefs publication information

    Page(s): C2
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  • An IR-UWB Transmitter for Ranging Systems

    Page(s): 721 - 725
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (752 KB) |  | HTML iconHTML  

    This brief presents a continuous-time impulse radio ultrawideband transmitter. The transmitter is a part of a high-precision ranging single-chip transceiver that measures the time-of-flight symbol propagation. The clock burst generator in the transmitter will initiate symbol transmission in continuous time unbounded by any clock signal while maintaining an accurate chip rate during symbol transmission. Using a calibration circuit, the clock period can be programmed precisely to compensate for device mismatch. The transmitter is fabricated in Taiwan Semiconductor Manufacturing Company 90-nm CMOS technology and occupies an area of 0.123 mm2. The programmable clock range is from 12.65 to 111 MHz, and the measured rms jitter is 3.26 ps at 50 MHz. The entire transmitter has a power consumption of 1.41 mW at the data rate of 2 Mbit/s. View full abstract»

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  • A 1- to 10-GHz RF and Wideband IF Cross-Coupled Gilbert Mixer in 0.13- \mu\hbox {m} CMOS

    Page(s): 726 - 730
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    A modified Gilbert-cell mixer exhibiting both wideband radio-frequency (RF) and wideband IF performance is presented. With the proposed common-gate RF stage with the cross-coupled complementary transistors, a measured conversion gain of 3-8 dB over an RF band of 1-10 GHz is demonstrated, together with an RF input return loss better than 10 dB. The proposed mixer also incorporates wideband active local oscillator (LO) and IF baluns for matching and testing purposes. An IF bandwidth from 100 MHz to 1 GHz is achieved with a conversion gain variation of less than 2 dB. The measured output return loss within the IF band is better than 10 dB. Fabricated in a standard 0.13- μm CMOS technology, the chip only draws 7 mA from a 1.2-V supply due to the current reuse in the proposed RF stage. The measured input referred 1-dB compression point IP1-dB, third-order input intercept point IIP3, and single-sideband noise figure are better than -16 dBm, - 7 dBm, and 15 dB throughout the entire RF band. View full abstract»

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  • IIP3 Enhancement of Subthreshold Active Mixers

    Page(s): 731 - 735
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (663 KB) |  | HTML iconHTML  

    This brief presents a modified subthreshold Gilbert mixer that includes an inductor between the drain of the radio frequency (RF) transistor and the sources of the LO transistors, an inductive source degeneration for the RF transistor, and a cross-coupling capacitor between the source of the RF transistor and the drain of the RF transistor in the other mixer branch to improve third-order distortion characteristics. This linearization technique enables a third-order intermodulation intercept point (IIP3) improvement of at least 10 dB compared to other subthreshold mixers. A 2.4-GHz mixer was designed and simulated using 0.11- μm CMOS technology. In the typical corner case of the postlayout simulations, the linearized mixer achieves 6.7-dBm IIP3, 8.6-dB voltage gain, and 19.2-dB single-sideband noise figure with a low power consumption of 0.423 mW. View full abstract»

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  • K -band High-PAE Wide-Tuning-Range VCO Using Triple-Coupled LC Tanks

    Page(s): 736 - 740
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1610 KB) |  | HTML iconHTML  

    This brief presents a fully differential K-band voltage-controlled oscillator (VCO) using commercial 0.18- μm SiGe BiCMOS process. By using triple-coupled LC tanks with strong coupling and varactor-controlled capacitor bank, the proposed VCO simultaneously achieves a wide tuning range, low phase noise, high output RF power, and high power-added efficiency (PAE). The implemented VCO demonstrates an oscillation frequency range from 22.50 to 26.23 GHz, a frequency tuning range of 15.3%, a phase noise of -107.7 dBc/Hz at 1-MHz offset, an output power of -3.1 dBm, PAE of 5.97%, and a figure of merit of -186.9 dBc/Hz with a dc power of 8.2 mW. View full abstract»

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  • A Fast-Locking ADPLL With Instantaneous Restart Capability in 28-nm CMOS Technology

    Page(s): 741 - 745
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (889 KB) |  | HTML iconHTML  

    This brief presents a bang-bang all-digital phase-locked loop (ADPLL) clock generator for multiprocessor system-on-chip applications in Globalfoundries 28-nm superlow-power CMOS technology. The circuit features a single-shot phase synchronization scheme for instantaneous phase lock after power-up. This feature is used for fast frequency search during lock-in, resulting in less than 1-μs initial lock time and the capability of instantaneous restart. The ADPLL provides a wide range of output clocks from 83 MHz to 2 GHz and exhibits 31-ps accumulated jitter with 3-ps period jitter at 2 GHz. It occupies an area of only 0.00234 mm2 and consumes 0.64 mW from a 1.0-V supply. View full abstract»

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  • Fast Static Characterization of Residual-Based ADCs

    Page(s): 746 - 750
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (869 KB) |  | HTML iconHTML  

    Computationally exhaustive time-domain Monte Carlo (MC) simulations are commonly conducted to obtain the static characteristics of a residual analog-to-digital converter (ADC) (e.g., pipelined ADC) for the calculation of the integral nonlinearity (INL) and differential nonlinearity (DNL). In this brief, a new ultrahigh-speed, yet precise, behavioral-level dc characterization algorithm for residual-based ADC is introduced. The algorithm derives the transition points of a given stage of the ADC based on the random parameters of that stage. Then, it merges the dc characteristics of all stages together to extract detailed dc input-output characteristics for the entire ADC. Then, the exact amount of DNL and INL is derived. The proposed algorithm is verified by the results obtained through the conventional time-domain algorithm ran under several MC simulations. The INL and DNL of the algorithms are off by merely 1%. While the proposed algorithm obtains the INL in a few seconds, the conventional algorithm takes hours to achieve the same result. Fast calculation of the yield of the ADC is possible for a given set of values for the variance of stage parameters. View full abstract»

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  • Presilicon Circuit-Aware Linear Least Squares Spectral Analysis for Time-Based Data Converters

    Page(s): 751 - 755
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (356 KB) |  | HTML iconHTML  

    Presilicon time-based data converter spectral analysis usually incurs long simulation times. This brief shows an approach for the estimation of the data converter's spectral components and noise floor based on a small simulation window. Additionally, it provides two useful estimates of the technique's expected accuracy. The method is based on circuit-aware linear least squares spectral analysis. It can be applied together with the accuracy estimate and knowledge of the noise spectrum's shape during the design time of time-based data converters. It provides a significant advantage over classic fast Fourier transform-based techniques for time-based data converters. Both a theoretical background and simulation results are provided for a voltage-controlled oscillator (VCO)-based analog-to-digital (A/D) converter. The technique provides a good accuracy for both the spectral components and the data converter's noise floor. The accuracy estimate expresses the technique's performance, achieving a worst case error of only 5 dB, which proves its usability. View full abstract»

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  • Noise Weighting in the Design of \Delta \Sigma Modulators (With a Psychoacoustic Coder as an Example)

    Page(s): 756 - 760
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    A design flow for ΔΣ modulators is illustrated, allowing quantization noise to be shaped according to an arbitrary weighting profile. Based on finite-impulse-response noise transfer functions, possibly with high order, the flow is best suited for digital architectures. This work builds on a recent proposal in which the modulator is matched to the reconstruction filter, showing that this type of optimization can benefit a wide range of applications in which noise (including in-band noise) is known to have a different impact at different frequencies. The designs of a multiband modulator, a modulator avoiding dc noise, and an audio modulator capable of distributing quantization artifacts according to a psychoacoustic model are discussed as examples. A software toolbox is provided as a general design aid and to replicate the proposed results. View full abstract»

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  • A Single-Branch Third-Order Pole–Zero Low-Pass Filter With 0.014- \hbox {mm}^{2} Die Size and 0.8-kHz (1.25-nW) to 0.94-GHz (3.99-mW) Bandwidth–Power Scalability

    Page(s): 761 - 765
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    A single-branch third-order low-pass filter with an ultracompact die size and extensive bandwidth (BW)-power scalability is described. It unifies a source follower , a stackable floating active inductor, and a feedforward capacitor to constitute a transistorized- LC-ladder topology with a stable pole-zero transfer function over a wide range of tunable BW. Differentially, only eight transistors and five untuned capacitors are required. Fabricated in 0.18- μm CMOS, the prototype occupies 0.014- mm2 die size. By scaling the bias current (and, hence, the power), the flexible BW measures 0.8 kHz at 1.25 nW and 0.94 GHz at 3.99 mW. View full abstract»

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  • An Interface Circuit With Wide Dynamic Range for Differential Capacitive Sensing Applications

    Page(s): 766 - 770
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (989 KB) |  | HTML iconHTML  

    An interface circuit for differential capacitive sensing applications with tunable dynamic range is presented. Capacitive microsensors are ubiquitously employed in many applications pertaining to all aspects of modern life. The proposed circuit requires a small chip area and offers a good signal-to-noise ratio as well as adjustable sensitivity and dynamic range. Reference signals are produced on chip and used for the synchronous demodulation of current signals through a differential capacitive sensor. In addition to the normal open-loop operation mode of the circuit, it can be operated within a novel closed-loop configuration in order to extend its dynamic range. The circuit was designed and fabricated in a standard 0.35-μm CMOS technology from Austriamicrosystems. Experimental and simulation results are presented and discussed. The circuit is capable of resolving 0.4 fF of variation in capacitance with a 50-kHz measurement bandwidth. Reducing the bandwidth to 1 kHz for signal frequencies around 10 kHz increases the dynamic range of the closed-loop circuit to 99 and 110 dB for open-loop and closed-loop circuits, respectively. View full abstract»

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  • A 0.45-V MOSFETs-Based Temperature Sensor Front-End in 90 nm CMOS With a Noncalibrated \pm \hbox {3.5} ^{\circ}\hbox {C} \hbox {3}\sigma Relative Inaccuracy From -\hbox {55} ^{\circ}\hbox {C} to 105 ^{\circ}\hbox {C}

    Page(s): 771 - 775
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (836 KB) |  | HTML iconHTML  

    This brief presents a low-voltage subthreshold MOSFETs-based scattered relative temperature sensor that uses a simple regulated current mirror structure. NMOSFETs in the subthreshold region instead of bipolar junction transistors are used as sensing devices for low voltage purpose. Dynamic element matching is implemented to minimize the errors induced by device mismatches. The 3 × 3 sensor nodes with small size are remotely distributed across the chip, whereas the other parts are centralized and shared. Experimental results show that the minimum analog supply voltage can be 0.45 V from -55°C to 105°C in a 90-nm process implementation. The measured 3σ relative inaccuracy was less than ±3.5°C without any calibration. Furthermore, the multilocation thermal monitoring function has been experimentally demonstrated, and a 2.2°C/mm on-chip temperature gradient was detected. Compared with our previous design, superior line sensitivity and comparable relative accuracy are realized with simpler circuit implementation. View full abstract»

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  • Power-Efficient Fast Write and Hidden Refresh of ReRAM Using an ADC-Based Sense Amplifier

    Page(s): 776 - 780
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    An ADC-based current-mode sense amplifier and its usage to improve speed, power efficiency, and reliability of ReRAM are proposed. The adaptive step-size control of incremental step pulse programming enables 2.25 times faster write with 50% power. The degradation of ReRAM cells due to aging can be recovered by hidden refresh without sacrificing system performance. The test circuits are fabricated using a 350-nm technology and integrated with a 1-Kb HfOx array chip. View full abstract»

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  • Low-Area and High-Throughput Architecture for an Adaptive Filter Using Distributed Arithmetic

    Page(s): 781 - 785
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (241 KB) |  | HTML iconHTML  

    A high-performance implementation scheme for a least mean square adaptive filter is presented. The architecture is based on distributed arithmetic in which the partial products of filter coefficients are precomputed and stored in lookup tables (LUTs) and the filtering is done by shift-and-accumulate operations on these partial products. In the case of an adaptive filter, it is required that the filter coefficients be updated and, hence, these LUTs are to be recalculated. A new strategy based on the offset binary coding scheme has been proposed in order to update these LUTs from time to time. Simulation results show that the proposed scheme consumes very less chip area and operates at high throughput for large base unit size k ( = N/m) , where m is an integer and N is the number of filter coefficients. For example, a 128-tap finite-impulse-response adaptive filter with the proposed implementation produces 12 times more throughput (for k = 8) and consumes almost 26% less area when compared to the best of existing architectures. View full abstract»

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  • A Highly Time Sensitive XOR Gate for Probe Attempt Detectors

    Page(s): 786 - 790
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    Probe attempt detectors are sensors designed to protect buses of secure chips against the physical contact of probes. The operation principle of these detectors relies on the comparison of the delay propagation times between lines. CMOS XOR gates are very well suited for this comparison since they are small, fast, and compatible with the technology used in secure chips. However, the lack of activity while comparing matched lines and the limited reaction time pose a risk for tampering and decrease the sensitivity of the sensor, respectively. In this brief, a modification of a CMOS XOR gate is presented, which solves both the aforementioned problems. View full abstract»

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  • High-Performance Architecture for the Conjugate Gradient Solver on FPGAs

    Page(s): 791 - 795
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    The conjugate gradient (CG) solver is an important algorithm for solving the symmetric positive define systems. However, existing CG architectures on field-programmable gate arrays (FPGAs) either need aggressive zero padding or can only be applied for small matrices and particular matrix sparsity patterns. This brief proposes a high-performance architecture for the CG solver on FPGAs, which can handle sparse linear systems with arbitrary size and sparsity pattern. Furthermore, it does not need aggressive zero padding. Our CG architecture mainly consists of a high-throughput sparse matrix-vector multiplication design including a multi-output adder tree, a reduction circuit, and a sum sequencer. Our experimental results demonstrate that our CG architecture can achieve speedup of 4.62X-9.24X on a Virtex5-330 FPGA, relative to a software implementation. View full abstract»

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  • FPGA Implementation of Isotropic and Nonisotropic Fading Channels

    Page(s): 796 - 800
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    A realistic fading channel simulator (FCS) is a key component for the development and faithful performance evaluation of wireless communication systems. This brief presents an efficient implementation of an FCS on a single field-programmable gate array. The FCS utilizes a configurable filter processor along with a multistage interpolator for a compact implementation. The FCS can be parameterized to accurately reproduce the statistical properties of both isotropic and nonisotropic scattering scenarios. View full abstract»

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  • Insight Into a Generic Interconnect Resource Model for Xilinx Virtex and Spartan Series FPGAs

    Page(s): 801 - 805
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    With increasing scale of field-programmable gate arrays (FPGAs), the architecture of interconnect resources (IRs) in FPGAs is becoming more and more complicated. FPGAs become more vulnerable to defects during manufacturing or lifetime operation. IR testing plays an important role to guarantee correct functionality of FPGAs. This brief provides insight into a generic IR model that we developed. This IR model is a directed and weighted graph and can exhibit connection relationships among wire segments in FPGAs. Based on the generic IR model, a routing algorithm to automatically derive the minimal or near-minimal set of test configurations for IRs of Virtex and Spartan series FPGAs is also proposed. The generic IR model and associated routing algorithm are verified in Virtex, Virtex-II, Virtex-4, Virtex-5, Virtex-6, 7 Series, and Spartan series FPGAs, respectively. The experimental results demonstrate that the proposed IR model with the accompanying routing algorithm is applicable to these FPGAs with IR full coverage achieved. View full abstract»

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  • An Innovative Fast Algorithm and Structure Design for Analysis and Synthesis Quadrature Mirror Filterbanks on the SBR in DRM

    Page(s): 806 - 810
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (692 KB) |  | HTML iconHTML  

    This brief presents a novel fast algorithm derivation and structure design of analysis and synthesis quadrature mirror filterbanks (SQMFs) on the spectral band replication in Digital Radio Mondiale (DRM). After the preprocedure and postprocedure, a Fourier-transform-based computational kernel was required to construct two types of fast algorithms that offered certain advantages. The Proposed-I method employs a modified split-radix fast Fourier transform (FFT) for analysis quadrature mirror filterbank (AQMF) to reduce the number of additions at the last stage of the butterfly and adopts a split-radix FFT to calculate the SQMF coefficients. The Proposed-II method used the compact structure of the variable-length recursive DFT to realize the kernel procedure for the proposed fast AQMF and SQMF algorithms. In addition, a well-known lifting scheme was applied to reduce numerous multiplication and addition calculations. Compared with the original calculations for the long transform length, all multiplication, addition, and coefficient operations for the Proposed-I method (i.e., AQMF + SQMF) had 91.65%, 79.81%, and 97.22% reductions, respectively. However, for the Proposed-II method, the total reductions of multiplication, addition, and coefficient operations were 64.16%, 21.53%, and 97.12%, respectively. Compared with the fast SQMF algorithm by Huang , the Proposed-I method for SQMF reduces 58.33% of the multiplication, 65% of the addition, and 67.19% of the coefficients. Therefore, the proposed fast quadrature mirror filterbank algorithm is a better solution than other approaches for future DRM applications. View full abstract»

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  • Kernel Affine Projection Sign Algorithms for Combating Impulse Interference

    Page(s): 811 - 815
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    The kernel method has been successfully applied to nonlinear adaptive filtering. This brief presents a kernel affine projection sign algorithm (KAPSA), which is a nonlinear extension of the affine projection sign algorithm (APSA). The proposed KAPSA combines the benefits of the kernel method and the APSA, and is robust against non-Gaussian impulse interference. In order to further improve the filtering performance, a variable step-size adjustment is incorporated into the KAPSA, resulting in a new variable step-size kernel APSA (VSS-KAPSA) without increasing the computational burden. Simulations in the context of time-series prediction show that both the KAPSA and the VSS-KAPSA are robust against impulse interference and that both outperform other affine projection algorithms in terms of steady-state mean square errors. View full abstract»

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  • Improved Results on Statistic Information Control With a Dynamic Neural Network Identifier

    Page(s): 816 - 820
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    This brief proposes a novel statistic information tracking control framework for complex stochastic processes with a dynamic neural network (DNN) identifier and multiple dead zone actuators. The new driven information for the tracking problem is a series of statistic information sets (SISs) of the stochastic output signal. By using an adaptive method to adjust the weight matrices and to compensate the unknown parameters, a new control input is built with the Nussbaum gain matrix and feedback control gain. It is shown that both the identification errors of DNNs and the closed-loop SIS tracking errors converge to zero. Finally, a numerical example is included to illustrate the effectiveness of the theoretical results. View full abstract»

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    Page(s): 821
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    Page(s): 822
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    Page(s): 823
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Aims & Scope

TCAS II publishes brief papers in the field specified by the theory, analysis, design, and practical implementations of circuits, and the application of circuit techniques to systems and to signal processing. Included is the whole spectrum from basic scientific theory to industrial applications. The field of interest covered includes:

  • Circuits: Analog, Digital and Mixed Signal Circuits and Systems  
  • Nonlinear Circuits and Systems, Integrated Sensors, MEMS and Systems on Chip, Nanoscale Circuits and Systems, Optoelectronic
  • Circuits and Systems, Power Electronics and Systems
  • Software for Analog-and-Logic Circuits and Systems
  • Control aspects of Circuits and Systems. 

Full Aims & Scope