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IEEE Embedded Systems Letters

Issue 4 • Date Dec. 2013

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Displaying Results 1 - 13 of 13
  • Table of contents

    Publication Year: 2013, Page(s): C1
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  • IEEE Embedded Systems Letters publication information

    Publication Year: 2013, Page(s): C2
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  • Introducing New Localization and Positioning System for Aerial Vehicles

    Publication Year: 2013, Page(s):57 - 60
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (539 KB) | HTML iconHTML

    The concept of localization and positioning has received major attention as the use of UAVs is growing by day. Although there is the general method of GPS for positioning, as we will explain later, the need for alternative measures, such as new methods of localization based on visual means are growing. In this letter we present a new system based on common ubiquitous wireless and communication tra... View full abstract»

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  • Employing Symmetric Dual-Rail Logic to Thwart LPA Attack

    Publication Year: 2013, Page(s):61 - 64
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (382 KB) | HTML iconHTML

    Leakage power analysis (LPA) attacks aim at finding the secret key of a cryptographic device from measurements of its static (leakage) power. This novel power analysis attacks take advantage of the dependence of the leakage power of CMOS integrated circuits on the data they process. This letter proposes symmetric dual-rail logic (SDRL), a standard cell LPA attack countermeasure that theoretically ... View full abstract»

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  • Fast Filter-Based Boolean Matchers

    Publication Year: 2013, Page(s):65 - 68
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (713 KB) | HTML iconHTML

    Boolean matching is one of the fundamental and time-consuming procedures in field-programmable gate array (FPGA) synthesis. The SAT-based Boolean matchers (BMs) are not scalable while other Boolean matchers based on complicated Boolean logic operation algorithms are not flexible for complex PLBs. Recently, a scalable Boolean matcher (F-BM) based on the Bloom filter has been proposed for both scala... View full abstract»

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  • Hybrid Fault Detection for Adaptive NoC

    Publication Year: 2013, Page(s):69 - 72
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (529 KB) | HTML iconHTML

    This letter presents a hybrid approach to efficiently locating data packet errors in an adaptive network-on-chips (NoC). We propose to combine offline and online concepts based on a distributed and factorized online error detection module that will enable us to perform an efficient analysis of partial and localized area networks. This combination allows for an accurate localization of fault source... View full abstract»

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  • Self-Adaptive Network-on-Chip Interface

    Publication Year: 2013, Page(s):73 - 76
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (564 KB) | HTML iconHTML

    This letter presents an original approach of bandwidth-oriented self-adaptivity in the domain of network-on-chip, where reconfiguration is handled by network interfaces offering traffic with guarantee of service. Reconfiguration is first based on multiple first-in-first-outs (FIFOs) with variables bounds and implemented in a single dual-port memory with a dedicated controller. Secondly, it relies ... View full abstract»

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  • Optimization of Processor-to-Hardware Module Communications on Spaceborne Hybrid FPGA-based Architectures

    Publication Year: 2013, Page(s):77 - 80
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (521 KB) | HTML iconHTML

    Satellite on-board processing systems are becoming more important every day, thanks to recent advances in hardware architectures. SpaceCube, developed by engineers at NASA Goddard Space Flight Center and based on Virtex-5 commercial field-programmable gate arrays (FPGAs), is one such satellite on-board processing system. This letter describes how methodologies implemented on the Virtex-5 hardware ... View full abstract»

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  • 2013 List of reviewers

    Publication Year: 2013, Page(s):81 - 82
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  • 2013 Index IEEE Embedded Systems Letters Vol. 5

    Publication Year: 2013, Page(s):83 - 87
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  • myIEEE

    Publication Year: 2013, Page(s): 88
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  • IEEE Embedded Systems Letters information for authors

    Publication Year: 2013, Page(s): C3
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  • [Blank page]

    Publication Year: 2013, Page(s): C4
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Aims & Scope

The IEEE Embedded Systems Letters (ESL), provides a forum for rapid dissemination of latest technical advances in embedded systems and related areas in embedded software.

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Meet Our Editors

EDITOR-IN-CHIEF
Sri Parameswaran
School of Computer Science and Engineering
University of New South Wales

DEPUTY EDITOR-IN-CHIEF
Tulika Mitra
School of Computing
National University of Singapore