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Design & Test, IEEE

Issue 4 • Date Aug. 2013

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Displaying Results 1 - 24 of 24
  • [Front cover]

    Publication Year: 2013 , Page(s): C1
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  • [Front inside cover]

    Publication Year: 2013 , Page(s): C2
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  • [Masthead]

    Publication Year: 2013 , Page(s): 1
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  • Table of contents

    Publication Year: 2013 , Page(s): 2
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  • Table of contents

    Publication Year: 2013 , Page(s): 3
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  • A look at silicon debug and diagnosis [From the EIC]

    Publication Year: 2013 , Page(s): 4 - 5
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  • Guest Editors' Introduction: Silicon Debug and Diagnosis

    Publication Year: 2013 , Page(s): 6 - 7
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  • Linking the Verification and Validation of Complex Integrated Circuits Through Shared Coverage Metrics

    Publication Year: 2013 , Page(s): 8 - 15
    Request Permissions | Click to expandAbstract | PDF file iconPDF (691 KB)  

    This paper discusses the current state of the art in measuring validation coverage through embedded instrumentation in FPGAs and presents new instrumentation that allows any cover point to be measured. View full abstract»

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  • Evolution of Graphics Northbridge Test and Debug Architectures Across Four Generations of AMD ASICs

    Publication Year: 2013 , Page(s): 16 - 25
    Cited by:  Papers (1)
    Request Permissions | Click to expandAbstract | PDF file iconPDF (1360 KB)  

    Rapid growth in size and complexity of modern SoCs results in numerous architectural changes in design for test (DFT) and design for debug (DFD). Understanding the challenges and tracking the advances in DFT and DFD (DFx) design and architecture are essential for correct architecture planning of the next generation of SoCs. This paper provides an insight into the evolution of Graphics Northbridge ... View full abstract»

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  • Deriving Feature Fail Rate from Silicon Volume Diagnostics Data

    Publication Year: 2013 , Page(s): 26 - 34
    Cited by:  Papers (1)
    Request Permissions | Click to expandAbstract | PDF file iconPDF (842 KB)  

    In this paper, we propose expanding the use of volume diagnostics to go beyond the identification of critical features to accurately estimate their FFRs. We present a case study where FFRs of a few critical features are identified using volume diagnostics. We also compare FFRs calculated from volume diagnostics to those extracted for the same feature on test structures, which validates our present... View full abstract»

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  • Can new uses for phaser data measurements prevent blackouts? [advertisement]

    Publication Year: 2013 , Page(s): 35
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  • Dynamic Specification Testing and Diagnosis of High-Precision Sigma-Delta ADCs

    Publication Year: 2013 , Page(s): 36 - 48
    Cited by:  Papers (2)
    Request Permissions | Click to expandAbstract | PDF file iconPDF (1792 KB)  

    High-resolution ADCs generally require high-end testers to ensure their performances meeting design specifications. This paper presents new test methods that facilitate to test such devices with low-cost testers. View full abstract»

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  • A New Approach for Automatic Test Pattern Generation in Register Transfer Level Circuits

    Publication Year: 2013 , Page(s): 49 - 59
    Cited by:  Papers (1)
    Request Permissions | Click to expandAbstract | PDF file iconPDF (453 KB)  

    In this paper, we propose an approach to generate high-level test patterns from the arithmetic model of a register-transfer-level (RTL) circuit using a hybrid canonical data structure based on a decision diagram. High-level simplified and fast symbolic path activation strategy as well as input justification is combined with test pattern generation for circuits under consideration. The current appr... View full abstract»

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  • LCTI–SS: Low-Clock-Tree-Impact Scan Segmentation for Avoiding Shift Timing Failures in Scan Testing

    Publication Year: 2013 , Page(s): 60 - 70
    Request Permissions | Click to expandAbstract | PDF file iconPDF (906 KB)  

    In this contribution, the authors describe a method for ensuring that false failures do not occur when shifting scan chains for testing. Their approach identifies an optimal combination of scan segments for simultaneous clocking that reduces the switching activity near clock trees while maintaining the average power reduction for conventional scan segmentation. Experiments using various benchmark ... View full abstract»

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  • Design Methods for Parallel Hardware Implementation of Multimedia Iterative Algorithms

    Publication Year: 2013 , Page(s): 71 - 80
    Request Permissions | Click to expandAbstract | PDF file iconPDF (521 KB)  

    The methodology from this paper exploits fine and coarse-grained parallelism for the automated design of digital architectures for multimedia applications. Specific focus is placed on iterative algorithms, as demonstrated through a case study of the Chambolle algorithm for optical flow estimation. View full abstract»

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  • SAT-Based Analysis of Sensitizable Paths

    Publication Year: 2013 , Page(s): 81 - 88
    Cited by:  Papers (1)
    Request Permissions | Click to expandAbstract | PDF file iconPDF (404 KB)  

    A common trend in the past has been to detect delay defects in nanoscale technologies through the longest sensitisable paths. This approach does not hold up for non-trivial defects due to modeling inaccuracies. This article supports tests through all paths of customized length, using current SATsolving advances. View full abstract»

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  • IEEE was here

    Publication Year: 2013 , Page(s): 89
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  • CEDA Currents

    Publication Year: 2013 , Page(s): 90 - 91
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  • Discover more. IEEE Educational Activities

    Publication Year: 2013 , Page(s): 92
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  • Test Technology TC Newsletter

    Publication Year: 2013 , Page(s): 93 - 94
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  • Can semantic technologies make the Web truly worldwide? [Advertisement: IEEE Xplore Digital Library]

    Publication Year: 2013 , Page(s): 95
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  • The Most Important DFT Tool

    Publication Year: 2013 , Page(s): 96
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  • [Back inside cover]

    Publication Year: 2013 , Page(s): C3
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  • [Back cover]

    Publication Year: 2013 , Page(s): C4
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Aims & Scope

IEEE Design & Test offers original works describing the models, methods and tools used to design and test microelectronic systems from devices and circuits to complete systems-on-chip and embedded software. The magazine focuses on current and near-future practice, and includes tutorials, how-to articles, and real-world case studies. The magazine seeks to bring to its readers not only important technology advances but also technology leaders, their perspectives through its columns, interviews and roundtable discussions. Topics include semiconductor IC design, semiconductor intellectual property blocks, design, verification and test technology, design for manufacturing and yield, embedded software and systems, low-power and energy efficient design, electronic design automation tools, practical technology, and standards.  

It was published as IEEE Design & Test of Computers between 1984 and 2012.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief
Andre Ivanov
Department of Electrical and Computer Engineering, UBC