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Computers & Digital Techniques, IET

Issue 6 • Date November 2013

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Displaying Results 1 - 9 of 9
  • Special issue on emerging on-chip networks and architectures [Editorial]

    Page(s): 235 - 237
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    Freely Available from IEEE
  • A fault-tolerant core mapping technique in networks-on-chip

    Page(s): 238 - 245
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (696 KB)  

    This study proposes a fault-tolerant technique on application mapping and spare core allocation in networks-on-chip. The proposed technique sets the place of spare cores among free non-faulty processing cores, dynamically. Here, dynamically setting means that the places of spare cores are tuned for each application and are not fixed in the platform statically. Some vertices of each application core graph can be known as critical, based on their vulnerabilities, the performance degradation and the energy consumption overheads because of negative impacts of failure recovery. This technique locates the spare cores near to the critical cores. As the main theoretical contribution, the problem of spare core placement and its impression on system fault-tolerance properties is discussed. Some metrics are investigated to be considered in spare core allocation. The results of 1 000 000 fault injection experiments show that the proposed technique leads to communication energy reductions and performance improvement, compared with related works. View full abstract»

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  • HW/SW co-design of dedicated heterogeneous parallel systems: an extended design space exploration approach

    Page(s): 246 - 254
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (776 KB)  

    This work faces the problem of the hardware/software (HW/SW) co-design of dedicated electronic digital systems based on heterogeneous parallel architectures. In particular, other than describing the reference HW/SW co-design flow, it proposes an extension of a previous system-level design space exploration approach able to suggest to the designer an HW/SW partitioning of the system functionalities specification and a mapping of the partitioned entities onto an automatically defined `heterogeneous multi multi-core processor' architecture. View full abstract»

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  • Highly adaptive and deadlock-free routing for three-dimensional networks-on-chip

    Page(s): 255 - 263
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (674 KB)  

    This study proposes a new method for designing adaptive routing algorithms for three-dimensional (3D) networks-on-chip (NoCs). This method is based on extending the existing 2D turn model adaptive routing to a 3D scenario. A 3D plane-balanced approach with maximal degree of adaptiveness is achieved by applying a well-defined set of rules for different strata of the 3D NoC. The proposed method is applicable to any of the turn models. In this study, the authors employ odd-even turn model as a basis for introducing the proposed strategy. Experimental results show that the new 3D odd-even turn model can achieve up to 28.5% improvement in performance over conventional 3D odd-even approach. The improvement is consistent for different traffic types and selection strategies. The proposed method enables a new avenue to explore adaptive approaches for future large-scale 3D integration. View full abstract»

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  • Fully adaptive routing algorithms and region-based approaches for two-dimensional and three-dimensional networks-on-chip

    Page(s): 264 - 273
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    Network congestion has negative impact on the performance of networks-on-chip (NoC). In traditional congestion-aware techniques, congestion is measured at a router level and delivered to other routers, either local or non-local. One of the contributions of this study is to show that performance can be improved if the congestion level is measured for a group of routers, called cluster, and propagated over the network, rather than considering the congestion level of a single router. The presented approach is discussed in both two-dimensional (2D) and three-dimensional (3D) mesh networks. To collect and propagate the congestion information of different clusters, a distributed approach is presented. The gathered information is utilised at routing units to deliver packets through the less congested regions. To distribute packets over the network without forming deadlock, routing algorithms should be carefully designed. The authors take advantage of fully adaptive routing algorithms, providing the maximum degree of adaptiveness for distributing packets. For 2D NoCs, a conventional fully adaptive routing algorithm, named dynamic XY (DyXY), is utilised. However, for 3D NoCs a fully adaptive routing algorithm is proposed and this method is called 3D-FAR. On top of each fully adaptive routing algorithm, a region-based approach is developed. View full abstract»

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  • Temperature control in three-network on chips using task migration

    Page(s): 274 - 281
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (340 KB)  

    Combination of three-dimensional (3D) IC technology and network on chip (NoC) is an effective solution to increase system scalability and also alleviate the interconnect problem in large-scale integrated circuits. However, because of the increased power density in 3D NoC systems and the destructive effect of high temperatures on chip reliability, applying thermal management solutions becomes crucial in such circuits. In this study, the authors propose a runtime distributed migration algorithm based on game theory to balance the heat dissipation among processing elements (PEs) in a 3D NoC chip multiprocessor. The objective of this algorithm is to minimise the 3D NoC system's peak temperature, as well as the overhead imposed on chip performance during migration. Owing to the high thermal correlation between adjacent PEs in the same stack in 3D NoCs, the authors model this multi-objective problem as a cooperative game. The simulation results indicate upto 23 and 27% decrease in peak temperature, for the benchmarks that have the highest communication rate and the largest number of tasks, respectively. This comes at the price of slight migration overhead in terms of power-delay product. View full abstract»

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  • Unified multi-objective mapping and architecture customisation of networks-on-chip

    Page(s): 282 - 293
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (905 KB)  

    One of the challenging problems in networks-on-chip (NoC) design is optimising the architectural structure of the on-chip network in order to maximise the network performance while minimising the corresponding costs. In this study, a methodology for multi-objective optimisation of NoC standard architectures using Genetic Algorithms is presented. The methodology considers two cost metrics, power and area, and two performance metrics, delay and reliability. Our methodology combines the best selection of NoC standard topology, the optimum mapping of application cores onto that topology, and the best routing of application traffic traces over the generated network. The methodology is evaluated by applying it to different NoC benchmark applications as case studies. Results show that the architectures generated by our methodology outperform those of other standard architecture customisation techniques with respect to four metrics: power, area, delay and reliability, and their combination. View full abstract»

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  • Hybrid wire-surface wave interconnects for next-generation networks-on-chip

    Page(s): 294 - 303
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    Networks-on-chip (NoC) is a communication paradigm that has emerged to tackle different on-chip challenges and satisfy different demands in terms of high performance and economical interconnect implementation. However, merely metal-based NoC pursuit offers limited scalability with the relentless technology scaling especially in global communications. To meet the scalability demand, this study proposes a new hybrid architecture empowered by both metal interconnect and Zenneck surface waves interconnects (SWIs). This architecture reduces the NoC average hop count between any communication pairs, which has been reflected as a better average delay and throughput. Furthermore, SWI enables more efficient power dissipation and faster cross the chip signal propagation. The authors' initial results based on a cycle-accurate simulator demonstrate the effectiveness of the proposed system architecture, such as significant power reduction (23%), large average delay reduction (34%) and higher throughput (35%) compared with regular NoC. These results are achieved with negligible hardware and area overhead. This study explores promising potentials of SWI for future complex global communication. View full abstract»

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  • Prevention slot flow-control mechanism for low latency torus network-on-chip

    Page(s): 304 - 316
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (1048 KB)  

    The challenge for on-chip networks is to provide low latency communication in a very low power budget. To reduce the latency and maintain the simplicity of a mesh topology, torus topology is proposed. As torus topology has an inherent circular dependency, additional effort is needed to prevent deadlock, even if deadlock free routing algorithms are used. The authors propose a novel flow-control mechanism to address cost/performance constraints in torus networks and ensure deadlock freedom. They achieve flow-control by using a prevention mechanism and ensure deadlock freedom while requiring only a single packet buffer per input port. They simplify the router design by having a simple switch allocator that prioritises in-flight packets, and a single packet buffer per input port that eliminates the need for virtual channels. They also propose a mechanism to avoid starvation that can arise because of the prioritised arbitration. Experimental validation reveals that the authors design achieves significant improvement in throughput, as compared with the traditional design, while using significantly fewer buffers. View full abstract»

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Aims & Scope

IET Computers & Digital Techniques publishes technical papers describing recent research and development work in all aspects of digital system-on-chip design and test of electronic and embedded systems.

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