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Semiconductor Manufacturing, IEEE Transactions on

Issue 4 • Date Nov. 2013

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  • Table of contents

    Publication Year: 2013 , Page(s): C1 - C4
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  • IEEE Transactions on Semiconductor Manufacturing publication information

    Publication Year: 2013 , Page(s): C2
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  • Guest Editorial Special Section on the 2012 SEMI Advanced Semiconductor Manufacturing Conference

    Publication Year: 2013 , Page(s): 433 - 435
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  • Using Selective Voltage Binning to Maximize Yield

    Publication Year: 2013 , Page(s): 436 - 441
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    Yield loss associated with leakage screens is increasing as products migrate to technologies with thinner gate oxide and more aggressive lithography. Product competitiveness requires meeting low power and when products have exhausted design options, tighter than 3 sigma fast leakage screens are implemented to reduce power which can result in significant yield loss. View full abstract»

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  • Bevel RIE Application to Reduce Defectivity in Copper BEOL Processing

    Publication Year: 2013 , Page(s): 442 - 447
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    Bevel etch used during wafer fabrication for semiconductor devices is discussed. In this paper, the bevel etch process was utilized in middle of the line processing to reduce back end of line (BEOL) defectivity. Tungsten and titanium nitride films, from the formation of contacts to the transistors, extend into the bevel region of the wafer and have been shown to initiate arcing. This can spread foreign material defects on the front side of the wafer in various BEOL postprocessing steps, including subsequent reactive ion etching, SEM metrology, and film depositions. The bevel etch tool confines a plasma etch to the outer edge of the front side of the wafer (which can be individually adjusted), and can remove dielectric, organic, and Ti/TiN/W films using a fluorine based chemistry. View full abstract»

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  • Hidden Equipment Productivity Opportunities in Semiconductor Fabrication Operations

    Publication Year: 2013 , Page(s): 448 - 453
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (11896 KB) |  | HTML iconHTML  

    In this paper, we first show that true equipment utilizations may be significantly lower than what is recorded by existing monitoring systems in semiconductor fabrication operations, owing to various process and tool-related delays that occur during the tool “busy” or “running” state. We then demonstrate the use of a custom-developed system aimed at re-gaining the productivity loss, piloted at an Intel production facility for 300 mm 45 nm high volume manufacturing. Through a pilot case study, we present how these delays were reduced significantly (37% on average delay and 17-40% on variation in delay.) This improvement represents an equivalent of up to 4% improvement in true utilization on the pilot toolset, far more than any single project or even aggregation of projects on the roadmap for the toolset's availability improvement. View full abstract»

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  • Condition Monitoring and Operational Decision Making in Semiconductor Manufacturing

    Publication Year: 2013 , Page(s): 454 - 464
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    Today, the majority of semiconductor fabrication plants (fabs) conduct equipment preventive maintenance based on statistically-derived time-or wafer-count-based intervals. While these practices have had relative success in managing equipment availability and product yield, the cost, both in time and materials, remains high. Condition-based maintenance has been successfully adopted in several industries, where costs associated with equipment downtime range from potential loss of life to unacceptable affects to companies' bottom lines. In this paper, we present a method for the monitoring of complex systems in the presence of multiple operating regimes. In addition, the new representation of degradation processes will be used to define an optimization procedure that facilitates concurrent maintenance and operational decision-making in a manufacturing system. This decision-making procedure metaheuristically maximizes a customizable cost function that reflects the benefits of production uptime, and the losses incurred due to deficient quality and downtime. The new degradation monitoring method is illustrated through the monitoring of a deposition tool operating over a prolonged period of time in a major fab, while the operational decision-making is demonstrated using simulated operation of a generic cluster tool. View full abstract»

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  • Enabling Collaborative Solutions Across the Semiconductor Manufacturing Ecosystem

    Publication Year: 2013 , Page(s): 465 - 475
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1652 KB) |  | HTML iconHTML  

    A qualitative empirical study of 29 semiconductor manufacturer and supplier firms investigates the challenges associated with implementing lean practices that require broadly based collaboration across firms. The study's primary contribution is a model of the semiconductor manufacturing ecosystem, which shows how chipmakers, suppliers of enabling technologies, subsystem suppliers, and their respective competitors interact to develop the right technologies at the right time. The study finds that the biggest challenge to industry-wide collaboration is managing knowledge flows between users and suppliers in a manner that allows all parties to collaborate without losing competitive advantage. The paper also presents insights into how inter-organizational knowledge is created synchronously in the semiconductor industry. Finally, the paper makes suggestions as to how interfirm knowledge can be managed. View full abstract»

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  • Detection of Sub-Design Rule Physical Defects Using E-Beam Inspection

    Publication Year: 2013 , Page(s): 476 - 481
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (11269 KB) |  | HTML iconHTML  

    E-beam inspection provides an alternative approach to brightfield inspection for detection of otherwise difficult to detect physical defects. Advantages of E-beam inspection include superior resolution, the ability to classify defects using patch images, automatic filtering of prior level defects, and beam conditions for material contrast. For extremely small defects, which are becoming more common with each technology, brightfield inspection can fall short because of resolution limits. Either the defects are too small to even be detected or the defects are hidden among nuisance or other types of defects and cannot be binned out without SEM review. We present four examples of challenging defects that could not effectively be monitored with brightfield inspection and, therefore, were monitored with E-beam inspection. Throughput is a key limitation of E-beam inspection. Therefore, brightfield inspection should always be used for defection of physical defects when effective. To maximize the chance of success with brightfield inspection, E-beam inspection data may be used as a gold standard for development of the best optical inspection conditions. A methodology to do this is described and illustrated. View full abstract»

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  • Use of 22 nm Litho SEM Non-visual Defect Data as a Process Quality Indicator

    Publication Year: 2013 , Page(s): 482 - 487
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    This paper proposes that the non-visual defect rate for Litho layers is an indicator of the quality of the process up to and including Litho. “Non-visual” (NV) defects are those detected by optical defect inspection systems but not re-detected by the SEM review tool. The defects are occurring either on or below the surfaces of the films deposited immediately prior to lithography, or buried within the actual lithographic films. Rather than ignore the non-visual data obtained during defect inspection post lithography, the NV rate can be used as a quality indicator to trigger immediate action for root cause determination. This paper presents a new strategy for responding to Litho SEM NV defects based on a detailed study of the origin of these defects. View full abstract»

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  • Detecting Arcing Events in Semiconductor Manufacturing Equipment

    Publication Year: 2013 , Page(s): 488 - 492
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    Bi-polar arcs require a high voltage difference between two closely spaced points. As an example, if there is excessive deposition or contamination on the deposition and or cover ring in a physical vapor deposition tool (PVD) tool, a DC bipolar arc can occur leading to ablation of underlying materials, wafer breakage, or chamber damage caused by the discharge. In some cases these incidents are not identified until numerous wafers have been processed. Therefore, it is essential to identify arcing at the time of the event. In this paper, we address arc detection in a PVD chamber. The electrostatic chuck (ESC) critical parameter(s) are captured with 1000 Hz sampling frequency and signal processing techniques such as FFT and wavelet transforms are used to improve the signal-to-noise ratio enhancing the ability to isolate arcs from raw data. This methodology can be implemented on other plasma chamber types. View full abstract»

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  • Post Copper CMP Hybrid Clean Process for Advanced BEOL Technology

    Publication Year: 2013 , Page(s): 493 - 499
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (13166 KB) |  | HTML iconHTML  

    A “hybrid” post Cu CMP cleaning process that combines acidic and basic clean in sequence is developed and implemented. The new process demonstrates the strengths of both acidic and basic cleans and achieves a more than 60% reduction in CMP defects, such as polish residues, foreign materials, slurry abrasives, scratches, and hollow metal, relative to an all-basic clean process. It also eliminates the circular ring defects that occur intermittently during roller brush cleans. TXRF scans confirm the reduction of AlOx defects when using the hybrid clean process. XPS spectra show similar Cu surface oxidation states between the basic and hybrid clean processes. As revealed by XRD analysis, surface Cu oxide is dissolved into aqueous solution by the acidic clean chemical. The formation mechanism of circular ring defects and the key to their elimination is discussed. View full abstract»

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  • New Passivating Chemistries for the Deep Etching of Through Silicon Vias

    Publication Year: 2013 , Page(s): 500 - 505
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    This paper investigated a number of environmentally friendly fluorocarbon and hydrofluorocarbon (HFC) gas chemistries for sidewall passivation during time-multiplexed plasma etch processes of through-silicon vias (TSVs). The effect of plasma processing conditions on TSV etch rate, etch selectivity, and mask undercut was examined. The choice of passivating gas on TSV sidewall roughness was studied using atomic force microscopy (AFM). In addition, blanket fluorocarbon films were deposited, etched, and characterized with x-ray photoelectron spectroscopy (XPS) to study the effect of film chemistry on polymer growth and etch rates. We observed that sidewall film deposition rate, sidewall film etch rate, and degree of crosslinking in the passivating film tended to predict results of mask undercut and selectivity. Compared to octafluorocyclobutane (C4F8) processes, recipes using the four test gases generally showed a reduction in mask undercut, an increase in selectivity, and a decrease in sidewall roughness at the cost of reduced silicon etch rate. View full abstract»

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  • Performance Evaluation of Blended Metrology Schemes Incorporating Virtual Metrology

    Publication Year: 2013 , Page(s): 506 - 515
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    This paper formulates and explores the tradeoff between re-calibration and off-line metrology to find the optimal number of samples that maximizes the profit. A sequence of metrology samples using a regression model with linearly drifting coefficients is simulated, a model realistically applying to a manufacturing process with linearly drifting hidden variables. Three different types of statistical models, linear regression, exponentially-weighted linear regression (EWLR), and the Kalman Filter are used as VM prediction tools. We simulate two blended metrology sampling scenarios, one that automatically discards flagged wafers and another that allows re-inspection and process re-tuning. We alternate between training sets and testing sets, and compare the resulting net profit, Type I, and Type II errors as a function of varying VM prediction sample sizes. Results show that each VM prediction model has a different tradeoff between the Type I and Type II errors that determine the optimal sampling scheme. The ultimate goal is to create a general framework that quickly leads to the optimal design of such schemes given the characteristics of the process in question. View full abstract»

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  • Implementation of Nonthreaded Estimation for Run-to-Run Control of High Mix Semiconductor Manufacturing

    Publication Year: 2013 , Page(s): 516 - 528
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (6339 KB) |  | HTML iconHTML  

    Semiconductor processing consists of many different unit operations that are combined in a sequence to create the finished product. Many of these unit operations utilize run to run control in order to keep the process within the required manufacturing constraints. Typically, the difference, or bias, between the desired and actual result of processing a particular wafer is affected by not only the particular product being produced, but the prior processing path. Each possible effect is called a context category, and the particular context items relevant for a wafer is called a thread. Because of frequent changes and updates in semiconductor products as well as a large number of product lines, run to run control must deal with a high-mix environment of products, and a large number of threads. Previously, several authors have discussed a method of describing the bias for a particular thread as a sum of context item biases and using a Kalman Filter to estimate these biases. However, two issues with previous implementations have been the observability of the state realization of the bias model, and the computational cost of the Kalman filter. In this paper, we introduce a model formulation that does not require model reduction or the specification of special reference threads, thus easily allowing new threads to be added and old threads removed. In addition, we describe how the problem structure allows the information form of the Kalman filter to be much more computationally efficient. Simulation results illustrate the proposed method. View full abstract»

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  • Development of a 60 \mu{\rm m} Deep Trench and Refill Process for Manufacturing Si-Based High-Voltage Super-Junction Structures

    Publication Year: 2013 , Page(s): 529 - 541
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    A unique and novel, 60 μm deep trench and refill process for manufacturing Si-based Super-Junction device structures for high-voltage applications beyond 600 V is discussed on the following pages. We combine an etching-process with a DCS-HCl epitaxial growth method to achieve a homogenous refilling of the generated deep-trench structures with oppositely charged dopants. Utilizing numerical process simulations, we demonstrate the advantage of the trench and refill technological approach as compared to the more established multiple-epitaxy and implantation manufacturing method. In order to experimentally validate the homogeneity of our refilling procedure, we perform secondary electron potential contrast as well as nanoscaled scanning capacitance microscopy measurements on our fabricated micro-structures. View full abstract»

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  • Feature Analysis and Modeling of 670 nm Laser Optical Endpoint Traces in Tungsten CMP

    Publication Year: 2013 , Page(s): 542 - 548
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    The measurement of the light reflected by the surface of the wafer during process is one of the most widely used endpoint detection methods for the chemical mechanical polishing of metals. In spite of the many advantages in the process, the endpoint traces are seen just as a drop in reflectivity that marks the end of the process. In this paper, we analyze the optical endpoint traces commonly obtained during tungsten CMP and we focus our attention on different features that characterize the curve shape. Using both measurements and theoretical simulations of reflectivity of the film stack involved, we describe such characteristics and connect them to the layers being polished and to the lifetime of CMP pad installed on the equipment. In particular, we focus on a secondary peak of intensity that can be seen when the thickness of titanium nitride under tungsten increases, and on the darkening of pad window as the lifetime increases. Finally, we simulate the endpoint traces by using internal library values of optical properties of materials involved, achieving a good match between real and simulated curve. View full abstract»

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  • Re-examining Chemical Mechanical Polishing Pattern Effects Considering Slurry Selectivity

    Publication Year: 2013 , Page(s): 549 - 555
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    Chip surface topography after chemical mechanical polishing (CMP) process is determined by both process conditions and layout geometric characteristics. In Cu interconnect CMP, slurry used in P3 stage may have a higher copper remove rate or a higher dielectric remove rate, and this difference in slurry selectivity will result in different surface topography. In order to study the influence of slurry selectivity on CMP pattern effects, test chips containing different line width/space arrays are designed and they are fabricated in two typical process conditions. Surface topography of the arrays is measured by an atomic force profiler (AFP) and cross-sectional images are acquired using a scanning electron microscope (SEM) after CMP. Measurement results in two process conditions are compared, and the effects of layout geometric parameters on metal dishing are also analyzed. For large features, dishing changes obviously with density; while for small features, dishing is less affected by density. Also, a new phenomenon is observed: morphology of the copper line after P3 changes with width/space parameters. Line edges are protruding in some arrays, and this protrusion disappears in others. This phenomenon is believed to be due to different selectivity of the slurries used in P2 and P3 stages. View full abstract»

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  • Kinematic Optimization for Chemical Mechanical Polishing Based On Statistical Analysis of Particle Trajectories

    Publication Year: 2013 , Page(s): 556 - 563
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (20115 KB) |  | HTML iconHTML  

    The abrasive effect of particles is one of the basic mechanical actions in chemical mechanical polishing (CMP). In this paper, numerical simulations of particle sliding trajectories are performed to examine the influence of the kinematic parameters on the polishing uniformity of typical rotary-type CMP equipment. The trajectory simulations are carried out based on the kinematic analysis. The results reveal that the speed ratio α and the period ratio kT0, which represent the coupling relationships among the three basic motions of CMP, are the two major factors affecting the trajectory distribution. Further, a trajectory density parameter is proposed to quantitatively evaluate the global uniformity of the trajectory distributions and to optimize the kinematic parameters for better uniformity. The statistical results of the trajectory density analysis reveal that the trajectory of the wafer edge is denser than that of the wafer central area. To obtain better trajectory uniformity, some particular values of α and kT0, that is, α = 1 and kT0=1, which imply that the basic motions have a special coupling relationship, should be excluded; the preferred kinematic parameter values for CMP are α = 0.91-0.93 and kT0=5-7. This paper provides a basic guide to the kinematic parameter settings of CMP. View full abstract»

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  • Yield Learning Curve Models in Semiconductor Manufacturing

    Publication Year: 2013 , Page(s): 564 - 571
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (4340 KB) |  | HTML iconHTML  

    Semiconductor manufacturing is a constantly growing business characterized with complex production processes, advanced equipment, and volatile demand. In wafer fabrication where die are produced, good and defected die are combined on the same wafer. The proportion between good and total die, noted (die) yield, is a key performance measure in operations and has a dominant effect on manufacturing economics. Integrated circuits life cycle commonly starts with low yields that should be significantly increased and then maintained at a high level, to maximize profit. Traditional manufacturing learning curves are in the form of a power function, and exhibit decreasing cost as a function of cumulative output. This study suggests generalized multi-factor learning curves composed of power and exponential functions of cumulative output, elapsed time, and production rate. It presents a unique approach to develop compound yield learning model as a product of individual steps yield learning curves, rather than displaying total yield in former models. The proposed single step yield learning curve applies more suitable exponential function, and the compound yield product-form model illustrates sigmoid shape curve which better coincides with practice. These models provide yield forecasting tools for improving short term operations planning and supply chain efficiency, and for setting strategic directions for wafer fabrication economics. View full abstract»

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  • Temperature Distribution and Deposition Rate on Semiconductor Wafers in Low-Pressure CVD Equipment Processing Two Wafers

    Publication Year: 2013 , Page(s): 572 - 577
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (7677 KB) |  | HTML iconHTML  

    We studied hot-wall-type low-pressure chemical vapor deposition (LPCVD) equipment processing two wafers. The temperature distribution of the wafers and deposition rate of Si3N4 film in the LPCVD equipment were experimentally measured by changing parameters at 50 °C.Results showed that the steady-state temperature deviation of the two wafers was within ±1.0°C. Change of wafer temperature during a continual heating process was 0.7 °C by using the feed-forward control (FFC) method, which is less than half of that without the FFC method. The change of the deposition rate of the wafers during a continual deposition process was within 2% by using the FFC control method. The deviation of the deposition rate was reduced to ±1.3% by using the flip-flop flow of the process gas, which is 14% of that without the flip-flop flow. View full abstract»

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  • Petri Net-Based Optimal One-Wafer Scheduling of Single-Arm Multi-Cluster Tools in Semiconductor Manufacturing

    Publication Year: 2013 , Page(s): 578 - 591
    Cited by:  Papers (9)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (5070 KB) |  | HTML iconHTML  

    In operating a multi-cluster tool, it needs to coordinate the activities of multiple robots. Thus, it is very challenging to schedule it. This paper conducts a study on one-wafer cyclic scheduling for multi-cluster tools whose bottleneck cluster tool is process-bound. The system is modeled by a Petri net. With this model, conditions under which a one-wafer cyclic schedule exists are developed. Based on them, it is shown that, for any multi-cluster tool whose bottleneck cluster tool is process-bound, there is always a one-wafer cyclic schedule. Then, a method is presented to find the minimal cycle time and the optimal one-wafer cyclic schedule. It is computationally efficient. Illustrative examples are used to show the applications and effectiveness of the proposed method. View full abstract»

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  • Scheduling Lot Switching Operations for Cluster Tools

    Publication Year: 2013 , Page(s): 592 - 601
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (10600 KB) |  | HTML iconHTML  

    A cluster tool that consists of several processing modules, a transport robot, and loadlocks is widely used for wafer processing in the semiconductor industry. The cluster tool repeats an identical operational sequence for processing wafers in a lot, and such a cyclic operation sequence is determined by the wafer flow pattern and process times of a wafer lot. When a wafer lot changes, the tool operation sequence should be switched accordingly. Switching from a cyclic tool operation sequence to another is subject to deadlocks and unnecessary task delays to avoid scheduling complexity. Hence, it is necessary to have a scheduling method for such frequent lot switchings that prevents a deadlock and reduces the switching time. In this paper, we first develop a Petri net model for lot switching operations and then utilize a mixed integer programming model for an optimal schedule. However, since its practical value is limited, we develop effective heuristic methods for lot switching in single-armed and dual-armed cluster tools. The scheduling strategies adapt prevalent cyclic tool scheduling rules, such as backward and swap sequences. By computational experiments, we prove the efficiency and effectiveness of the proposed scheduling rules. View full abstract»

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  • Planning Wafer Starts Using Nonlinear Clearing Functions: A Large-Scale Experiment

    Publication Year: 2013 , Page(s): 602 - 612
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    The nonlinear, circular dependency between workload and cycle times for production resources governed by queueing behavior has been a longstanding difficulty in the production planning domain. The issue is particularly important for semiconductor wafer fabrication facilities, which must operate at relatively high utilization to be profitable. Nonlinear clearing functions that relate the expected output of a resource in a planning period to the amount of work available to it have been proposed as an alternative approach. While computational tests on small systems have been promising, the question of whether the results remain valid for large-scale systems has remained open. In this paper we evaluate the performance of a clearing function based production planning model using a simulation of a large-scale wafer fab with two products and several hundred operations. Results indicate that, consistent with the results of previous experiments, the clearing function model yields substantial improvements in profit over conventional linear programming models. View full abstract»

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  • On Improving the Predictability of Cycle Time in an NVM Fab by Correct Segmentation of the Process

    Publication Year: 2013 , Page(s): 613 - 618
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    Based on a simulated fab, we first show that forecasting the steady state cycle time of process segments is possible based on certain segment characteristics. We then show that the cycle time predictability is highly dependent on the choice of the segmentation, with the more efficient segmentation corresponding to the product layers. View full abstract»

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Aims & Scope

The IEEE Transactions on Semiconductor Manufacturing addresses the challenging problems of manufacturing complex microelectronic components.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief

Anthony Muscat
Department of Chemical and Environmental Engineering
Harshbarger Bldg., Room 134
1133 E. James Rogers Way
University of Arizona
Tucson, AZ  85721