IEEE Transactions on Electron Devices

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Publication Year: 2013, Page(s):C1 - 3610
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• IEEE Transactions on Electron Devices publication information

Publication Year: 2013, Page(s): C2
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• Comparative Simulation Analysis of Process-Induced Variability in Nanoscale SOI and Bulk Trigate FinFETs

Publication Year: 2013, Page(s):3611 - 3617
Cited by:  Papers (16)
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This paper presents a comprehensive simulation study of the process and statistical variability in 16-nm technology node bulk and silicon-on-insulator (SOI) fin field effect transistors (FinFETs). The devices are carefully designed to offer good manufacturability while meeting the performance requirements of the 16-nm technology. First, the sensitivity of the two types of FinFETs to process- induc... View full abstract»

• Energy Landscape Model of Conduction and Phase Transition in Phase Change Memories

Publication Year: 2013, Page(s):3618 - 3624
Cited by:  Papers (4)
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Conduction and switching in the phase-change memory (PCM) strongly depend on the transport mechanisms in the disordered amorphous phase. To predict the programming characteristics and the scaling behavior of PCM, accurate models for transport in the amorphous phase considering the local disorder are essential. This paper presents a numerical model to study the subthreshold conduction in the amorph... View full abstract»

• Robust ESD Protection Design for 40-Gb/s Transceiver in 65-nm CMOS Process

Publication Year: 2013, Page(s):3625 - 3631
Cited by:  Papers (4)
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To protect a 40-Gb/s transceiver from electrostatic discharge (ESD) damages, a robust ESD protection design has been proposed and realized in a 65-nm CMOS process. In this paper, diodes are used for ESD protection and inductors are used for high-speed performance fine tuning. Experimental results of the test circuits have been successfully verified, including high-speed performances and ESD robust... View full abstract»

• Off-State Stress Degradation Analysis and Optimization for the High-Voltage SOI-pLEDMOS With Thick Gate Oxide

Publication Year: 2013, Page(s):3632 - 3638
Cited by:  Papers (5)
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In this paper, the off-state stress degradation for the high-voltage p-type lateral extended drain MOS (pLEDMOS) based on the silicon-on-insulator (SoI) substrate with the thick gate oxide has been investigated experimentally. It shows that, during the stress, there are interface states and negative oxide-trapped charges at the polygate terminal region, but the negative oxide-trapped charges are i... View full abstract»

• Effects of Fin Width on Device Performance and Reliability of Double-Gate n-Type FinFETs

Publication Year: 2013, Page(s):3639 - 3644
Cited by:  Papers (12)
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This paper investigates the impact of fin width ( Wfins = 15, 20, and 25 nm) in a double-gate n-type FinFET on the performance and reliability of the device. Carrier conduction in the Si-fin body of FinFETs with various Wfins is also studied. The experimental results show that the threshold voltage and drain current of n-type FinFETs increases and decreases, respectively, as ... View full abstract»

• Compact Modeling of Statistical BTI Under Trapping/Detrapping

Publication Year: 2013, Page(s):3645 - 3654
Cited by:  Papers (24)
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The aging process due to negative bias temperature instability (NBTI) is a key limiting factor of circuit lifetimes in CMOS design. Recent NBTI data exhibits an excessive amount of randomness and fast recovery, which are difficult to be handled by conventional power-law model (tn). Such discrepancies further pose the challenge on long-term reliability prediction under statistical variat... View full abstract»

• Subthreshold Behavior Models for Nanoscale Short-Channel Junctionless Cylindrical Surrounding-Gate MOSFETs

Publication Year: 2013, Page(s):3655 - 3662
Cited by:  Papers (36)
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With the exact solution of the 2-D Poisson's equation in cylindrical coordinates, analytical subthreshold behavior models for junctionless cylindrical surrounding-gate (JLCSG) MOSFETs are developed. Using these analytical models, subthreshold characteristics of JLCSG MOSFETs are investigated in terms of channel electrostatic potential distribution, subthreshold current, and subthreshold slope (SS)... View full abstract»

• Performance Dependence on Width-to-Length Ratio of Si Cap/SiGe Channel MOSFETs

Publication Year: 2013, Page(s):3663 - 3668
Cited by:  Papers (2)
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This paper measures the n- and p-MOSFETs fabricated through 65-nm high- k/metal gate CMOSFET process flow. The [110] channels of the Si cap on SiGe with different width (W) and length (L) ratios were compared with Si-only channels. The results show that a high W-L ratio in the [110] n-channel can alleviate the degradation of biaxial compressive stress. Meanwhile, a low W-L ratio in the p-channel c... View full abstract»

• Investigations on Line-Edge Roughness (LER) and Line-Width Roughness (LWR) in Nanoscale CMOS Technology: Part I–Modeling and Simulation Method

Publication Year: 2013, Page(s):3669 - 3675
Cited by:  Papers (16)
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In this paper, the correlation between line-edge roughness (LER) and line-width roughness (LWR) is investigated. Based on the characterization methodology of auto-correlation functions (ACF), a new theoretical model of LWR is proposed, which indicates that the LWR ACF is composed of two parts: one involves LER information; the other involves the cross-correlation of the two edges. Additional chara... View full abstract»

• Investigations on Line-Edge Roughness (LER) and Line-Width Roughness (LWR) in Nanoscale CMOS Technology: Part II–Experimental Results and Impacts on Device Variability

Publication Year: 2013, Page(s):3676 - 3682
Cited by:  Papers (17)
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In the part I of this paper, the correlation between line-edge roughness (LER) and line-width roughness (LWR) is investigated by theoretical modeling and simulation. In this paper, process-dependence of the correlation between LER and LWR is studied. The experimental results indicate that both Si Fin and nanowire have strongly correlated LER/LWR, and the cross-correlation of two edges depends on t... View full abstract»

• Intrinsic Time Zero Dielectric Breakdown Characteristics of HfAlO Alloys

Publication Year: 2013, Page(s):3683 - 3689
Cited by:  Papers (4)
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A thermochemical model describing the relationship between the dielectric breakdown field (EBD) and dielectric constant (k) of high- k dielectric has been calibrated for HfxAl1-xOy alloys with k values from 7 to 24. Metal-insulator-metal (MIM) capacitors with HfxAl1-xOy high- k dielectric films were used to extract the intrinsic tim... View full abstract»

• A Thermally Stable and High-Performance 90-nm ${rm Al}_{2}{rm O}_{3}backslash{rm Cu}$-Based 1T1R CBRAM Cell

Publication Year: 2013, Page(s):3690 - 3695
Cited by:  Papers (40)
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In this paper, we optimize the stack of a 90-nm CMOS-friendly WAl2O3Cu conductive-bridging random access memory cell integrated in the one-transistor/one-resistor configuration. We show that the excellent Cu buffering properties of a TiW layer inserted at the Al2O3Cu interface make it possible, on one hand, to ensure cell integrity after back-end-of-line... View full abstract»

• Tri-Mode Independent Gate FinFET-Based SRAM With Pass-Gate Feedback: Technology–Circuit Co-Design for Enhanced Cell Stability

Publication Year: 2013, Page(s):3696 - 3704
Cited by:  Papers (11)
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We present 6T SRAMs with pass-gate feedback using tri-mode independent gate (TMIG) FinFETs as the access transistors. We perform a comprehensive analysis of TMIG FinFETs and the proposed SRAM cell using our simulation framework, which is based on the non-equilibrium Green's function models for FinFETs. We compare our technique with the tied gate (TG) FinFET SRAM and the previously proposed indepen... View full abstract»

• Analytical Modeling of a Double Gate MOSFET Considering Source/Drain Lateral Gaussian Doping Profile

Publication Year: 2013, Page(s):3705 - 3709
Cited by:  Papers (16)
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As the MOSFET is scaled into a nanoscale regime, spreading of source/drain (S/D) dopant into the channel region will facilitate the lateral electric field spread into the channel and in turn deteriorate the gate electrostatic integrity. The short channel effects and performance are aggravated with the increase in lateral straggle (σL) of S/D Gaussian profile. In this paper, we ha... View full abstract»

• Parasitic Gate Capacitance Model for Triple-Gate FinFETs

Publication Year: 2013, Page(s):3710 - 3717
Cited by:  Papers (18)
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Triple-gate FinFETs have demonstrated to be promising candidates to push further the performance limits of the microelectronics industry, thanks to their high immunity to short-channel effects. However, owing to their 3-D nature, high parasitic gate capacitances appear that dramatically degrade their high-speed digital and analog/RF performances. Thus, in order to meet the International Technology... View full abstract»

• Measurements of Silicon Photomultipliers Responsivity in Continuous Wave Regime

Publication Year: 2013, Page(s):3718 - 3725
Cited by:  Papers (10)
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We report on the electrical and optical characterization, in continuous wave regime, of a novel class of silicon photomultipliers fabricated in standard planar technology on a silicon p-type substrate. Responsivity measurements, performed with an incident optical power down to tenths of picowatts, at different reverse bias voltages and on a broad (340-820 nm) spectrum, will be shown and discussed.... View full abstract»

• CMOS Small-Signal and Thermal Noise Modeling at High Frequencies

Publication Year: 2013, Page(s):3726 - 3733
Cited by:  Papers (12)
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In this paper, the behavior of radio frequency (RF) CMOS noise up to 24 GHz is analyzed and verified with measurements over a wide range of bias voltages and channel lengths. For the first time, approaches for excess noise factor modeling are validated versus measurements. Furthermore, important RF CMOS figures of merit are examined over many CMOS generations. With the scaling of CMOS technology, ... View full abstract»

• Spin Transport in Bilayer Graphene Armchair Nanoribbon: A Monte Carlo Simulation Study

Publication Year: 2013, Page(s):3734 - 3740
Cited by:  Papers (2)
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In this paper, we study the spin relaxation in bilayer armchair graphene nanoribbons (acGNRs) by employing the semiclassical Monte Carlo approach. D'yakonov-Perel relaxation due to structural inversion asymmetry (Rashba spin-orbit coupling) and Elliott-Yafet relaxation cause spin dephasing in bilayer GNRs. We investigate the spin relaxation in bilayer α-, β-, and γ-acGNRs with... View full abstract»

• Influence of Implantation Damages and Intrinsic Dislocations on Phosphorus Diffusion in Ge

Publication Year: 2013, Page(s):3741 - 3745
Cited by:  Papers (2)
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Influence of the implant-induced damages and the threading dislocations during germanium (Ge) epitaxy was investigated on the phosphorus diffusion in Ge. An adequate n-type junction was formed by 650°C rapid thermal annealing of the implanted bulk Ge. It is observed that for epitaxial Ge on Si substrate, there was an enhanced local phosphorus diffusion approaching the Ge/Si interface. A dif... View full abstract»

• Compact Charge-Based Physical Models for Current and Capacitances in AlGaN/GaN HEMTs

Publication Year: 2013, Page(s):3746 - 3752
Cited by:  Papers (19)
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This paper presents physics-based compact models for the C-V and I-V characteristics of AlGaN/GaN HEMT devices. The contribution of only the first energy level in the triangular quantum well at the AlGaN/GaN interface (where most of the charge carriers of the 2-DEG channel reside) is considered, which resulted in an accurate and simple unified charge control model. Based on this, analytical models... View full abstract»

• Improved Quantum Efficiency in Semipolar $(1bar{1}01)$ InGaN/GaN Quantum Wells Grown on GaN Prepared by Lateral Epitaxial Overgrowth

Publication Year: 2013, Page(s):3753 - 3759
Cited by:  Papers (5)
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We investigated the comparative structural and optical properties of semipolar InGaN/GaN multiple quantum wells (MQWs) grown on the (1̅101) facet GaN/sapphire substrate by metal-organic chemical vapor deposition using lateral epitaxial overgrowth. The scanning electron microscopy (SEM), photoluminescence (PL), and temperature-varying time-resolved photoluminescence measurement were performe... View full abstract»

• Statistical Model and Rapid Prediction of RRAM SET Speed–Disturb Dilemma

Publication Year: 2013, Page(s):3760 - 3766
Cited by:  Papers (26)
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A comprehensive study of SET speed-disturb dilemma in resistive-switching random access memory (RRAM) is presented using statistically based prediction methodologies, accounting for the stochastic nature of SET. An analytical percolation model has been successful in explaining the statistical Weibull distribution of SET time and SET voltage in addition to the power-law voltage-time dependence. Two... View full abstract»

• Evidence for Non-Arrhenius Kinetics of Crystallization in Phase Change Memory Devices

Publication Year: 2013, Page(s):3767 - 3774
Cited by:  Papers (16)
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The programming speed in a phase change memory (PCM) relies on the kinetics of crystallization in the pulsed regime. To predict the programming speed and retention of a PCM, a careful understanding and modeling of crystallization in the phase change material is essential. In this paper, we study crystallization kinetics directly in PCM devices. From thermal annealing and pulsed-set experiments, we... View full abstract»

Aims & Scope

IEEE Transactions on Electron Devices publishes original and significant contributions relating to the theory, modeling, design, performance and reliability of electron and ion integrated circuit devices and interconnects.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief

Giovanni Ghione
Politecnico di Torino,
10129 Torino, Italy