# IEEE Transactions on Very Large Scale Integration (VLSI) Systems

## Filter Results

Displaying Results 1 - 25 of 28

Publication Year: 2013, Page(s):C1 - C4
| |PDF (418 KB)
• ### IEEE Transactions on Very Large Scale Integration (VLSI) Systems publication information

Publication Year: 2013, Page(s): C2
| |PDF (136 KB)
• ### Implementing Flexible Reliability in a Coarse-Grained Reconfigurable Architecture

Publication Year: 2013, Page(s):2165 - 2178
Cited by:  Papers (14)
| |PDF (3608 KB) | HTML

This paper proposes a coarse-grained dynamically reconfigurable architecture that offers flexible reliability to deal with soft errors and aging. The notion of a cluster is introduced as a basic architectural element; each cluster can select four operation modes with different levels of spatial redundancy and area efficiency. We evaluate the aging effect due to negative bias temperature instabilit... View full abstract»

• ### SPREAD: A Streaming-Based Partially Reconfigurable Architecture and Programming Model

Publication Year: 2013, Page(s):2179 - 2192
Cited by:  Papers (14)
| |PDF (2709 KB) | HTML

Partially reconfigurable systems are promising computing platforms for streaming applications, which demand both hardware efficiency and reconfigurable flexibility. To realize the full potential of these systems, a streaming-based partially reconfigurable architecture and unified software/hardware multithreaded programming model (SPREAD) is presented in this paper. SPREAD is a reconfigurable archi... View full abstract»

• ### Multiplierless Algorithm for Multivariate Gaussian Random Number Generation in FPGAs

Publication Year: 2013, Page(s):2193 - 2205
Cited by:  Papers (2)  |  Patents (1)
| |PDF (1218 KB) | HTML

The multivariate Gaussian distribution is used to model random processes with distinct pair-wise correlations, such as stock prices that tend to rise and fall together. Multivariate Gaussian vectors with length n are usually produced by first generating a vector of n independent Gaussian samples, then multiplying with a correlation inducing matrix requiring O(n2) multiplications. This p... View full abstract»

• ### Time-Interleaved and Circuit-Shared Dual-Channel 10 b 200 MS/s 0.18 $mu{rm m}$ CMOS Analog-to-Digital Convertor

Publication Year: 2013, Page(s):2206 - 2213
Cited by:  Papers (7)
| |PDF (1522 KB) | HTML

This paper proposes a 10 b 200 MS/s pipeline analog-to-digital convertor (ADC) for high-quality video systems based on double-channel and op-amp sharing schemes to minimize power consumption and channel mismatch. The double channel time-interleaved scheme reduces the required operating speed of amplifiers in the sample-and-hold amplifier and multiplying digital-to-analog (D/A) converters by 50%. T... View full abstract»

• ### Variation-Aware Aging Analysis in Digital ICs

Publication Year: 2013, Page(s):2214 - 2225
Cited by:  Papers (2)
| |PDF (1687 KB) | HTML

As CMOS devices become smaller, the process variations (PVs) and aging variations (AVs) become major issues for circuit reliability and yield. In this paper, we analyze the effects of PVs on aging effects such as hot carrier injection (HCI) and negative bias temperature instability (NBTI). Using Monte Carlo-based transistor-level simulations including principal component analysis, the correlations... View full abstract»

• ### Timing Uncertainty in 3-D Clock Trees Due to Process Variations and Power Supply Noise

Publication Year: 2013, Page(s):2226 - 2239
Cited by:  Papers (7)
| |PDF (2572 KB) | HTML

Clock distribution networks are affected by different sources of variations. The resulting clock uncertainty significantly affects the frequency of a circuit. To support this analysis, a statistical model of skitter, which consists of clock skew and jitter, for 3-D clock trees is introduced. The effect of skitter on both the setup and hold time slacks is modeled. The variation of skitter is shown ... View full abstract»

• ### Process-Resilient Low-Jitter All-Digital PLL via Smooth Code-Jumping

Publication Year: 2013, Page(s):2240 - 2249
Cited by:  Papers (4)
| |PDF (1167 KB) | HTML

For an all-digital phase-locked loop, the frequency range supported is often segmented, and this could cause significant jitter when the operating condition (such as the supply voltage and/or the temperature) changes. To address this issue, we present a scheme, called smooth code-jumping, that can stitch together the segmented frequency profile of a digitally controlled oscillator (DCO) into a con... View full abstract»

• ### Near-Field Communication Transceiver System Modeling and Analysis Using SystemC/SystemC-AMS With the Consideration of Noise Issues

Publication Year: 2013, Page(s):2250 - 2261
Cited by:  Papers (7)
| |PDF (2043 KB) | HTML

SystemC, as a C++-based hardware description language, is used for system architecture design, large digital hardware, software, and their interaction. Its extension, SystemC-AMS, provides the capability of abstract modeling to deliver analog system-level simulation of “real-time” application scenarios. SystemC and SystemC-AMS help designers to analyze a whole mixed-signal system and... View full abstract»

• ### VLSI Implementation of a Soft-Output Signal Detector for Multimode Adaptive Multiple-Input Multiple-Output Systems

Publication Year: 2013, Page(s):2262 - 2273
Cited by:  Papers (3)
| |PDF (1210 KB) | HTML

This paper presents a multimode soft-output multiple-input multiple-output (MIMO) signal detector that is efficient in hardware cost and energy consumption. The detector is capable of dealing with spatial-multiplexing (SM), space-division-multiple-access (SDMA), and spatial-diversity (SD) signals of 4 × 4 antenna and 64-QAM modulation. Implementation-friendly algorithms, which reuse most of... View full abstract»

• ### A 5-Gb/s Automatic Sub-Bit Between-Pair Skew Compensator for Parallel Data Communications in 0.13-$mu{rm m}$ CMOS

Publication Year: 2013, Page(s):2274 - 2285
| |PDF (1772 KB) | HTML

This paper presents a between-pair skew (BPS) compensator for parallel data communications. It can detect time skew between two independent data sequences using continuous-time correlations and then automatically align the two using a wide-bandwidth voltage controlled data delay line. A 5-Gb/s sub-bit BPS compensator in 0.13- μm CMOS occupies approximately 0.038- mm2 active die a... View full abstract»

• ### Faults Affecting Energy-Harvesting Circuits of Self-Powered Wireless Sensors and Their Possible Concurrent Detection

Publication Year: 2013, Page(s):2286 - 2294
| |PDF (862 KB) | HTML

We analyze the effects of faults on an energy-harvesting circuit (EHC) providing power to a wireless biomedical multisensor node. We show that such faults may prevent the EHC from producing the power supply voltage level required by the multisensor node. Then, we propose a low-cost (in terms of power consumption and area overhead) additional circuit monitoring the voltage level produced by the EHC... View full abstract»

• ### Hardware Designer's Guide to Fault Attacks

Publication Year: 2013, Page(s):2295 - 2306
Cited by:  Papers (27)
| |PDF (538 KB) | HTML

Hardware designers invest a significant design effort when implementing computationally intensive cryptographic algorithms onto constrained embedded devices to match the computational demands of the algorithms with the stringent area, power, and energy budgets of the platforms. When it comes to designs that are employed in potential hostile environments, another challenge arises-the design has to ... View full abstract»

• ### Timing Measurement Platform for Arbitrary Black-Box Circuits Based on Transition Probability

Publication Year: 2013, Page(s):2307 - 2320
Cited by:  Papers (2)
| |PDF (1272 KB) | HTML

The key aspects of a good on-chip timing measurement platform are high measurement resolution, accuracy, and low area overhead. A measurement method based on transition probability (TP) has shown promising characteristics in all these areas. In this paper, the TP measurement method is examined through simulation to understand its apparent effectiveness and accuracy in measuring complex circuits. T... View full abstract»

• ### Functional Broadside Templates for Low-Power Test Generation

Publication Year: 2013, Page(s):2321 - 2325
Cited by:  Papers (1)
| |PDF (173 KB) | HTML

This brief describes a new approach to low-power test generation targeting the maximum switching activity during the fast functional clock cycles of broadside tests. This brief defines functional broadside templates as incompletely-specified broadside tests, which capture the signal-transitions that occur during the fast functional clock cycles of functional broadside tests. The same signal-transi... View full abstract»

• ### Parallelization of Radix-2 Montgomery Multiplication on Multicore Platform

Publication Year: 2013, Page(s):2325 - 2330
Cited by:  Papers (4)
| |PDF (317 KB) | HTML

Montgomery multiplication is the kernel operation in public key ciphers. Aiming at parallel implementation of Montgomery multiplication, this brief presents an improved task partitioning of the Montgomery multiplication algorithm for the multicore platform with area-efficient processors. Several multicore platforms are designed to verify the efficiency of parallelization. The fastest platform take... View full abstract»

• ### Novel Architecture for Efficient FPGA Implementation of Elliptic Curve Cryptographic Processor Over ${rm GF}(2^{163})$

Publication Year: 2013, Page(s):2330 - 2333
Cited by:  Papers (21)
| |PDF (292 KB) | HTML

A new and highly efficient architecture for elliptic curve scalar point multiplication is presented. To achieve the maximum architectural and timing improvements, we reorganize and reorder the critical path of the Lopez-Dahab scalar point multiplication architecture such that logic structures are implemented in parallel and operations in the critical path are diverted to noncritical paths. The res... View full abstract»

• ### Concurrent Error Detection for Orthogonal Latin Squares Encoders and Syndrome Computation

Publication Year: 2013, Page(s):2334 - 2338
Cited by:  Papers (11)
| |PDF (314 KB) | HTML

Error correction codes (ECCs) are commonly used to protect memories against errors. Among ECCs, orthogonal latin squares (OLS) codes have gained renewed interest for memory protection due to their modularity and the simplicity of the decoding algorithm that enables low delay implementations. An important issue is that when ECCs are used, the encoder and decoder circuits can also suffer errors. In ... View full abstract»

• ### Oscillation and Transition Tests for Synchronous Sequential Circuits

Publication Year: 2013, Page(s):2338 - 2343
| |PDF (370 KB) | HTML

In this brief, we propose an oscillation-ring test methodology for synchronous sequential circuits under the scan test environment. This approach provides the following features: 1) it is at-speed testing, which makes delay defects detectable; 2) the automatic test pattern generation is much easier, and the test set is usually smaller; and 3) test responses are directly observable at primary outpu... View full abstract»

• ### High-Efficiency Customized Coarse-Grained Dynamically Reconfigurable Architecture for JPEG2000

Publication Year: 2013, Page(s):2343 - 2348
Cited by:  Papers (2)
| |PDF (419 KB) | HTML

This brief presents an efficient implementation of JPEG2000 encoding algorithm based on an architecture consisting of a coarse-grained dynamically reconfigurable instruction cell array and an embedded advanced RISC machine core. In this implementation, different tasks within the JPEG2000 encoding algorithm are allocated with proper computational resources to achieve high throughput. The proposed a... View full abstract»

• ### Cell-Based Process Resilient Multiphase Clock Generation

Publication Year: 2013, Page(s):2348 - 2352
Cited by:  Papers (1)
| |PDF (716 KB) | HTML

Multiphase clock generation (MPCG) is a problem that aims to generate a sequence of clock signals with the same frequency and uniformly shifted phases. In this brief, we present a cell-based MPCG design with two technical merits. We use a process calibration scheme that makes the per-phase delay (defined as the timing difference between two consecutive phases of clock signals) highly accurate. We ... View full abstract»

• ### Efficiency Optimization of a Step-Down Switched Capacitor Converter for Subthreshold

Publication Year: 2013, Page(s):2353 - 2357
Cited by:  Papers (5)
| |PDF (330 KB) | HTML

In this brief, an efficient voltage scalable switched capacitor converter (SCC) for 1.1 V battery-powered digital system is presented. The SCC employs a binary resolution technique to preserve high efficiency at load voltages down to sub-200 mV while keeping the efficiency high. The proposed converter can be configured into four topologies to support subthreshold output levels of 0.18-0.6 V. The c... View full abstract»

• ### IEEE Transactions on Very Large Scale Integration (VLSI) Systems information for authors

Publication Year: 2013, Page(s): 2358
| |PDF (98 KB)
• ### Do what you do better with What's New @ IEEE Xplore

Publication Year: 2013, Page(s): 2359
| |PDF (424 KB)

## Aims & Scope

Design and realization of microelectronic systems using VLSI/ULSI technologies requires close collaboration among scientists and engineers in the fields of systems architecture, logic and circuit design, chips and wafer fabrication, packaging, testing, and systems applications. Generation of specifications, design, and verification must be performed at all abstraction levels, including the system, register-transfer, logic, circuit, transistor, and process levels. To address this critical area through a common forum, the IEEE Transactions on VLSI Systems was founded.

Full Aims & Scope

## Meet Our Editors

Editor-in-Chief

Krishnendu Chakrabarty
Department of Electrical Engineering
Duke University
Durham, NC 27708 USA
Krish@duke.edu