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Very Large Scale Integration (VLSI) Systems, IEEE Transactions on

Issue 12 • Date Dec. 2013

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Displaying Results 1 - 25 of 28
  • Table of contents

    Page(s): C1 - C4
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  • IEEE Transactions on Very Large Scale Integration (VLSI) Systems publication information

    Page(s): C2
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  • Implementing Flexible Reliability in a Coarse-Grained Reconfigurable Architecture

    Page(s): 2165 - 2178
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (3608 KB) |  | HTML iconHTML  

    This paper proposes a coarse-grained dynamically reconfigurable architecture that offers flexible reliability to deal with soft errors and aging. The notion of a cluster is introduced as a basic architectural element; each cluster can select four operation modes with different levels of spatial redundancy and area efficiency. We evaluate the aging effect due to negative bias temperature instability and illustrate that periodically alternating active cells with resting ones will greatly mitigate the effects of the aging process with a negligible power overhead. The area of circuits that are added for immunity to soft errors and for mitigating aging effects is 29.3% of the proposed reconfigurable device. A fault-tolerance evaluation of a Viterbi decoder mapped on the architecture suggests that there is a considerable tradeoff between reliability and area overhead. Finally, we design and fabricate a test chip that contains a 4 × 8 cluster array in a 65-nm process and demonstrate its immunity to soft errors. Accelerated tests using an alpha particle foil showed that the mean time to failure and failure in time are well characterized with the number of sensitive bits and that our architecture can trade off soft error immunity with the area of implementation. View full abstract»

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  • SPREAD: A Streaming-Based Partially Reconfigurable Architecture and Programming Model

    Page(s): 2179 - 2192
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    Partially reconfigurable systems are promising computing platforms for streaming applications, which demand both hardware efficiency and reconfigurable flexibility. To realize the full potential of these systems, a streaming-based partially reconfigurable architecture and unified software/hardware multithreaded programming model (SPREAD) is presented in this paper. SPREAD is a reconfigurable architecture with a unified software/hardware thread interface and high throughput point-to-point streaming structure. It supports dynamic computing resource allocation, runtime software/hardware switching, and streaming-based multithreaded management at the operating system level. SPREAD is designed to provide programmers of streaming applications with a unified view of threads, allowing them to exploit thread, data, and pipeline parallelism; it enhances hardware efficiency while simplifying the development of streaming applications for partially reconfigurable systems. Experimental results targeting cryptography applications demonstrate the feasibility and superior performance of SPREAD. Moreover, the parallelized Advanced Encryption Standard (AES), Data Encryption Standard (DES), and Triple DES (3DES) hardware threads on field-programmable gate arrays show 1.61-4.59 times higher power efficiency than their implementations on state-of-the-art graphics processing units. View full abstract»

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  • Multiplierless Algorithm for Multivariate Gaussian Random Number Generation in FPGAs

    Page(s): 2193 - 2205
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    The multivariate Gaussian distribution is used to model random processes with distinct pair-wise correlations, such as stock prices that tend to rise and fall together. Multivariate Gaussian vectors with length n are usually produced by first generating a vector of n independent Gaussian samples, then multiplying with a correlation inducing matrix requiring O(n2) multiplications. This paper presents a method of generating vectors directly from the uniform distribution, removing the need for an expensive scalar Gaussian generator, and eliminating the need for any multipliers. The method relies only on small read-only memories and adders, and so can be implemented using only logic resources (lookup-tables and registers), saving multipliers, and block-memory resources for the numerical simulation that the multivariate generator is driving. The new method provides a ten times increase in performance (vectors/second) over the fastest existing field-programmable gate array generation method, and also provides a five times improvement in performance per resource over the most efficient existing method. Using this method, a single 400-MHz Virtex-5 FPGA can generate vectors ten times faster than an optimized implementation on a 1.2-GHz graphics processing unit, and a hundred times faster than vectorized software on a general purpose quad core 2.2-GHz processor. View full abstract»

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  • Time-Interleaved and Circuit-Shared Dual-Channel 10 b 200 MS/s 0.18 \mu{\rm m} CMOS Analog-to-Digital Convertor

    Page(s): 2206 - 2213
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    This paper proposes a 10 b 200 MS/s pipeline analog-to-digital convertor (ADC) for high-quality video systems based on double-channel and op-amp sharing schemes to minimize power consumption and channel mismatch. The double channel time-interleaved scheme reduces the required operating speed of amplifiers in the sample-and-hold amplifier and multiplying digital-to-analog (D/A) converters by 50%. The switched and shared op-amp with two input pairs amplifies each channel signal without extra series switches while minimizing the gain, bandwidth and offset mismatches between channels. The low-jitter sampling clock with a 50% duty cycle improves the dynamic performance of the wideband input signals significantly. The Flash ADCs employ a differential difference amplifier type pre-amp to continuously process dual-channel outputs. The prototype ADC in a 0.18 μm CMOS technology demonstrates the measured differential nonlinearity and integral nonlinearity within 0.62 and 0.99 LSB, respectively. At 200 MS/s, the ADC shows a maximum SNDR of 52.8 dB and a maximum SFDR of 60.4 dB. The ADC with an active die area of 1.28 mm2 consumes 54.0 mW at 1.8 V. View full abstract»

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  • Variation-Aware Aging Analysis in Digital ICs

    Page(s): 2214 - 2225
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    As CMOS devices become smaller, the process variations (PVs) and aging variations (AVs) become major issues for circuit reliability and yield. In this paper, we analyze the effects of PVs on aging effects such as hot carrier injection (HCI) and negative bias temperature instability (NBTI). Using Monte Carlo-based transistor-level simulations including principal component analysis, the correlations between PVs and AVs are considered, by which the accuracy of analysis is improved (1.2% for standard deviation and 1.7% for Vth99%) compared to other methods that ignore the correlations, especially in the smaller technology. In addition, we perform regression analysis with various models to improve the efficiency of variation-aware aging analysis. All models show an error rate about 1% for NBTI, and quadratic and custom models show an error rate of about 10% on average for HCI. View full abstract»

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  • Timing Uncertainty in 3-D Clock Trees Due to Process Variations and Power Supply Noise

    Page(s): 2226 - 2239
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    Clock distribution networks are affected by different sources of variations. The resulting clock uncertainty significantly affects the frequency of a circuit. To support this analysis, a statistical model of skitter, which consists of clock skew and jitter, for 3-D clock trees is introduced. The effect of skitter on both the setup and hold time slacks is modeled. The variation of skitter is shown to be underestimated up to 36% if process variations and dynamic power supply noise are considered separately, which highlights the importance of this unified treatment. Potential scenarios of supply noise in 3-D integrated circuits (ICs) are investigated. 3-D circuits generated from industrial benchmarks are simulated to show the skitter under these scenarios. The mean and standard deviation of skitter can vary up to 60% and 51%, respectively, due to the different amplitudes and phases of supply noise. The tradeoff between skitter and the power consumed by clock trees is also shown. A set of guidelines are presented to decrease skitter in 3-D ICs. By applying these guidelines to industrial benchmarks, simulations show a decrease in the mean skitter up to 31%. View full abstract»

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  • Process-Resilient Low-Jitter All-Digital PLL via Smooth Code-Jumping

    Page(s): 2240 - 2249
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    For an all-digital phase-locked loop, the frequency range supported is often segmented, and this could cause significant jitter when the operating condition (such as the supply voltage and/or the temperature) changes. To address this issue, we present a scheme, called smooth code-jumping, that can stitch together the segmented frequency profile of a digitally controlled oscillator (DCO) into a continuous range, and thereby reduce the jitter significantly. This scheme incorporates a new mirror-DCO-based calibration scheme to take into account process variations. We validate this scheme by test chips in 0.18-μm CMOS technology. Measurement results show that, when operating at 1 GHz, the rms jitter is 4.3 ps (0.43%UI) and the peak-to-peak jitter is 35.6 ps (3.56%UI), respectively. View full abstract»

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  • Near-Field Communication Transceiver System Modeling and Analysis Using SystemC/SystemC-AMS With the Consideration of Noise Issues

    Page(s): 2250 - 2261
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    SystemC, as a C++-based hardware description language, is used for system architecture design, large digital hardware, software, and their interaction. Its extension, SystemC-AMS, provides the capability of abstract modeling to deliver analog system-level simulation of “real-time” application scenarios. SystemC and SystemC-AMS help designers to analyze a whole mixed-signal system and further guide the circuit design to reduce the design cost. This paper presents SystemC (2.2.0) and SystemC-AMS (1.0 Beta2) modeling of a near-field communication (NFC) system working in passive mode, based on the proximity contactless identification cards ISO/IEC 14443 international standard. The NFC transceiver system includes reader and card analog blocks, digital blocks, and antennas. Problems caused by realistic imperfections are considered, simulated, and then solved by modifying the design at a system level, which is significant to high-level modeling. Systematic simulation is given to prove SystemC/SystemC-AMS is an accurate and efficient tool to model a heterogeneous mixed-signal system in an early-design stage. View full abstract»

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  • VLSI Implementation of a Soft-Output Signal Detector for Multimode Adaptive Multiple-Input Multiple-Output Systems

    Page(s): 2262 - 2273
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1210 KB) |  | HTML iconHTML  

    This paper presents a multimode soft-output multiple-input multiple-output (MIMO) signal detector that is efficient in hardware cost and energy consumption. The detector is capable of dealing with spatial-multiplexing (SM), space-division-multiple-access (SDMA), and spatial-diversity (SD) signals of 4 × 4 antenna and 64-QAM modulation. Implementation-friendly algorithms, which reuse most of the mathematical operations in these three MIMO modes, are proposed to provide accurate soft detection information, i.e., log-likelihood ratio, with much reduced complexity. A unified reconfigurable VLSI architecture has been developed to eliminate the implementation of multiple detector modules. In addition, several block level technologies, such as parallel metric update and fast bit-flipping, are adopted to enable a more efficient design. To evaluate the proposed techniques, we implemented the triple-mode MIMO detector in a 65-nm CMOS technology. The core area is 0.25 mm2 with 83.7 K gates. The maximum detecting throughput is 1 Gb/s at 167-MHz clock frequency and 1.2-V supply, which archives the data rate envisioned by the emerging long-term evolution advanced standard. Under frequency-selective channels, the detector consumes 59.3-, 10.5-, and 169.6-pJ energy per bit detection in SM, SD, and SDMA modes, respectively. View full abstract»

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  • A 5-Gb/s Automatic Sub-Bit Between-Pair Skew Compensator for Parallel Data Communications in 0.13- \mu{\rm m} CMOS

    Page(s): 2274 - 2285
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    This paper presents a between-pair skew (BPS) compensator for parallel data communications. It can detect time skew between two independent data sequences using continuous-time correlations and then automatically align the two using a wide-bandwidth voltage controlled data delay line. A 5-Gb/s sub-bit BPS compensator in 0.13- μm CMOS occupies approximately 0.038- mm2 active die area and dissipates 22.5 mW. View full abstract»

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  • Faults Affecting Energy-Harvesting Circuits of Self-Powered Wireless Sensors and Their Possible Concurrent Detection

    Page(s): 2286 - 2294
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    We analyze the effects of faults on an energy-harvesting circuit (EHC) providing power to a wireless biomedical multisensor node. We show that such faults may prevent the EHC from producing the power supply voltage level required by the multisensor node. Then, we propose a low-cost (in terms of power consumption and area overhead) additional circuit monitoring the voltage level produced by the EHC continuously, and concurrently with the normal operation of the device. Such a monitor gives an error indication if the generated voltage falls below the minimum value required by the sensor node to operate correctly, thus allowing the activation of proper recovery actions to guarantee system fault tolerance. The proposed monitor is self-checking with regard to the internal faults that can occur during its in-field operation, thus providing an error signal when affected by faults itself. View full abstract»

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  • Hardware Designer's Guide to Fault Attacks

    Page(s): 2295 - 2306
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    Hardware designers invest a significant design effort when implementing computationally intensive cryptographic algorithms onto constrained embedded devices to match the computational demands of the algorithms with the stringent area, power, and energy budgets of the platforms. When it comes to designs that are employed in potential hostile environments, another challenge arises-the design has to be resistant against attacks based on the physical properties of the implementation, the so-called implementation attacks. This creates an extra design concern for a hardware designer. This paper gives an insight into the field of fault attacks and countermeasures to help the designer to protect the design against this type of implementation attacks. We analyze fault attacks from different aspects and expose the mechanisms they employ to reveal a secret parameter of a device. In addition, we classify the existing countermeasures and discuss their effectiveness and efficiency. The result of this paper is a guide for selecting a set of countermeasures, which provides a sufficient security level to meet the constraints of the embedded devices. View full abstract»

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  • Timing Measurement Platform for Arbitrary Black-Box Circuits Based on Transition Probability

    Page(s): 2307 - 2320
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    The key aspects of a good on-chip timing measurement platform are high measurement resolution, accuracy, and low area overhead. A measurement method based on transition probability (TP) has shown promising characteristics in all these areas. In this paper, the TP measurement method is examined through simulation to understand its apparent effectiveness and accuracy in measuring complex circuits. Timing uncertainties and logic glitch activities are considered in detail, and the effect of varying input vectors' probability distributions is analyzed to enable further accuracy improvements. Using a field-programmable gate array, the method is implemented and demonstrated as a modular on-chip test platform for testing complex arbitrary circuits. Practical circuits found in typical modular designs, including fixed/floating-point arithmetic and filter circuits, are chosen to evaluate the test platform. The resolution of the timing measurements ranges from 0.3 to 8.0 ps, and the measurement errors against reference measurements are found to be within 3.6%. The test platform can be applied to VLSI designs with minor area overhead, and provides designers with precise and accurate physical timing information of circuits. View full abstract»

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  • Functional Broadside Templates for Low-Power Test Generation

    Page(s): 2321 - 2325
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    This brief describes a new approach to low-power test generation targeting the maximum switching activity during the fast functional clock cycles of broadside tests. This brief defines functional broadside templates as incompletely-specified broadside tests, which capture the signal-transitions that occur during the fast functional clock cycles of functional broadside tests. The same signal-transitions can occur during functional operation. Therefore, functional broadside templates can guide the generation of low-power test sets when the goal is to match the power dissipation that is possible during functional operation on a line-by-line basis. This brief describes a procedure for computing functional broadside templates from completely-specified functional broadside tests, and a low-power test generation procedure for transition faults based on templates. View full abstract»

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  • Parallelization of Radix-2 Montgomery Multiplication on Multicore Platform

    Page(s): 2325 - 2330
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    Montgomery multiplication is the kernel operation in public key ciphers. Aiming at parallel implementation of Montgomery multiplication, this brief presents an improved task partitioning of the Montgomery multiplication algorithm for the multicore platform with area-efficient processors. Several multicore platforms are designed to verify the efficiency of parallelization. The fastest platform takes 3460 cycles to finish a 1024-b Montgomery multiplication, which is six times faster than a single MIPS processor and three times faster than the pSHS parallelization based on a platform with eight MicroBlaze cores. View full abstract»

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  • Novel Architecture for Efficient FPGA Implementation of Elliptic Curve Cryptographic Processor Over {\rm GF}(2^{163})

    Page(s): 2330 - 2333
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (292 KB) |  | HTML iconHTML  

    A new and highly efficient architecture for elliptic curve scalar point multiplication is presented. To achieve the maximum architectural and timing improvements, we reorganize and reorder the critical path of the Lopez-Dahab scalar point multiplication architecture such that logic structures are implemented in parallel and operations in the critical path are diverted to noncritical paths. The results we obtained show that with G=55 our proposed design is able to compute scalar multiplication over GF(2163) in 9.6 μs with the maximum achievable frequency of 250 MHz on Xilinx Virtex-4 (XC4VLX200), where G is the digit size of the underlying digit-serial finite-field multiplier. Another implementation variant for less resource consumption is also proposed; with G=33, the design performs the same operation in 11.6 μs at 263 MHz on the same platform. The results of synthesis show that, in the first implementation, 17 929 slices or 20% of the chip area is occupied, which makes it suitable for speed-critical cryptographic applications, while in the second implementation 14203 slices or 16% of the chip area is utilized, which makes it suitable for applications that may require speed-area tradeoff. View full abstract»

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  • Concurrent Error Detection for Orthogonal Latin Squares Encoders and Syndrome Computation

    Page(s): 2334 - 2338
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (314 KB) |  | HTML iconHTML  

    Error correction codes (ECCs) are commonly used to protect memories against errors. Among ECCs, orthogonal latin squares (OLS) codes have gained renewed interest for memory protection due to their modularity and the simplicity of the decoding algorithm that enables low delay implementations. An important issue is that when ECCs are used, the encoder and decoder circuits can also suffer errors. In this brief, a concurrent error detection technique for OLS codes encoders and syndrome computation is proposed and evaluated. The proposed method uses the properties of OLS codes to efficiently implement a parity prediction scheme that detects all errors that affect a single circuit node. View full abstract»

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  • Oscillation and Transition Tests for Synchronous Sequential Circuits

    Page(s): 2338 - 2343
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    In this brief, we propose an oscillation-ring test methodology for synchronous sequential circuits under the scan test environment. This approach provides the following features: 1) it is at-speed testing, which makes delay defects detectable; 2) the automatic test pattern generation is much easier, and the test set is usually smaller; and 3) test responses are directly observable at primary outputs and, thus, it greatly reduces the communication bandwidth between the automatic test equipment and the circuit under test. A modified scan register design supporting the oscillation-ring test is presented and an effective oscillation test generation algorithm for the proposed test scheme is given. Experimental results on LGSyn91 benchmarks show that the proposed test method achieves high fault coverage with a smaller number of test vectors. View full abstract»

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  • High-Efficiency Customized Coarse-Grained Dynamically Reconfigurable Architecture for JPEG2000

    Page(s): 2343 - 2348
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (419 KB) |  | HTML iconHTML  

    This brief presents an efficient implementation of JPEG2000 encoding algorithm based on an architecture consisting of a coarse-grained dynamically reconfigurable instruction cell array and an embedded advanced RISC machine core. In this implementation, different tasks within the JPEG2000 encoding algorithm are allocated with proper computational resources to achieve high throughput. The proposed architecture is dynamically reconfigured for different tasks during the encoding process. Simulation results demonstrate that the proposed architecture provides a throughput of up to 52.1 f/s (or 19.18 ms/frame) to encode a 256 × 256 standard Lena test image. Compared with various digital signal processor & very long instruction word-based JPEG2000 solutions, the proposed architecture provides significant advantages in terms of throughput and energy consumption. View full abstract»

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  • Cell-Based Process Resilient Multiphase Clock Generation

    Page(s): 2348 - 2352
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    Multiphase clock generation (MPCG) is a problem that aims to generate a sequence of clock signals with the same frequency and uniformly shifted phases. In this brief, we present a cell-based MPCG design with two technical merits. We use a process calibration scheme that makes the per-phase delay (defined as the timing difference between two consecutive phases of clock signals) highly accurate. We further exploit a so-called cyclic property to make the achievable per-phase delay much smaller than a buffer delay. A design with 16-phase clock signal (with the per-phase delay of only 100 ps) is used to demonstrate its effectiveness. View full abstract»

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  • Efficiency Optimization of a Step-Down Switched Capacitor Converter for Subthreshold

    Page(s): 2353 - 2357
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    In this brief, an efficient voltage scalable switched capacitor converter (SCC) for 1.1 V battery-powered digital system is presented. The SCC employs a binary resolution technique to preserve high efficiency at load voltages down to sub-200 mV while keeping the efficiency high. The proposed converter can be configured into four topologies to support subthreshold output levels of 0.18-0.6 V. The converter is designed in a standard lowpower 40-nm CMOS TSMC process. Simulation results show that the efficiency of the SCC can be improved by 10%-11% in the vicinity of VDD=200 mV as compared to one using a conventional approach. An optimization strategy for designing multi-topology SCC is presented to improve the effectiveness of the circuit and to preserve efficiency over large load voltages. View full abstract»

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    Page(s): 2358
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Aims & Scope

Design and realization of microelectronic systems using VLSI/ULSI technologies require close collaboration among scientists and engineers in the fields of systems architecture, logic and circuit design, chips and wafer fabrication, packaging, testing, and systems applications. Generation of specifications, design, and verification must be performed at all abstraction levels, including the system, register-transfer, logic, circuit, transistor, and process levels.

To address this critical area through a common forum, the IEEE Transactions on VLSI Systems was founded. The editorial board, consisting of international experts, invites original papers which emphasize the novel system integration aspects of microelectronic systems, including interactions among system design and partitioning, logic and memory design, digital and analog circuit design, layout synthesis, CAD tools, chips and wafer fabrication, testing and packaging, and system level qualification. Thus, the coverage of this Transactions focuses on VLSI/ULSI microelectronic system integration.

Topics of special interest include, but are not strictly limited to, the following: • System Specification, Design and Partitioning, • System-level Test, • Reliable VLSI/ULSI Systems, • High Performance Computing and Communication Systems, • Wafer Scale Integration and Multichip Modules (MCMs), • High-Speed Interconnects in Microelectronic Systems, • VLSI/ULSI Neural Networks and Their Applications, • Adaptive Computing Systems with FPGA components, • Mixed Analog/Digital Systems, • Cost, Performance Tradeoffs of VLSI/ULSI Systems, • Adaptive Computing Using Reconfigurable Components (FPGAs) 

Full Aims & Scope

Meet Our Editors

Editor-in-Chief
Yehea Ismail
CND Director
American University of Cairo and Zewail City of Science and Technology
New Cairo, Egypt
y.ismail@aucegypt.edu