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Very Large Scale Integration (VLSI) Systems, IEEE Transactions on

Issue 11 • Date Nov. 2013

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Displaying Results 1 - 21 of 21
  • Table of contents

    Publication Year: 2013 , Page(s): C1 - C4
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  • IEEE Transactions on Very Large Scale Integration (VLSI) Systems publication information

    Publication Year: 2013 , Page(s): C2
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  • Security-Enabled Near-Field Communication Tag With Flexible Architecture Supporting Asymmetric Cryptography

    Publication Year: 2013 , Page(s): 1965 - 1974
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (824 KB) |  | HTML iconHTML  

    This paper presents the design and implementation of a complete near-field communication (NFC) tag system that supports high-security features. The tag design contains all hardware modules required for a practical realization, which are: an analog 13.56-MHz radio-frequency identification (RFID) front-end, a digital part that includes a tiny (programmable) 8-b microcontroller, a framing logic for data transmission, a memory unit, and a crypto unit. All components have been highly optimized to meet the fierce requirements of passively powered RFID devices while providing a high level of flexibility and security. The tag is fully compliant with the NFC Forum Type-4 specification and supports the ISO/IEC 14443A (layer 1-4) communication protocol as well as block transmission according to ISO/IEC 7816. Its security features include support of encryption and decryption using the Advanced Encryption Standard (AES-128), the generation of digital signatures using the elliptic curve digital signature algorithm according to NIST P-192, and several countermeasures against common implementation attacks, such as side-channel attacks and fault analyses. The chip has been fabricated in a 0.35- μm CMOS process technology, and requires 49999 GEs of chip area in total (including digital parts and analog front-end). Finally, we present a practical realization of our design that can be powered passively by a conventional NFC-enabled mobile phone for realizing proof-of-origin applications to prevent counterfeiting of goods, or to provide location-aware services using RFID technology. View full abstract»

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  • Design of Logic Gates and Flip-Flops in High-Performance FinFET Technology

    Publication Year: 2013 , Page(s): 1975 - 1988
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1506 KB) |  | HTML iconHTML  

    With the emergence of nonplanar CMOS devices at the 22-nm node and beyond, it is highly likely that multigate device adoption will occur in a high-performance process technology, owing to the increased performance and area benefits. In this paper, for the first time, we evaluate symmetric (Symm-ΦG) and asymmetric (Asymm-ΦG) gate-workfunction FinFETs head to head in a high-performance process, using technology computer-aided design 3-D device simulations. We demonstrate that Asymm-ΦG shorted-gate (a-SG) n/p-FinFETs, which use both workfunctions corresponding to typical high-performance metal-gate n/p-FinFETs, are promising, as they can yield over two orders of magnitude lower leakage without excessive degradation in ON-state current, in comparison to Symm- ΦG shorted-gate (SG) FinFETs, placing them in a better position than back-gate biased independent-gate (IG) FinFETs for leakage reduction. Thereafter, we explore the design space of FinFET logic gates, latches, and flip-flops, for optimal tradeoffs in leakage versus delay and temperature, using mixed-mode 2-D device simulations. Elementary logic gates (such as INV, NAND2, NOR2, XOR2, and XNOR2) using Asymm-ΦG SG-mode FinFETs appear to be located optimally in the leakage-delay spectrum, in comparison to the most versatile configurations possible by mixing corresponding Symm-ΦG SG- and IG-mode FinFETs. Latches and flip-flops, however, require an astute combination of Symm-ΦG and Asymm-ΦG FinFETs to optimize leakage, delay, and setup time simultaneously. View full abstract»

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  • Scalable Digital CMOS Comparator Using a Parallel Prefix Tree

    Publication Year: 2013 , Page(s): 1989 - 1998
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    We present a new comparator design featuring wide-range and high-speed operation using only conventional digital CMOS cells. Our comparator exploits a novel scalable parallel prefix structure that leverages the comparison outcome of the most significant bit, proceeding bitwise toward the least significant bit only when the compared bits are equal. This method reduces dynamic power dissipation by eliminating unnecessary transitions in a parallel prefix structure that generates the N-bit comparison result after (log4 N)+(log16N)+4 CMOS gate delays. Our comparator is composed of locally interconnected CMOS gates with a maximum fan-in and fan-out of five and four, respectively, independent of the comparator bitwidth. The main advantages of our design are high speed and power efficiency, maintained over a wide range. Additionally, our design uses a regular reconfigurable VLSI topology, which allows analytical derivation of the input-output delay as a function of bitwidth. HSPICE simulation for a 64-b comparator shows a worst case input-output delay of 0.86 ns and a maximum power dissipation of 7.7 mW using 0.15- μm TSMC technology at 1 GHz. View full abstract»

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  • Energy-Efficient High-Throughput Montgomery Modular Multipliers for RSA Cryptosystems

    Publication Year: 2013 , Page(s): 1999 - 2009
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1081 KB) |  | HTML iconHTML  

    Modular exponentiation in the Rivest, Shamir, and Adleman cryptosystem is usually achieved by repeated modular multiplications on large integers. To speed up the encryption/decryption process, many high-speed Montgomery modular multiplication algorithms and hardware architectures employ carry-save addition to avoid the carry propagation at each addition operation of the add-shift loop. In this paper, we propose an energy-efficient algorithm and its corresponding architecture to not only reduce the energy consumption but also further enhance the throughput of Montgomery modular multipliers. The proposed architecture is capable of bypassing the superfluous carry-save addition and register write operations, leading to less energy consumption and higher throughput. In addition, we also modify the barrel register full adder (BRFA) so that the gated clock design technique can be applied to significantly reduce the energy consumption of storage elements in BRFA. Experimental results show that the proposed approaches can achieve up to 60% energy saving and 24.6% throughput improvement for 1024-bit Montgomery multiplier. View full abstract»

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  • Relaxed Min-Max Decoder Architectures for Nonbinary Low-Density Parity-Check Codes

    Publication Year: 2013 , Page(s): 2010 - 2023
    Cited by:  Papers (8)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1066 KB) |  | HTML iconHTML  

    Compared to binary low-density parity-check (LDPC) codes, nonbinary (NB) LDPC codes can achieve higher coding gain when the codeword length is moderate, but at the cost of higher decoding complexity. One major bottleneck of NB-LDPC decoding is the complicated check node processing. In this paper, a novel relaxed check node processing scheme is proposed for the min-max NB-LDPC decoding algorithm. Each finite field element of GF(2p) can be uniquely represented by a linear combination of p independent field elements. Making use of this property, an innovative method is developed in this paper to first find a set of the p most reliable variable-to-check messages with independent field elements, called the minimum basis. Then, the check-to-variable messages are efficiently computed from the minimum basis. With very small performance loss, the complexity of the check node processing can be substantially reduced using the proposed scheme. In addition, efficient VLSI architectures are developed to implement the proposed check node processing and the overall NB-LDPC decoder. Compared to the most efficient prior design, the proposed decoder for a (837, 726) NB-LDPC code over GF(25) can achieve 52% higher efficiency in terms of throughput-over-area ratio. View full abstract»

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  • Configurable Input–Output Power Pad for Wafer-Scale Microelectronic Systems

    Publication Year: 2013 , Page(s): 2024 - 2033
    Cited by:  Papers (1)
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    We describe, in this paper, a new digital input-output power configurable PAD (CPAD) for a wafer-scale-based rapid prototyping platform for electronic systems. This wafer-scale platform includes a reconfigurable wafer-scale circuit that can interconnect any digital components manually deposited on its active alignment-insensitive surface. The whole platform is powered using a massive grid of embedded voltage regulators. Power is fed from the bottom side of the wafer using through silicon vias. The CPAD can be configured to provide CMOS standard voltages of 1.0, 1.5, 1.8, 2.0, 2.5, and 3.3 V using a single 3.3 V power supply. The digital I/O includes transistors sharing and is embedded within the regulation circuit by combining it with a turbo mode that insures high-speed operation. Fast load regulation is achieved with a 5.5-ns response time to a current step load for a maximum current of 110 mA per CPAD. The proposed circuit architecture benefits from a hierarchical arborescence topology where one master stage drives 16 CPADs with a very small quiescent current of 366 nA. The CPAD circuit and the master stage occupy a small area of 0.00847 and 0.00726 mm2, respectively, in CMOS 0.18-μm technology. View full abstract»

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  • An 8-to-1 bit 1-MS/s SAR ADC With VGA and Integrated Data Compression for Neural Recording

    Publication Year: 2013 , Page(s): 2034 - 2044
    Cited by:  Papers (5)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1270 KB) |  | HTML iconHTML  

    Low power consumption per channel and data rate minimization are two key challenges which need to be addressed in future generations of neural recording systems (NRS). Power consumption can be reduced by avoiding unnecessary processing whereas data rate is greatly decreased by sending spike time-stamps along with spike features as opposed to raw digitized data. Dynamic range in NRS can vary with time due to change in electrode-neuron distance or background noise, which demands adaptability. An analog-to-digital converter (ADC) is one of the most important blocks in a NRS. This paper presents an 8-bit SAR ADC in 0.13- μm CMOS technology along with input and reference buffer. A novel energy efficient digital-to-analog converter switching scheme is proposed, which consumes 37% less energy than the present state-of-the-art. The use of a ping-pong input sampling scheme is emphasized for multichannel input to alleviate the bandwidth requirement of the input buffer. To reduce the data rate, the A/D process is only enabled through the in-built background noise rejection logic to ensure that the noise is not processed. The ADC resolution can be adjusted from 8 to 1 bit in 1-bit step based on the input dynamic range. The ADC consumes 8.8 μW from 1 V supply at 1 MS/s speed. It achieves effective number of bits of 7.7 bits and FoM of 42.3 fJ/conversion-step. View full abstract»

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  • Dynamic Thermal Management Under Soft Thermal Constraints

    Publication Year: 2013 , Page(s): 2045 - 2054
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (618 KB) |  | HTML iconHTML  

    In this paper, we investigate dynamic thermal management (DTM) policies under soft thermal constraint that allow the thermal constraint to be violated occasionally for boosting system performance. First, we investigate soft-constraint DTM using lumped radio control (RC) thermal models. We develop analytical expressions for the optimal core frequency policies that maximize overall performance under soft thermal constraint for both single-core and homogeneous multicore processors. We then generalize the problem to heterogeneous multicore processor and use a more accurate distributed RC thermal model to account for the spatial thermal variation. The generalized problem also takes into account the impact of increased temperature on transistor delay and leakage power. The problem is solved by convex optimization. Experimental results indicate that for a two-core processor, a mere 10 °C increase in the core temperature for 100 s results in about 30% performance gain. View full abstract»

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  • Optimized Quantum Gate Library for Various Physical Machine Descriptions

    Publication Year: 2013 , Page(s): 2055 - 2068
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1018 KB) |  | HTML iconHTML  

    Quantum logic circuits consist of a cascade of quantum gates. These gates are realized using primitive quantum operations that are supported by a quantum physical machine description (PMD). Since different quantum systems are associated with different Hamiltonians, a specific quantum operation may be more easily realizable in one quantum system than another. Thus, different quantum systems have different PMDs. Also, the quantum cost for implementing a quantum operation may differ from one PMD to another. Thus, a quantum logic circuit needs to be realized with and optimized for only the set of primitive quantum operations supported by the given PMD. Quantum logic design that can be targeted at multiple PMDs has not been attempted before, to the best of our knowledge. In this paper, we target quantum logic design with respect to the set of primitive quantum operations that are supported by six different PMDs: quantum dot, superconducting, ion trap, neutral atom, and two photonics systems. Our aim is to build a quantum gate library that targets these PMDs. This is akin to a cell library in traditional logic design that enables logic gates to be mapped to cells realizable in an underlying technology. To make our quantum gate library efficient in terms of the number of primitive quantum operations involved and the associated delay, we explore one- and two-qubit quantum identity rules that can help remove redundancies in the quantum gate implementation. We show that, using these identities, each gate in the library can be efficiently mapped to just the set of primitive operations supported by each of the six PMDs. Each mapping results in a different circuit structure and quantum cost, which is measured in terms of the number of primitive quantum operations and the number of execution cycles required. Thus, such a library provides the foundation for quantum logic synthesis, just like a cell library provides the foundation for technology-dependent logic synthesis (i.e., te- hnology mapping) in traditional synthesis. View full abstract»

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  • Robust Hybrid Memristor-CMOS Memory: Modeling and Design

    Publication Year: 2013 , Page(s): 2069 - 2079
    Cited by:  Papers (5)
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    In this paper, we explore various aspects of memristor modeling and use them to propose improved access operations and design of a memristor-based memory. We study the current mathematical and SPICE modeling of memristors and compare them with known device specifications. Based on this survey of existing models, we adopt an improved mathematical model of the memristor that captures the well-established features of memristive devices. This modeling is used to analyze the time and voltage characteristics of stable read and write operations. The tradeoffs between the various design parameters such as voltage, frequency, noise margin, and area are also analyzed. Based on the device modeling, we propose a hybrid CMOS-memristor memory cell and architecture that addresses the limitations of memristor such as state drift, cell-cell interference, and refresh requirements. Memristor is used as a state element, and CMOS-based transistors are used to isolate, control, decode, and inter operate the logic. We verify our design using SPICE simulation using a 28-nm model for CMOS and a modified memristor model. View full abstract»

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  • 10–315-MHz Cascaded Hybrid Phase-Locked Loop for Pixel Clock Generation

    Publication Year: 2013 , Page(s): 2080 - 2093
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    A cascaded hybrid phase-locked loop (PLL) fabricated in a 65-nm CMOS process consumes 21 mW and occupies 0.4 mm2. An all-digital PLL (ADPLL) with piecewise linear calibrated hierarchical time-to-digital converter is proposed to achieve a wide operation range, and a charge-pump PLL (CPPLL) with an auxiliary (AUX) charge-pump for low current mismatch is cascaded to filter out the ADPLL output noise. The ADPLL achieves low long-term jitter regardless of the leakage current, and the CPPLL realizes low short-term jitter using a self-biased technique and the AUX charge pump. A phase-selectable divider is also proposed to divide the clock frequency while keeping the relative phase difference constant. The measured peak-to-peak short-term and long-term jitters at an output frequency of 315 MHz are 40 and 70 pspp, respectively, with a multiplication factor of 1024. View full abstract»

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  • 3-D-TCAD-Based Parasitic Capacitance Extraction for Emerging Multigate Devices and Circuits

    Publication Year: 2013 , Page(s): 2094 - 2105
    Cited by:  Papers (1)
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    In recent years, the multigate field-effect transistor (FET) has emerged as the most viable contender for technology scaling down to the sub-10-nm nodes. The nonplanar nature of multigate devices, along with rapidly shrinking front-end-of-line (FEOL) and back-end-of-line (BEOL) features, has compounded the problem of parasitics extraction in future technology nodes. In this paper, for the first time, we address the above problem through a holistic 3-D-technology CAD (3-D-TCAD) flow for the extraction of FEOL/(FEOL+BEOL) capacitances in generic multigate circuit layouts, using a transport analysis-based approach. We investigate device-level parasitic capacitances in 3-D-process-simulated bulk and silicon-on-insulator FinFETs, and uncover capacitance scaling trends for candidate single/multifin multigate FETs along the 22-nm/14-nm/10-nm technology nodes. Leveraging automated structure synthesis algorithms, we synthesize 3-D multigate 6T SRAM structures using the process-simulated devices, and examine the effects of fin pitch, gate pitch, and fin count on circuit-level parasitics. Thereafter, we show that traditional segregated FEOL/BEOL modeling approaches fail to provide accurate estimates, by back-annotating 3-D-TCAD-extracted capacitances into mixed-mode write simulations of a 6T FinFET SRAM bitcell. Finally, using FinFET NAND2 logic gate delay simulations, we establish the fact that capturing parasitics accurately is as important as modeling device transport accurately, and that performance/dynamic behavior in multigate circuits is highly sensitive to both factors. View full abstract»

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  • Architectural Analysis for Wirelessly Powered Computing Platforms

    Publication Year: 2013 , Page(s): 2106 - 2117
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    We present a design framework for wirelessly powered generic computing platforms that takes into account various system parameters in response to a time-varying energy source. These parameters are the charging profile of the energy source, computing speed (fclk), digital supply voltage (VDD), energy storage capacitance (Cs), and power conversion efficiency (η). We address both continuous and discrete operational modes of computation based on the energy source's charging profile. Unlike other reported works where investigations are limited to wireless energy transfer and functional demonstrations, our aim is to develop a theoretical model that comprises the complete system architecture by combining energy transfer and consumption in a step-by-step manner. We show that field resilience operation in a wireless energy field can be incorporated by modulating the power consumption in the digital platform in response to changing energy fields using this analysis. This paper also allows guidelines for choosing the appropriate computing policies based on the charging profile of energy source. This leads to an optimal, adaptive use of available energy in order to optimize the overall performance. View full abstract»

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  • Routing-Based Traffic Migration and Buffer Allocation Schemes for 3-D Network-on-Chip Systems With Thermal Limit

    Publication Year: 2013 , Page(s): 2118 - 2131
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1955 KB) |  | HTML iconHTML  

    The 3-D network-on-chip (NoC) router is a major source of thermal hotspots, limiting the performance gain of 3-D integration. Due to the varying cooling efficiency of different silicon layers in 3-D NoC, the optimal criteria of traditional load balancing design (LBD) scheme and temperature balancing design (TBD) scheme may not be satisfied. To analyze the tradeoff between performance and temperature, we provide a new analytical model. The model shows that the LBD scheme and the TBD scheme can be considered as two corner cases in the design space, and design cases can be categorized by comparing the bandwidth bound and the thermal-limited bound. To find the optimal design criteria between the LBD and the TBD schemes in 3-D NoC, we propose a new routing-based traffic migration, vertical-downward lateral-adaptive proactive routing (VDLAPR), and buffer allocation methods, vertical buffer allocation (VBA). The VDLAPR algorithm enables to tradeoff between the LBD and the TBD schemes. The proposed VBA method mitigates the traffic congestion caused by traffic migration. To reach the optimal configuration, we propose a systematic design flow, which assists in finding the best design parameters in the expanded space between LBD and TBD. Based on the traffic-thermal co-simulation experiments, the achievable throughput can be improved from 2.7% to 45.2% using the proposed design scheme. View full abstract»

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  • Design and Analysis of Dual-Mode Digital-Control Step-Up Switched-Capacitor Power Converter With Pulse-Skipping and Numerically Controlled Oscillator-Based Frequency Modulation

    Publication Year: 2013 , Page(s): 2132 - 2140
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1386 KB) |  | HTML iconHTML  

    This paper presents a 3 V-to-5 V integrated dual-mode digital-control step-up switched-capacitor (SC) power converter. The feedback control circuit is equipped with a low-power analog-to-digital converter which monitors and feeds the output voltage to a digital controller. With light loading, the control loop operates in a pulse-skipping mode. With heavy loading, the control loop operates in a frequency modulation mode (FMM) based on a numerically controlled oscillator whose switching frequency varies from 31.25 kHz to 1 MHz. The design is fabricated in a 0.5- μm digital CMOS process. With multiplierless implementation, the controller requires a gate count of less than 300. The whole design occupies a total active area of 0.23 mm2. From silicon measurement, with a 330-nF external flying capacitor, the design delivers a regulated 5 V output with an output current up to 25 mA from a 3 V supply, delivering an output power greater than 100 mW. The load regulation is measured to be 0.14%. A remarkable efficiency of 80% or above on average under various loading conditions is achieved. Dynamic characteristic and stability analysis of the SC converter in the FMM are presented. Comparisons with existing designs demonstrate the excellence of the proposed design. View full abstract»

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  • Extending the Energy Efficiency and Performance With Channel Buffers, Crossbars, and Topology Analysis for Network-on-Chips

    Publication Year: 2013 , Page(s): 2141 - 2154
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1760 KB) |  | HTML iconHTML  

    Network-on-chips (NoCs) have emerged as a scalable solution to the wire delay constraints, thereby providing a high-performance communication fabric for future multicores. Research has shown that power, area, and performance of the NoC architecture are tightly integrated with the design and optimization of the link, router (buffer and crossbar), and topology. Recent work has shown that adaptive channel buffers (on-link storage) can considerably reduce power consumption and area overhead by reducing or replacing the power-hungry router buffers. However, channel buffer design can lead to head-of-line (HoL) blocking, which eventually reduces the throughput of the network. In this paper, we design channel buffers and router crossbars to improve the performance (latency, throughput) while reducing the power consumption. In addition, we implement the proposed channel buffers and crossbar organizations in a concentrated torus (CTorus) topology which is a dual network without the additional area overhead. We compare other dual networks with leading topologies such as mesh2X, concentrated mesh2X (CMesh2X), and flattened butterfly2X (FBfly2X), each implemented with channel buffers. Our proposed designs analyze the power-performance-area tradeoff in designing channel buffers for NoC architectures while alleviating HoL blocking through buffer organizations and crossbar optimizations. Results using Synopsys design compiler showed that the buffer and crossbar organizations for an 8 × 8 mesh architecture can reduce power consumption by 25%-40%, improve throughput and reduce latency by 525%, while occupying 4%-13% more area when compared to the baseline architecture for both synthetic as well as real benchmark traces such as Princeton Application Repository for Shared-Memory Computers (PARSEC) and Standard Performance Evaluation Corporation (SPEC). CPU2006. When the energy-efficient buffer and crossbar organization was inserted into our CTorus topology, we further reduced - nergy dissipation by 32% and area by 53%, on average, over mesh2X, CMesh2X, and FBfly2X. View full abstract»

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  • Skew Compensation Technique for Source-Synchronous Parallel DRAM Interface

    Publication Year: 2013 , Page(s): 2155 - 2159
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    The interpin skew among the data and the strobe signals of a source-synchronous parallel DRAM interface is compensated by a simple delay-locked loop, which reuses the circuitry of a normal input data path. With the interpin skew compensation, the printed circuit board traces of the data and the strobe signals are allowed to have unequal length. The prototype implemented in a 0.13- μm standard CMOS process shows that the interpin skew is reduced to be less than 26 ps for a 3.2-Gb/s/pin ×8 parallel interface. View full abstract»

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  • Improved High Code-Rate Soft BCH Decoder Architectures With One Extra Error Compensation

    Publication Year: 2013 , Page(s): 2160 - 2164
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    Compared with traditonal hard Bose-Chaudhuri-Hochquenghem (BCH) decoders, soft BCH decoders provide better error-correcting performance but much higher hardware complexity. In this brief, an improved soft BCH decoding algorithm is presented to achieve both competitive hardware complexity and better error-correcting performance by dealing with least reliable bits and compensating one extra error outside the least reliable set. For BCH (255, 239; 2) and (255, 231; 3) codes, our proposed soft BCH decoders can achieve up to 0.75-dB coding gain with one extra error compensation and 5% less complexity than the traditional hard BCH decoders. View full abstract»

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  • IEEE Transactions on Very Large Scale Integration (VLSI) Systems society information

    Publication Year: 2013 , Page(s): C3
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    Freely Available from IEEE

Aims & Scope

Design and realization of microelectronic systems using VLSI/ULSI technologies require close collaboration among scientists and engineers in the fields of systems architecture, logic and circuit design, chips and wafer fabrication, packaging, testing, and systems applications. Generation of specifications, design, and verification must be performed at all abstraction levels, including the system, register-transfer, logic, circuit, transistor, and process levels.

To address this critical area through a common forum, the IEEE Transactions on VLSI Systems was founded. The editorial board, consisting of international experts, invites original papers which emphasize the novel system integration aspects of microelectronic systems, including interactions among system design and partitioning, logic and memory design, digital and analog circuit design, layout synthesis, CAD tools, chips and wafer fabrication, testing and packaging, and system level qualification. Thus, the coverage of this Transactions focuses on VLSI/ULSI microelectronic system integration.

Topics of special interest include, but are not strictly limited to, the following: • System Specification, Design and Partitioning, • System-level Test, • Reliable VLSI/ULSI Systems, • High Performance Computing and Communication Systems, • Wafer Scale Integration and Multichip Modules (MCMs), • High-Speed Interconnects in Microelectronic Systems, • VLSI/ULSI Neural Networks and Their Applications, • Adaptive Computing Systems with FPGA components, • Mixed Analog/Digital Systems, • Cost, Performance Tradeoffs of VLSI/ULSI Systems, • Adaptive Computing Using Reconfigurable Components (FPGAs) 

Full Aims & Scope

Meet Our Editors

Editor-in-Chief

Krishnendu Chakrabarty
Department of Electrical Engineering
Duke University
Durham, NC 27708 USA
Krish@duke.edu