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# IEEE Transactions on Very Large Scale Integration (VLSI) Systems

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Displaying Results 1 - 22 of 22

Publication Year: 2013, Page(s):C1 - C4
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• ### IEEE Transactions on Very Large Scale Integration (VLSI) Systems publication information

Publication Year: 2013, Page(s): C2
| PDF (136 KB)
• ### Enhancing the Efficiency of Energy-Constrained DVFS Designs

Publication Year: 2013, Page(s):1769 - 1782
Cited by:  Papers (20)
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The proliferation of embedded systems and mobile devices has created an increasing demand for low-energy hardware. Dynamic voltage and frequency scaling (DVFS) is a popular energy reduction technique that allows a hardware design to reduce average power consumption while still enabling the design to meet a high-performance target when necessary. To conserve energy, many DVFS-based embedded and mob... View full abstract»

• ### Timing Yield Slack for Timing Yield-Constrained Optimization and Its Application to Statistical Leakage Minimization

Publication Year: 2013, Page(s):1783 - 1796
Cited by:  Papers (4)
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This paper focuses on statistical optimization and, more specifically, timing yield (TY)-constrained optimization. For cell replacement in timing-constrained optimization, we need an indicator that examines whether or not a timing violation occurs and gives the available timing for a gate. In deterministic optimization, the timing slack is used for this indicator. Although there is an analogous co... View full abstract»

• ### Embedded Transition Inversion Coding With Low Switching Activity for Serial Links

Publication Year: 2013, Page(s):1797 - 1810
Cited by:  Papers (5)
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Serial link interconnection has been proposed for its advantages of reducing crosstalk and area. However, serializing parallel buses tends to increase bit transition and power dissipation. Several coding schemes, such as serial followed by encoding (SE) and transition inversion coding (TIC), have been proposed to reduce bit transition. TIC is capable of decreasing transitions by 15% compared to th... View full abstract»

• ### Statistical Run-Time Verification of Analog Circuits in Presence of Noise and Process Variation

Publication Year: 2013, Page(s):1811 - 1822
Cited by:  Papers (2)
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Noise and process variation present a practical limit on the performance of analog circuits. This paper proposes a methodology for modeling and verification of analog designs in the presence of shot noise, thermal noise, and process variations. The idea is to use stochastic differential equations to model noise in additive and multiplicative form and then combine process variation due to 0.18 �... View full abstract»

• ### Formal Worst-Case Analysis of Crosstalk Noise in Mesh-Based Optical Networks-on-Chip

Publication Year: 2013, Page(s):1823 - 1836
Cited by:  Papers (18)
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Crosstalk noise is an intrinsic characteristic as well as a potential issue of photonic devices. In large scale optical networks-on-chips (ONoCs), crosstalk noise could cause severe performance degradation and prevent ONoC from communicating properly. The novel contribution of this paper is the systematical modeling and analysis of the crosstalk noise and the signal-to-noise ratio (SNR) of optical... View full abstract»

• ### CASSER: A Closed-Form Analysis Framework for Statistical Soft Error Rate

Publication Year: 2013, Page(s):1837 - 1848
Cited by:  Papers (13)
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CMOS designs in the deep submicrometer era require statistical methods to accurately estimate the circuit soft error rate (SER). However, process variation increases the complexity of statistical characteristics related to transient faults, leading to considerable uncertainty in the behavior of soft errors. Regardless of the methods used, current statistical SER (SSER) frameworks invariably involv... View full abstract»

• ### Algorithm-Driven Architectural Design Space Exploration of Domain-Specific Medical-Sensor Processors

Publication Year: 2013, Page(s):1849 - 1862
Cited by:  Papers (3)
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Data-driven machine-learning techniques enable the modeling and interpretation of complex physiological signals. The energy consumption of these techniques, however, can be excessive, due to the complexity of the models required. In this paper, we study the tradeoffs and limitations imposed by the energy consumption of high-order detection models implemented in devices designed for intelligent bio... View full abstract»

• ### Exploiting Replicated Cache Blocks to Reduce L2 Cache Leakage in CMPs

Publication Year: 2013, Page(s):1863 - 1877
Cited by:  Papers (2)
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Modern chip multiprocessors (CMPs) employ large L2 caches to reduce the performance gap between processors and off-chip memory. However, as the size of an L2 cache increases, its leakage power consumption also becomes a major contributor to the total power dissipation. Managing the leakage power of L2 caches, therefore, is an important issue in realizing low-power CMPs. In CMPs with private L2 cac... View full abstract»

• ### Novel Bio-Inspired Approach for Fault-Tolerant VLSI Systems

Publication Year: 2013, Page(s):1878 - 1891
Cited by:  Papers (4)
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Living organisms are complex systems, and yet they possess extremely high degrees of reliability. Since failures are local, their repair will often be taken on the local (cell) level. Engineers have long sought systems that could offer similar reliability and have relatively recently started trying to integrate ideas inspired by nature into the modern silicon technology of today. While bio-inspire... View full abstract»

• ### New Crosstalk Avoidance Codes Based on a Novel Pattern Classification

Publication Year: 2013, Page(s):1892 - 1902
Cited by:  Papers (2)
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The crosstalk delay associated with global on-chip interconnects becomes more severe in deep submicrometer technology, and hence can greatly affect the overall system performance. Based on a delay model proposed by Sotiriadis , transition patterns over a bus can be classified according to their delays. Using this classification, crosstalk avoidance codes (CACs) have been proposed to alleviate the ... View full abstract»

• ### Mitigating the Impact of Process Variation on the Performance of 3-D Integrated Circuits

Publication Year: 2013, Page(s):1903 - 1914
Cited by:  Papers (1)
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Three-dimensional die-stacking architectures have been proposed as a promising solution to the increasing interconnect delay that is observed in scaled technologies. Although prior research has extensively evaluated the performance advantage of moving from a 2-D to a 3-D design style, the impact of process parameter variations on 3-D designs has not been studied in detail. In this paper, we attemp... View full abstract»

• ### Design and Evaluation of High-Performance Processing Elements for Reconfigurable Systems

Publication Year: 2013, Page(s):1915 - 1927
Cited by:  Papers (2)
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In this paper, we present the design and evaluation of two new processing elements for reconfigurable computing. We also present a circuit-level implementation of the data paths in static and dynamic design styles to explore the various performance-power tradeoffs involved. When implemented in IBM 90-nm CMOS process, the 8-b data paths achieve operating frequencies ranging over 1 GHz both for stat... View full abstract»

• ### 1-V Low-Power Programmable Rail-to-Rail Operational Amplifier With Improved Transconductance Feedback Technique

Publication Year: 2013, Page(s):1928 - 1935
Cited by:  Papers (6)
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A low-power process-independent programmable transconductance rail-to-rail operational amplifier (OpAmp) is proposed. It employs an improved transconductance feedback loop that senses the transconductance (gmT) accurately and enforces it to be equal to the conductance of a reference resistor. Experimental results in a 0.13- μm standard CMOS technology under a 1-V power supply dem... View full abstract»

• ### Efficient VLSI Implementation of $2^{{n}}$ Scaling of Signed Integer in RNS ${{2^{n}-1, 2^{n},2^{n}+1}}$

Publication Year: 2013, Page(s):1936 - 1940
Cited by:  Papers (9)
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Scaling is a problematic operation in residue number system (RNS) but a necessary evil in implementing many digital signal processing algorithms for which RNS is particularly good. Existing signed integer RNS scalers entail a dedicated sign detection circuit, which is as complex as the magnitude scaling operation preceding it. In order to correct the incorrectly scaled negative integer in residue ... View full abstract»

• ### Integrated Power and Clock Distribution Network

Publication Year: 2013, Page(s):1941 - 1945
Cited by:  Papers (1)
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In this brief, we investigate and propose solutions for integrating the clock and power distribution networks all the way to circuit level. The aim is to reduce metal requirements, routing complexity, and power. The concept of an integrated power and clock distribution network (IPCDN) is proposed in order to eliminate the need for the global and local clock distribution networks. In IPCDN, a diffe... View full abstract»

• ### On the Design of RNS Reverse Converters for the Four-Moduli Set ${bf{2^{mmb n}+1, 2^{mmb n}-1, 2^{mmb n}, 2^{{mmb n}+1}+1}}$

Publication Year: 2013, Page(s):1945 - 1949
Cited by:  Papers (11)
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In this brief, we propose a method to design efficient adder-based converters for the four-moduli set {2n+1, 2n-1, 2n, 2n+1+1} with n odd, which provides a dynamic range of 4n+1 bits for the residue number system (RNS). This method hierarchically applies the mixed radix approach to balanced pairs of residues in two levels. With the proposed method, only ... View full abstract»

• ### 366-kS/s 1.09-nJ 0.0013-mm2 Frequency-to-Digital Converter Based CMOS Temperature Sensor Utilizing Multiphase Clock

Publication Year: 2013, Page(s):1950 - 1954
Cited by:  Papers (11)
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A smart temperature sensor in 65-nm CMOS, utilizing CMOS ring oscillators, consumes 1.09 nJ at a conversion rate of 366 kS/s. This is achieved by the direct temperature-to-digital conversion method implemented in the frequency-to-digital converter. The algorithm utilized in the fine code generator makes it possible to increase the resolution of the sensor efficiently. Compared to previous work, th... View full abstract»

• ### Sparsification of Dense Capacitive Coupling of Interconnect Models

Publication Year: 2013, Page(s):1955 - 1959
Cited by:  Papers (1)
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Parasitic elements play a major role in advanced circuit design and pose considerable run-time and memory problems for the post-layout verification, especially in the case of full-chip extraction. This brief presents a realizable R(L)C(M)-netlist-in-R(L)C(M)-netlist-out method to sparsify and reduce the capacitive coupling parasitics in circuits with interconnect lines. The method is applicable in... View full abstract»

• ### VLSI Architecture for Layered Decoding of QC-LDPC Codes With High Circulant Weight

Publication Year: 2013, Page(s):1960 - 1964
Cited by:  Papers (10)
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In this brief, we propose a high-throughput layered decoder architecture to support a broader family of quasicyclic low-density parity-check (QC-LDPC) codes, whose parity-check matrices are constructed from arrays of circulant submatrices. Each nonzero circulant submatrix is a superposition of K cyclic-shifted identity matrices, where the circulant weight K ≥ 1. We propose a novel layered d... View full abstract»

• ### IEEE Transactions on Very Large Scale Integration (VLSI) Systems society information

Publication Year: 2013, Page(s): C3
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## Aims & Scope

Design and realization of microelectronic systems using VLSI/ULSI technologies requires close collaboration among scientists and engineers in the fields of systems architecture, logic and circuit design, chips and wafer fabrication, packaging, testing, and systems applications. Generation of specifications, design, and verification must be performed at all abstraction levels, including the system, register-transfer, logic, circuit, transistor, and process levels. To address this critical area through a common forum, the IEEE Transactions on VLSI Systems was founded.

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## Meet Our Editors

Editor-in-Chief

Krishnendu Chakrabarty
Department of Electrical Engineering
Duke University
Durham, NC 27708 USA
Krish@duke.edu