By Topic

IEEE Transactions on Computers

Issue 12 • Date Dec 1993

Filter Results

Displaying Results 1 - 13 of 13
  • Design of a fault-tolerant three-dimensional dynamic random-access memory with on-chip error-correcting circuit

    Publication Year: 1993, Page(s):1453 - 1468
    Cited by:  Papers (15)  |  Patents (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1200 KB)

    Most current-generation multimegabit dynamic random-access memory (DRAM) chips use three-dimensional storage capacitors where the charge is stored on a vertically integrated trench-type structure and are highly vulnerable to alpha particles, which frequently create plasma shorts between two adjoining trench capacitors on the same word line, resulting in uncorrectable double-bit soft errors. The au... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Fast simulation of highly dependable systems with general failure and repair processes

    Publication Year: 1993, Page(s):1440 - 1452
    Cited by:  Papers (17)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1336 KB)

    An approach for simulating models of highly dependable systems with general failure and repair time distribution is described. The approach combines importance sampling with event rescheduling in order to obtain variance reductions in such rare event simulations. The approach is general in nature and allows a variety of features commonly arising in dependability modeling to be simulated effectivel... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A recursive carry-lookahead/carry-select hybrid adder

    Publication Year: 1993, Page(s):1495 - 1499
    Cited by:  Papers (32)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (444 KB)

    The author presents a very fast adder for double-precision mantissas, which is an improvement on T. Lynch and E. E. Swartzlandes, Jr.'s spanning tree carry lookahead adder or redundant cell adder (see ibid., vol. 41, 1992) which was implemented using the Am29050 microprocessor. The adder presented is faster than theirs mainly because Manchester carry chains of various lengths are used instead of c... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Dynamic load balancing in very large shared-nothing hypercube database computers

    Publication Year: 1993, Page(s):1425 - 1439
    Cited by:  Papers (6)  |  Patents (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1256 KB)

    Two relational join strategies, broadcast-based join and bucket-based join, have been recently proposed for the hypercube interconnection topology. The first strategy, however, incurs many unnecessary comparisons of pairs of tuples of the two relations. Although the second technique compares only tuples of the relevant buckets, it may suffer from potential load imbalance, which is most critical to... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A class of (12, 8) codes for correcting single errors and detecting double errors within a nibble

    Publication Year: 1993, Page(s):1504 - 1506
    Cited by:  Papers (1)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (232 KB)

    A class of (12, 8) codes is given that corrects all single errors, and detects all double errors in the three nibbles. It is shown that there exist three distinct solutions to this problem. One of these can be implemented with an LS636/7 chip. It is also shown that there do not exist any other codes except these three which correct all single errors and detect adjacent double errors confined to a ... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Noise modeling effects in redundant synchronizers

    Publication Year: 1993, Page(s):1487 - 1494
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (636 KB)

    The effects of redundancy and masking on the reliability of synchronizer circuits in the presence of metastability are considered. It is shown that in the jitter model developed by L. Kleeman (1990), in which circuit noise effects are considered, redundancy improves the probability of metastable failure of synchronizers, contrary to Kleeman's claim. A stochastic model that relates the noise model ... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Introducing a new cache design into vector computers

    Publication Year: 1993, Page(s):1411 - 1424
    Cited by:  Papers (4)  |  Patents (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1276 KB)

    Introduces an innovative cache design for vector computers, called prime-mapped cache. By utilizing the special properties of a Mersenne prime, the new design does not increase the critical path length of a processor, nor does it increase the cache access time as compared to existing cache organizations. The prime-mapped cache minimizes cache miss ratio caused by line interferences that have been ... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Fast self-routing permutation switching on an asymptotically minimum cost network

    Publication Year: 1993, Page(s):1469 - 1479
    Cited by:  Papers (13)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1028 KB)

    A self-routing permutation network with O((n lg n)) switches and O(lg2n) routing time, where lg denotes log2, is presented. More generally, a permutation network with O(kn1+1k/) cost and O(k lg n) routing time for any k, 1⩽k lg n, is described. This improves D. Nassimi and J. Sahni's (1982) routing algorithm that gives O(k lg3 n) routing time for the... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Multiple-way network partitioning with different cost functions

    Publication Year: 1993, Page(s):1500 - 1504
    Cited by:  Papers (26)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (480 KB)

    An adaptation to multiple blocks of a two-block network partitioning algorithm by Krishnamurthy was previously presented and analyzed by the author (see ibid., vol.38, p.62-81, 1989). The algorithm assumed one of several possible generalizations of two-way partitioning to multiple-way partitioning. The problem of adapting this algorithm to work with different generalizations more suitable for othe... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • NP-hard module rotation problems

    Publication Year: 1993, Page(s):1506 - 1510
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (404 KB)

    Preplaced circuit modules may be rotated to improve performance and/or routability. It is shown that several simple versions of the module rotation problem are NP-hard View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Fault-tolerant ring embedding in de Bruijn networks

    Publication Year: 1993, Page(s):1480 - 1486
    Cited by:  Papers (41)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (592 KB)

    A method of embedding a ring in a d-ary de Bruijn multiprocessor network in the event of multiple node (processor) failures is presented. In particular, the algorithm guarantees that a (2n-n-1)-node ring will be found in a binary de Bruijn network with a single faulty node, where 2n is the total number of nodes in the network. It is also shown that a (dn-1)-node ri... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Analysis of gate oxide shorts in CMOS circuits

    Publication Year: 1993, Page(s):1510 - 1516
    Cited by:  Papers (14)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (616 KB)

    The resistance dependence, voltage dependence, temperature dependence, and pattern dependence properties of CMOS logic gate operation in the presence of gate oxide shorts are analyzed. The analysis is based on realistic defect models that incorporate the resistive nature of gate oxide shorts and the difference between gate oxide shorts in n- and p-channel transistors View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Recursive pseudoexhaustive test pattern generation

    Publication Year: 1993, Page(s):1517 - 1521
    Cited by:  Papers (9)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (496 KB)

    A recursive technique for generating exhaustive patterns is presented. The method is optimal, i.e., in one experiment it covers exhaustively every block of k adjacent inputs in the first 2k vectors. Implementation methods based on characteristic functions of test vectors are provided. They include a parallel pattern generator employing an exclusive-or array, and two serial generators th... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.

Aims & Scope

The IEEE Transactions on Computers is a monthly publication with a wide distribution to researchers, developers, technical managers, and educators in the computer field.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief
Paolo Montuschi
Politecnico di Torino
Dipartimento di Automatica e Informatica
Corso Duca degli Abruzzi 24 
10129 Torino - Italy
e-mail: pmo@computer.org