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IEEE Micro

Issue 4 • July-Aug. 2013

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  • Front Cover

    Publication Year: 2013, Page(s): c1
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  • Table of Contents

    Publication Year: 2013, Page(s): c2
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  • Masthead

    Publication Year: 2013, Page(s): 1
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  • Reliability, Theme Issues, and Plagiarism

    Publication Year: 2013, Page(s): 2
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  • Call for Papers: IEEE Micro's Top Picks from the Computer Architecture Conferences

    Publication Year: 2013, Page(s): 3
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  • Reliability-Aware Microarchitecture Design [Guest editor's introduction]

    Publication Year: 2013, Page(s):4 - 5
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  • Coping with Parametric Variation at Near-Threshold Voltages

    Publication Year: 2013, Page(s):6 - 14
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (676 KB) | HTML iconHTML

    Near-threshold voltage computing (NTC) promises significant improvement in energy efficiency. Unfortunately, when compared to conventional, super-threshold voltage computing (STC), NTC is more sensitive to parametric variation. This results in not only slower and leakier cores, but also substantial speed and power differences between the cores in a many-core chip. NTC's potential cannot be unlocke... View full abstract»

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  • Computing Now [Advertisement]

    Publication Year: 2013, Page(s): 15
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  • Improving Throughput of Power-Constrained Many-Core Processors Based on Unreliable Devices

    Publication Year: 2013, Page(s):16 - 24
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (610 KB) | HTML iconHTML

    Using slightly less device-level redundancy than is necessary to make all processor cores defect free actually makes cores smaller, faster, and more power efficient. Under the same power and yield constraints, a carbon nanotube processor with less device-level redundancy can provide 1.75x higher throughput, while also being nearly 2x smaller than a similar processor that has more device-level redu... View full abstract»

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  • Build Your Career [Advertisement]

    Publication Year: 2013, Page(s): 25
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  • Resilient High-Performance Processors with Spare RIBs

    Publication Year: 2013, Page(s):26 - 34
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1737 KB) | HTML iconHTML

    Resilience to defects and parametric variations is of the utmost concern for future technology generations. Traditional redundancy to repair defects, however, can incur performance penalties owing to multiplexing. This article presents a processor design that incorporates bit-sliced redundancy along the data path. This approach makes it possible to tolerate defects without hurting performance, bec... View full abstract»

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  • Active Guardband Management in Power7+ to Save Energy and Maintain Reliability

    Publication Year: 2013, Page(s):35 - 45
    Cited by:  Papers (21)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (840 KB) | HTML iconHTML

    Microprocessor voltage levels traditionally include substantial margin to ensure reliable operation despite variations in manufacturing, workload, and environmental parameters. This margin allows the microprocessor to function correctly during worst-case conditions, but during typical operation it is larger than necessary and wastes energy. The authors present a mechanism that reduces excess volta... View full abstract»

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  • A Cross-Layer Technology-Based Study of How Memory Errors Impact System Resilience

    Publication Year: 2013, Page(s):46 - 55
    Cited by:  Papers (7)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1673 KB) | HTML iconHTML

    Highly scaled technologies at and beyond the 22-nm node exhibit increased sensitivity to various scaling-related problems that conspire to reduce the overall reliability of integrated circuits and systems. In prior technology nodes, the assumption was that manufacturing technology was responsible for ensuring device reliability. This basic assumption is no longer tenable. Trying to contain reliabi... View full abstract»

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  • Evaluating Overheads of Multibit Soft-Error Protection in the Processor Core

    Publication Year: 2013, Page(s):56 - 65
    Cited by:  Papers (9)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (414 KB) | HTML iconHTML

    The Svalinn framework provides comprehensive analysis of multibit error protection overheads to facilitate better architecture-level design choices. supported protection techniques include hardening, parity, error-correcting code, parity prediction, residue codes, and spatial and temporal redundancy. The overheads of these are characterized via synthesis and, as a case study, presented here in the... View full abstract»

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  • Automating Stressmark Generation for Testing Processor Voltage Fluctuations

    Publication Year: 2013, Page(s):66 - 75
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2236 KB) | HTML iconHTML

    Rapid current changes (large di/dt) can lead to significant power supply voltage droops and timing errors in modern microprocessors. To test a processor's resilience to such errors and determine appropriate operating conditions, engineers generally create manual di/dt stressmarks that have large current variations at close to the power distribution network's resonance frequency to induce large vol... View full abstract»

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  • Microsoft Tells Court That Without FRAND, Standard-Setting Would Be "Blatant Antitrust Violation"

    Publication Year: 2013, Page(s):76 - 77
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1282 KB) | HTML iconHTML

    This column discusses Microsoft's attempt to argue the necessity of fair, reasonable, and nondiscriminatory (FRAND) licensing for patents essential to practicing a standard. In regard to a case under appeal in which Apple and Motorola sued each other over several Moto standards-essential patents (SEPs), Microsoft argues that standardization is anticompetitive unless owners of SEPs promise to licen... View full abstract»

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  • Platform Conflicts [Micro Economics]

    Publication Year: 2013, Page(s):78 - 79
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  • Membership [Advertisement]

    Publication Year: 2013, Page(s): 80
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  • Jobs Board [Advertisement]

    Publication Year: 2013, Page(s): c3
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  • Rockstars of Big Data [Advertisement]

    Publication Year: 2013, Page(s): c4
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Aims & Scope

IEEE Micro addresses users and designers of microprocessors and microprocessor systems, including managers, engineers, consultants, educators, and students involved with computers and peripherals, components and subassemblies, communications, instrumentation and control equipment, and guidance systems.

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Meet Our Editors

Editor-in-Chief
Erik R. Altman
School of Electrical and Computer Engineering
IBM T.J. Watson Research Center