By Topic

Display Technology, Journal of

Issue 9 • Date Sept. 2013

Filter Results

Displaying Results 1 - 23 of 23
  • Front Cover

    Page(s): C1
    Save to Project icon | Request Permissions | PDF file iconPDF (343 KB)  
    Freely Available from IEEE
  • Journal of Display Technology - publication information

    Page(s): C2
    Save to Project icon | Request Permissions | PDF file iconPDF (136 KB)  
    Freely Available from IEEE
  • Table of contents

    Page(s): 685 - 686
    Save to Project icon | Request Permissions | PDF file iconPDF (156 KB)  
    Freely Available from IEEE
  • Foreword [Special Issue on the 8th International Thin-Film Transistor Conference (ITC 2012)]

    Page(s): 687
    Save to Project icon | Request Permissions | PDF file iconPDF (85 KB)  
    Freely Available from IEEE
  • Be-Doped ZnO Thin-Film Transistors and Circuits Fabricated by Spray Pyrolysis in Air

    Page(s): 688 - 693
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1012 KB) |  | HTML iconHTML  

    We report the fabrication of zinc oxide (ZnO) thin-film transistors (TFTs) and simple integrated circuits by spray pyrolysis, and examine the role of beryllium (Be) as the chemical dopant. Doping is achieved through addition of Be-acetylacetonate into the parent Zn-acetate precursor solution followed by film deposition through spray pyrolysis. The microstructural properties of as-grown Be-ZnO films with different dopant concentrations are investigated using a combination of atomic force microscopy and x-ray diffraction techniques, which show the formation of polycrystalline films. Introduction of Be is found to impact the degree of crystallinity of ZnO films where a dramatic decrease in the average grain size is observed with increasing Be concentration. To assess the effects of Be-doping on the electrical properties of ZnO films we have fabricated Be-ZnO based TFTs using different doping concentrations. The average electron mobility calculated from these transistors is on the order of ~ 2 cm2·V-1·s-1 with the threshold voltage (VTH) exhibiting a strong dependence on Be concentration. The ability to control VTH through the introduction of Be has been exploited for the fabrication of unipolar inverters with symmetric trip-voltages and good noise margins. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Effects of Gate Insulator on Thin-Film Transistors With ZnO Channel Layer Deposited by Plasma-Assisted Atomic Layer Deposition

    Page(s): 694 - 698
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (776 KB) |  | HTML iconHTML  

    Zinc oxide (ZnO) thin films have attracted significant attention for application in thin-film transistors (TFTs) due to their specific characteristics, such as high mobility and transparency. The atomic layer deposition (ALD) thin film is deposited with alternating exposures of a source gas and oxidant. The ALD method keeps fabrication temperature of ZnO TFTs low. In this study, we investigated the effects of gate insulator properties on the performance of TFTs with a ZnO channel layer deposited by plasma-assisted ALD (PAALD). The TFTs with Al2O3 gate insulator indicated high performance (5.1 cm2/V·s field effect mobility) without thermal annealing. This result indicated a high-performance ZnO TFT with films deposited by PAALD can be obtained at temperatures below 100°C. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Effect of {\hbox {SiO}}_{2} and/or {\hbox {SiN}}_{x} Passivation Layer on Thermal Stability of Self-Aligned Coplanar Amorphous Indium–Gallium–Zinc–Oxide Thin-Film Transistors

    Page(s): 699 - 703
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (981 KB) |  | HTML iconHTML  

    We report the post-annealing effect on the performance of amorphous indium-gallium-zinc-oxide (a-IGZO) thin-film transistors (TFTs) with self-aligned coplanar structure. The a-IZGO layer was passivated with SiO2 or SiNx by plasma enhanced chemical vapor deposition (PECVD). The field-effect mobility of a-IGZO TFT with SiNx is almost unchanged by extending the post-annealing time at 250 °C, but that of SiO2 passivated TFT significantly degrades by increasing annealing time. It is found that the resistivity of the a-IGZO under SiNx is low enough and thus can be good conduction path, leading to the high performance TFT. It is also found that the interface trap density (Nit) between a-IGZO TFT with SiNx passivation decreases from 3.0×1011 to 1.54×1011 cm-2 eV-1, and the stability of the a-IGZO TFT with SiNx passivation is significantly improved by long post-annealing. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Effect of Aluminum and Gallium Doping on the Performance of Solution-Processed Indium Oxide Thin-Film Transistors

    Page(s): 704 - 709
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1396 KB) |  | HTML iconHTML  

    Thin-film transistors (TFTs) with indium gallium oxide and aluminum indium oxide as a channel layer were fabricated via an aqueous route with low temperature annealing. The effects of chemical composition on electrical performance were examined. The fabricated IGO and AIO TFTs exhibited mobility in the range of 3.9-10.7 cm 2·V-1·s-1 with an on-to-off current ratio over 106 and a sub-threshold swing of below 0.7 V/dec at the optimized composition. The optimized IGO and AIO thin-films were in an amorphous phase, which has an advantage in large area uniformity. Finally, we performed a positive and negative bias test on the optimized IGO and AIO TFTs to understand the resistance to external bias stress. The turn-on voltage shift of the optimized IGO and AIO TFTs, annealed at 300 °C, were 1.45 V (negative bias stress), and 1.56 V (positive bias stress) with 3600 s stress, respectively. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Solution-Processed Dual-Gate Polymer Field-Effect Transistors for Display Applications

    Page(s): 710 - 714
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (619 KB) |  | HTML iconHTML  

    We describe the advantages of dual-gate thin-film transistors (TFTs) for display applications. We show that in TFTs with active semiconductor layers composed of diketopyrrolopyrrole-naphthalene copolymer, the on-current is increased, the off-current is reduced, and the sub-threshold swing is improved compared to single-gate devices. Charge transport measurements in steady-state and under non-quasi-static conditions reveal the reasons for this improved performance. We show that in dual-gate devices, a much smaller fraction of charge carriers move in slow trap states. We also compare the activation energies for charge transport in the top-gate and bottom-gate configurations. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Stability Studies on Nitrogen Doped p-ZnO (NZO) Thin Films Grown by Reactive Magnetron Sputtering

    Page(s): 715 - 722
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1382 KB) |  | HTML iconHTML  

    Nitrogen doped ZnO (NZO) thin films, at different N2 flow rates have been deposited on glass substrates by pulsed DC reactive magnetron sputtering technique. The effect of N2 flow rate (1.0 sccm - 3.0 sccm) on the structural, optical, electrical and chemical state of N has been studied. With the effect of N2 flow rate: the crystallinity of the films decreased, tensile stress is developed, optical transmittance decreased (80% to 60%), conductivity decreased till 1.5 sccm and films were n-type conducting. At 2.0 sccm and 2.5 sccm of N2 flow rates, NZO thin films showed p-type conductivity. The changes in the magnitude and type of conductivity have a direct relation with the changes observed in N-chemical state in ZnO lattice. p- NZO thin films are electrically unstable; this instability has been explained based on the changes occurred in the N chemical states, resulting from the stress release in NZO lattice. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Plastic Compatible Sputtered {\hbox {Ta}}_{2}{\hbox {O}}_{5} Sensitive Layer for Oxide Semiconductor TFT Sensors

    Page(s): 723 - 728
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1645 KB) |  | HTML iconHTML  

    The effect of post-deposition annealing temperature on the pH sensitivity of room temperature RF sputtered Ta2O5 was investigated. Structural and morphological features of these films were analyzed before and after annealing at various temperatures. The deposited films are amorphous up to 600 °C and crystallize at 700 °C in an orthorhombic phase. Electrolyte-insulator-semiconductor (EIS) field effect based sensors with an amorphous Ta2O5 sensing layer showed pH sensitivity above 50 mV/pH. For sensors annealed above 200 °C pH sensitivity decreased with increasing temperature. Stabilized sensor response and maximum pH sensitivity was achieved after low temperature annealing at 200 °C, which is compatible with the use of polymeric substrates and application as sensitive layer in oxides TFT-based sensors. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Extended-Gate ISFETs Based on Sputtered Amorphous Oxides

    Page(s): 729 - 734
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1083 KB) |  | HTML iconHTML  

    We present the results obtained with an extended-gate ISFET totally based on amorphous oxides (GIZO as the semiconductor, Ta2O5:SiO2 as the dielectric and Ta2O5 as the sensitive layer). A full characterization of the device was performed with constant ionic strength pH buffer solutions, revealing a sensitivity of 40 mV/pH with small hysteresis, and good linearity in the pH 4-pH 10 range buffer solutions. These results clearly show that it is possible to produce room-temperature disposable and low cost bio-sensors. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • p-Type {\hbox {Cu}}_{x}{\hbox {O}} Thin-Film Transistors Produced by Thermal Oxidation

    Page(s): 735 - 740
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1081 KB) |  | HTML iconHTML  

    Thin-films of copper oxide $({hbox{Cu}}_{x}{hbox{O}})$ were produced by thermal oxidation of metallic copper (Cu) at different temperatures (150–450$ ^{circ}{hbox{C}}$). The films produced at temperatures of 200, 250 and 300 $ ^{circ}{hbox{C}}$ showed high Hall motilities of 2.2, 1.9 and 1.6 ${hbox{cm}}^{2} {hbox{V}}^{-1}{hbox{s}}^{-1}$, respectively. Single ${hbox{Cu}}_{2}{hbox{O}}$ phases were obtained at 200$ ^{circ}{hbox{C}}$ and its conversion to CuO starts at 250$ ^{circ}{hbox{C}}$. For lower thicknesses $sim$ 40 nm, the films oxidized at 250$ ^{circ}{hbox{C}}$ showed a complete conversion to CuO phase. Successful thin-film transistors (TFTs) were produce by thermal oxidation of a 20 nm Cu film, obtaining p-type ${hbox{Cu}}_{2}{hbox{O}}$ (at 200$ ^{circ}{hbox{C}}$) and CuO (at 250$ ^{circ}{hbox{C}}$ ) with On/Off ratios of ${hbox{6}}times {hbox{10}}^{1}$ and ${hbox{1}}times {hbox{10}}^{2}$, respectively. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Impact of Underwater Laser Annealing on Polycrystalline Silicon Thin-Film Transistor for Inactivation of Electrical Defects at Super Low Temperature

    Page(s): 741 - 746
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1275 KB) |  | HTML iconHTML  

    We propose underwater laser annealing (WLA) for the inactivation of electrical defects in polycrystalline silicon thin-film transistors (poly-Si TFTs) at super low-temperature. This technique can reduce the temperature of inactivation process drastically, and it requires only UV laser and deionized water. We performed WLA after the fabrication of top-gate type poly-Si TFTs. After WLA, the field-effect mobility of poly-Si TFTs increased from 52 to 72 cm$^{2}/{hbox{V}}cdot{hbox{sec}}$ . The TFT surface was exposed to water vapor which was generated by laser irradiation, resulting that electrical defects were inactivated by active species in water vapor. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Short Channel Effects on LTPS TFT Degradation

    Page(s): 747 - 754
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1686 KB) |  | HTML iconHTML  

    Double-gate (DG) polysilicon thin-film transistors (TFTs) are considered very important for future large area electronics, due to their capability to electrically control TFT characteristics. The scope of this paper is to study how high performance DG polysilicon TFT degradation is affected by shrinking of the channel length. We applied equivalent dc stress in DG TFTs of different top gate length ${L}_{rm top}$, with channel width ${W} = 8 mu$m and bottom gate length fixed at ${L}_{rm bot} = 4 mu$m. Also, to ensure that we only see effects from the top gate operation, the bottom gate bias was kept constant at ${-}$3 V, pushing the carriers towards the top interface. Degradation seemed to be much more intense in the longer device, despite the scaling of the stress field. This could be attributed to the larger number of sub-boundaries and grain boundaries as ${L}_{rm top}$ increases, causing larger scattering of the carriers towards the top interface and larger grain-boundary state creation. Low frequency noise measurements support the conclusions regarding the proposed degradation mechanisms of DG polysilicon TFTs with shrinking channel length. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Electrochromic Electrochemical Transistors Gated With Polyelectrolyte-Decorated Amyloid Fibrils

    Page(s): 755 - 759
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (942 KB) |  | HTML iconHTML  

    This paper presents the use of polyelectrolyte-decorated amyloid fibrils as gate electrolyte in electrochromic electrochemical transistors. Conducting polymer alkoxysulfonate poly(3,4-ethylenedioxythiophene) (PEDOT-S) and luminescent conjugate polymer poly(thiophene acetic acid) (PTAA) are utilized to decorate insulin amyloid fibrils for gating lateral poly(3,4-ethylenedioxythiophene):poly(styrene sulfonate) (PEDOT:PSS) electrochemical transistors. In this comparative work, four gate electrolytes are explored, including the polyelectrolytes and their amyloid-fibril complexes. The discrimination of transistor behaviors with different gate electrolytes is understood in terms of an electrochemical mechanism. The combination of luminescent polymers, biomolecules and electrochromic transistors enables multi functions in a single device, for example, the color modulation in monochrome electrochromic display, as well as biological sensing/labeling. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • {\hbox {In}}_{2} {\hbox {O}}_{3} Thin Film Paper Transistors

    Page(s): 760 - 763
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (470 KB) |  | HTML iconHTML  

    In this work, we report on the fabrication of hybrid n-channel thin film transistors using paper as substrate and gate insulator, and indium oxide (In2O3) thin films as channel layer, and contacts for the source, drain and gate respectively. Capacitor paper having 10 μm thickness was used. In2O3 thin films were grown by pulsed electron beam deposition method at room temperature. The gate leakage current was 20 nA at 5 V and the on/off current ratio up to 6×104, limited mainly by the gate leakage. The transfer characteristics -Id (Vgs)- showed a memory effect with a threshold voltage of 0.8 V in “0” state and -3.6 V in “1” state. The drain current-voltage characteristics family -Id (Vds)- showed saturation currents up to 3.5 mA in “1”state and about 500 μA in “0” state. The subthreshold swing was 0.3-0.5 V/decade. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Analysis of Kink Effect and Short Channel Effects in Fully Self-Aligned Gate Overlapped Lightly Doped Drain Polysilicon TFTs

    Page(s): 764 - 769
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1169 KB) |  | HTML iconHTML  

    Electrical characteristics of fully self-aligned gate overlapped lightly doped drain (FSA-GOLDD) polysilicon TFTs, fabricated with a spacer technology providing submicron (0.35 μm) LDD regions, have been analyzed by using two-dimensional numerical simulations. The numerical analysis was used to explain the observed reduced kink effect and short channel effects presented by FSA GOLDD devices, compared to SA devices. The reduction of the kink effect has been attributed to the reduced impact ionization rate, and related to reduced electric fields at the channel/LDD junction. In addition, the role of the LDD dose on the kink effect has been also investigated, clarifying the observed current inflection occurring in the kink effect regime and the LDD dose dependence of the breakdown. Reduced short channel effects were attributed to reduced floating body effects, since drain induced barrier lowering was apparently not affected by the SA GOLDD structure, when compared to SA devices. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Analysis of IGZO Thin-Film Transistors by XPS and Relation With Electrical Characteristics

    Page(s): 770 - 774
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1554 KB) |  | HTML iconHTML  

    The fabrication process and electrical characteristics of bottom-gate Indium Gallium Zinc Oxide (IGZO) thin-film transistors (TFTs) are reported in details. The influence of post-annealing ambient (Oxygen or Nitrogen) is studied. It has been found that characteristics of TFTs strongly depend on annealing conditions. TFTs with Oxygen annealing exhibit standard TFT characteristics. In this case, we have obtained a mobility of 7.2 cm2/V·s, a subthreshold swing of 0.3 V/decade, high Ion/Ioff of 107 and low leakage current of the order of 10-13 at Vgs = -20 V. In the meantime, TFTs without a post-annealing or with Nitrogen annealing exhibited poor characteristics; more particularly the channel could not be depleted in the reverse mode. To understand the origins of this phenomenon, IGZO films from these devices have been analyzed by X-Ray Photoelectron Spectroscopy (XPS). Experimental results show that IGZO layers after annealing in N2 have higher concentration of oxygen vacancies. This is consistent with our electrical results since it is assumed that conduction in IGZO films is the result of oxygen vacancies. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Open Access

    Page(s): 775
    Save to Project icon | Request Permissions | PDF file iconPDF (1155 KB)  
    Freely Available from IEEE
  • IEEE Xplore Digital Library

    Page(s): 776
    Save to Project icon | Request Permissions | PDF file iconPDF (1371 KB)  
    Freely Available from IEEE
  • Journal of Display Technology information for authors

    Page(s): C3
    Save to Project icon | Request Permissions | PDF file iconPDF (120 KB)  
    Freely Available from IEEE
  • [Blank page - back cover]

    Page(s): C4
    Save to Project icon | Request Permissions | PDF file iconPDF (5 KB)  
    Freely Available from IEEE

Aims & Scope

This publication covers the theory, design, fabrication, manufacturing and application of information displays and aspects of display technology.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief
Arokia Nathan
University of Cambridge
Cambridge, U.K.