By Topic

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Issue 9 • Date Sept. 2013

Filter Results

Displaying Results 1 - 20 of 20
  • Table of contents

    Publication Year: 2013, Page(s): C1
    Request permission for commercial reuse | PDF file iconPDF (84 KB)
    Freely Available from IEEE
  • IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems society information

    Publication Year: 2013, Page(s): C2
    Request permission for commercial reuse | PDF file iconPDF (132 KB)
    Freely Available from IEEE
  • Semi-Automatic Generation of Device Drivers for Rapid Embedded Platform Development

    Publication Year: 2013, Page(s):1293 - 1306
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1500 KB) | HTML iconHTML

    IP core integration into an embedded platform implies the implementation of a customized device driver complying with both the IP communication protocol and the CPU organization (single processor, SMP, AMP). Such a close dependence between driver and platform organization makes reuse of already existing device drivers very hard. Designers are forced to manually customize the driver code to any dif... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Design of Pin-Constrained General-Purpose Digital Microfluidic Biochips

    Publication Year: 2013, Page(s):1307 - 1320
    Cited by:  Papers (11)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1063 KB) | HTML iconHTML

    Digital microfluidic biochips are being increasingly used for biotechnology applications. The number of control pins used to drive electrodes is a major contributor to the fabrication cost for disposable biochips in a highly cost-sensitive market. Most prior work on pin-constrained biochip design determines the mapping of a small number of control pins to a larger number of electrodes according to... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Localized Stability Checking and Design of IC Power Delivery With Distributed Voltage Regulators

    Publication Year: 2013, Page(s):1321 - 1334
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1064 KB) | HTML iconHTML

    Placing multiple voltage regulators onto the die is an effective way of enabling distributed on-chip voltage regulation and provides significant benefits in suppressing various types of power supply noise. However, the complex interactions between the active voltage regulators and the large passive subnetwork may render the complete power delivery network (PDN) unstable, leading to design failures... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Through Silicon Via Aware Design Planning for Thermally Efficient 3-D Integrated Circuits

    Publication Year: 2013, Page(s):1335 - 1346
    Cited by:  Papers (8)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1361 KB) | HTML iconHTML

    3-D integrated circuits (3-D ICs) offer performance advantages due to their increased bandwidth and reduced wire-length enabled by through-silicon-via structures (TSVs). Traditionally TSVs have been considered to improve the thermal conductivity in the vertical direction. However, the lateral thermal blockage effect becomes increasingly important for TSV via farms (a cluster of TSV vias used for s... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Escape Routing for Staggered-Pin-Array PCBs

    Publication Year: 2013, Page(s):1347 - 1356
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (880 KB) | HTML iconHTML

    To accommodate the ever-growing pin number of complex printed circuit board (PCB) designs, the staggered pin array is introduced for modern designs with higher pin density. However, the escape routing for staggered pin arrays, which is a key component of PCB routing, is significantly different from that for grid arrays. This paper presents a routing algorithm for the escape routing for staggered-p... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Routing Challenges for Designs With Super High Pin Density

    Publication Year: 2013, Page(s):1357 - 1368
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (8027 KB) | HTML iconHTML

    Footprint scaling may reduce wire lengths when more metal layers are available for routing. To achieve optimal wire length, footprint should be very small in which case pin density will be extremely high. However, high pin density may lead to detailed routing failure. We demonstrate that there is a threshold pin density beyond which standard routing heuristics fail to access pins on the bottom lay... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • High-Quality Statistical Test Compression With Narrow ATE Interface

    Publication Year: 2013, Page(s):1369 - 1382
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (804 KB) | HTML iconHTML

    In this paper, we present a novel compression method and a low-cost decompression architecture that combine the advantages of both symbol-based and linear-based techniques and offer a very attractive unified solution that removes the barriers of existing test data compression techniques. Besides the traditional goals of high compression and short test application time, the proposed method also off... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Adjustable RF Mixers' Alternate Test Efficiency Optimization by the Reduction of Test Observables

    Publication Year: 2013, Page(s):1383 - 1394
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1038 KB) | HTML iconHTML

    A method for the optimization of the efficiency of alternate tests for adjustable RF mixers is presented in this paper. Alternate tests provide a cost- and time-effective substitute for their conventional specification-based counterparts by attempting to predict rather than directly measuring a circuit's performance from its response to suitable test stimuli. In order to provide post-manufacture y... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Detection, Diagnosis, and Recovery From Clock-Domain Crossing Failures in Multiclock SoCs

    Publication Year: 2013, Page(s):1395 - 1408
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (499 KB) | HTML iconHTML

    Clock-domain crossing (CDC) faults require careful post-silicon testing for multiclock circuits. Even when robust design methods based on synchronizers and design verification techniques are used, process variations can introduce subtle timing problems that affect data transfer across clock-domain boundaries for fabricated chips. We integrate solutions for detecting and locating CDC faults, and en... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Efficient Gröbner Basis Reductions for Formal Verification of Galois Field Arithmetic Circuits

    Publication Year: 2013, Page(s):1409 - 1420
    Cited by:  Papers (7)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (363 KB) | HTML iconHTML

    Galois field arithmetic is a critical component in communication and security-related hardware, requiring dedicated arithmetic architectures for better performance. In many Galois field applications, such as cryptography, the data-path size in the circuits can be very large. Formal verification of such circuits is beyond the capabilities of contemporary verification techniques. This paper addresse... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Functional Timing Analysis Made Fast and General

    Publication Year: 2013, Page(s):1421 - 1434
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (239 KB) | HTML iconHTML

    In contrast to structural timing analysis, functional timing analysis for circuit delay computation is accurate, but computationally expensive in refuting false critical paths. Despite recent progress on satisfiability-based functional timing analysis, the formulation generality and computation efficiency remain room for further improvement. This paper provides a unified view on different notions ... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Noise Companion State-Space Passive Macromodeling for RF/mm-Wave Circuit Design

    Publication Year: 2013, Page(s):1435 - 1439
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1811 KB) | HTML iconHTML

    Automatic macromodeling for passive linear systems is useful in RF/mm-wave circuit designs. Traditional macromodeling approaches only capture the port parameters of the systems, enabling small-signal (AC) and large-signal (transient, PSS, etc) analyses, but lack the capability of noise modeling which is very important in RF/mm-wave circuit designs. In this letter, we propose to account for noise i... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Oscillation-Based Prebond TSV Test

    Publication Year: 2013, Page(s):1440 - 1444
    Cited by:  Papers (11)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (5019 KB) | HTML iconHTML

    Testing the quality of prebond through-silicon vias (TSV) is a vital part of the Known-Good-Die test that is often necessary to retain a high compound yield for 3-D stacked integrated circuits. In this paper, we present a versatile prebond TSV test method applicable before wafer thinning when the deep end of the TSV is inaccessible as buried in the still-thick wafer. Technical merits include: 1) t... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Functional Broadside Tests With Incompletely Specified Scan-In States

    Publication Year: 2013, Page(s):1445 - 1449
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (95 KB) | HTML iconHTML

    Functional broadside tests address overtesting of delay faults by using reachable states as scan-in states. Since reachable states are, in general, fully specified, functional broadside tests are not amenable to the commonly used test data compression methods. This paper defines multicycle functional broadside tests whose scan-in states are incompletely specified. The first clock cycles of a test ... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Open Access

    Publication Year: 2013, Page(s): 1450
    Request permission for commercial reuse | PDF file iconPDF (1156 KB)
    Freely Available from IEEE
  • IEEE Copyright Form

    Publication Year: 2013, Page(s):1451 - 1452
    Request permission for commercial reuse | PDF file iconPDF (1589 KB)
    Freely Available from IEEE
  • IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems publication information

    Publication Year: 2013, Page(s): C3
    Request permission for commercial reuse | PDF file iconPDF (115 KB)
    Freely Available from IEEE
  • IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems information for authors

    Publication Year: 2013, Page(s): C4
    Request permission for commercial reuse | PDF file iconPDF (92 KB)
    Freely Available from IEEE

Aims & Scope

The purpose of this Transactions is to publish papers of interest to individuals in the area of computer-aided design of integrated circuits and systems composed of analog, digital, mixed-signal, optical, or microwave components.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief

VIJAYKRISHNAN NARAYANAN
Pennsylvania State University
Dept. of Computer Science. and Engineering
354D IST Building
University Park, PA 16802, USA
vijay@cse.psu.edu