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Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on

Issue 2 • Date Feb 1994

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Displaying Results 1 - 12 of 12
  • A cache-based method for accelerating switch-level simulation

    Page(s): 211 - 218
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (792 KB)  

    Switch-level simulation has become a common means of validating the behavior of MOS circuits. In this paper, we present a new cache-based simulation method that significantly reduces the cost of subnetwork evaluation during switch-level simulation. The method speeds up simulation by as much as a factor of two. While caching may require additional memory, the structural hierarchy can be exploited to quickly identify subnetworks computing identical functions, merge their cache tables, and significantly reduce the memory requirements View full abstract»

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  • Pattern matching and refinement hybrid approach to circuit comparison

    Page(s): 264 - 276
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1140 KB)  

    We present a new approach to circuit comparison which was developed to combine general applicability with most of the advantages of hierarchical processing. The basic principle of operation is the pattern matching of arbitrary subcircuits in larger circuits. Typically, a hierarchical schematic has to be compared with a flat netlist extracted from the layout. In our approach, this is accomplished by successive, bottom-up matching of schematic cells in the layout netlist, thus reconstructing the schematic hierarchy. The method is independent of circuit technology and design style. A sophisticated hierarchy handling scheme enables the usage of ill-structured schematic hierarchies. The typical problems in circuit comparison are overcome in a quite natural way by pattern matching. Real-life examples indicate the tool's suitability in function and performance. The hybrid approach is a mixture between the pattern matching approach and the traditional refinement technique. In this way, the advantages of both methods can be exploited View full abstract»

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  • Performance-driven interconnection optimization for microarchitecture synthesis

    Page(s): 137 - 149
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1092 KB)  

    This paper addresses the interconnection synthesis problem in microarchitecture-level designs. With emphasis on the speed of data movement operations, we propose algorithms that take into consideration the effect of each data-transfer-to-bus binding on the data transfer delay time. The delay time is calculated as a function of both data source load and data carrier (bus) load. By balancing loads among hardware components, the data transfer delay time (hence the total execution time) is shortened. We consider two types of problems: resource-constrained binding and performance-constrained binding. Two integer linear programming (ILP) formulations are derived to optimally solve the problems. In order to speed up the computation, a bipartite weighted matching method for the resource-constrained binding and a greedy merging method for the performance-constrained binding are also proposed. Both the ILP formulation generators and the heuristics have been programmed. Experimental results indicate that the proposed algorithms are indeed very effective in optimizing the performance aspect of the interconnection design View full abstract»

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  • A hybrid device simulator that combines Monte Carlo and drift-diffusion analysis

    Page(s): 201 - 210
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (776 KB)  

    A hybrid simulator suitable for modeling small semiconductor devices has been developed in which Monte Carlo and drift-diffusion models are combined. In critical device regions, the position-dependent coefficients of an extended drift-diffusion equation are extracted from a Monte Carlo simulation. Criteria for identifying these regions are described. Additional features which make the code more efficient are presented. First, a free-flight time calculation method using a new self-scattering algorithm is described. It allows for an efficient reduction of self-scattering events. Second, a unique Monte Carlo-Poisson coupling scheme has been developed which converges faster than all presently known schemes. It exploits the so-called Monte Carlo-drift diffusion coupling technique, which also forms the basis of the hybrid method. The simulator has been used to model submicron MOSFET's with gate lengths down to 0.15 μm. In addition to the non-local effects occurring in these devices, the performance of the hybrid simulation method is analyzed View full abstract»

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  • Models and algorithms for three-dimensional topography simulation with SAMPLE-3D

    Page(s): 219 - 230
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    Algorithms for general surface advancement, three-dimensional visibility, and convolution over a surface have been developed and coupled with physical models for pattern transfer. The resulting program, SAMPLE-3D, allows practical simulation of plasma etching and deposition processes on engineering workstations. The physical models are 3-D extensions of 2-D string and segment based models. The models include secondary effects, such as material density variations and damage enhanced etching. A general facet motion algorithm supports simple, isotropic, cosine-directional, and general surface orientation dependent processes. A 3-D grid of rectangular prismatic cells, which is updated by the advancing surface, contains an alternate topography representation for fast shadow and visibility calculation. The program is organized as a collection of modular functions for continued model and algorithm development. Guidelines for estimating CPU and memory requirements for various models and simulation cases are based on an analysis of the algorithms and data structures. Simple processes, such as lithography development, require 1-5 min of CPU time. Simulations involving integration over flux distributions, such as plasma etching and sputter deposition, require from 5-30 min for typical cases. Reflection or surface migration calculations require from 30-60 min. Physical memory of 4-32 megabytes is sufficient for many practical simulations View full abstract»

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  • A new approach to over-the-cell channel routing with three layers

    Page(s): 187 - 200
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    We introduce a new model for over-the-cell channel routing with three layers. The model consists of two channels and the routing area over a cell row between them. Three and two layers are available for routing in the channels and the over-the-cell routing area, respectively. We formulate the problem of over-the-cell routing as that of channel routing with additional constraints. Based on this formulation, we present an efficient over-the-cell routing algorithm that attempts to minimize the sum of channel densities of the trunks that remain in the channel. The effectiveness of our model and algorithm is demonstrated by our experimental results on industrial sea-of-gates array chips and a well-known benchmark circuit View full abstract»

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  • Exact and heuristic algorithms for the minimization of incompletely specified state machines

    Page(s): 167 - 177
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    In this paper we present two exact algorithms for state minimization of FSM's. Our results prove that exact state minimization is feasible for a large class of practical examples, certainly including most hand-designed FSM's. We also present heuristic algorithms, that can handle large, machine-generated, FSM's. The possibly many different reduced machines with the same number of states have different implementation costs. We discuss two steps of the minimization procedure, called state mapping and solution shrinking, that have received little prior attention to the literature, though they play a significant role in delivering an optimally implemented reduced machine. We also introduce an algorithm whose main virtue is the ability to cope with very general cost functions, while providing high performance View full abstract»

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  • On shifting blocks and terminals to minimize channel density

    Page(s): 178 - 186
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    We study in this paper the problem of minimizing channel density by simultaneously shifting the blocks that form the two sides of a channel and the terminals on the boundary of each block. Several special cases of this problem have been investigated, but no optimal algorithm was known for the general case. We present an optimal algorithm for solving this problem. For long channels, we also propose effective heuristic techniques to speed up our algorithm. Extensions as well as applications of our algorithms to detailed routing in building-block layout design are also discussed View full abstract»

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  • SPADES-ACE: a simulator for path delay faults in sequential circuits with extensions to arbitrary clocking schemes

    Page(s): 251 - 263
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    Testing of synchronous sequential circuits for path delay faults requires two sequences: a test sequence, that specifies the input values, and a clocking scheme, that specifies at what time units a fast clock should be applied. In this work, a fault simulator for path delay faults in synchronous sequential circuits is described, that has the following novel features. (1) For a given test sequence, all clocking schemes that have a single fast clock are simulated in parallel. (2) During the simulation process, it is possible to determine a minimal set of clocking schemes to achieve the same fault coverage as in (1). (3) Alternatively, it is possible to simulate the test sequence under a given clocking scheme, containing multiple fast clocks at arbitrary time units. (4) A path representation scheme is used, that allows efficient access to path delay faults detected by previous tests. Experimental results are presented to demonstrate these features and their effectiveness View full abstract»

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  • Automated transformation of algorithms into register-transfer level implementations

    Page(s): 150 - 166
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    This paper describes a high-level synthesis system, called CAMAD, for transforming algorithms into hardware implementation structures at register-transfer level. The algorithms are used to specify the behaviors of the hardware to be designed. They are first translated into a formal representation model which is based on timed Petri nets and consists of separate but related descriptions of control and data path. The formal model is used as an intermediate design representation and supports an iterative transformation approach to high-level synthesis. The basic idea is that once the behavioral specification is translated into the initial design representation, it can be viewed as a primitive implementation. Correctness-preserving transformations are then used to successively transform the initial design into an efficient implementation. Selection of transformations is guided by an optimization strategy which makes design decisions concerning operation scheduling, data path allocation, and control allocation simultaneously. The integration of these several synthesis subtasks has resulted in a better chance to reach the globally optimal solution. Experimental results show that our approach produces improved register-transfer designs, especially in the cases when the designed hardware consists of data paths and control logics that are tightly coupled View full abstract»

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  • An efficient nonenumerative method to estimate the path delay fault coverage in combinational circuits

    Page(s): 240 - 250
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1004 KB)  

    A method to estimate the coverage of path delay faults of a given test set, without enumerating paths, is proposed. The method is polynomial in the number of lines in the circuit, and thus allows circuits with large numbers of paths to be considered under the path delay fault model. Several levels of approximation, with increasing accuracy and increasing polynomial complexity, are proposed. Experimental results are presented to show the effectiveness and accuracy of the estimate in evaluating the path delay fault coverage. Combining this nonenumerative estimation method with a test generation method for path delay faults would yield a cost effective method to consider path delay faults in large circuits, which are beyond the capabilities of existing test generation and fault simulation procedures, that are based on enumeration of paths View full abstract»

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  • An efficient nonquasi-static diode model for circuit simulation

    Page(s): 231 - 239
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (792 KB)  

    Based on the partitioned-charge-based modeling approach, a general nonquasi-static dynamic charge element is derived to simulate both transient behavior and high-frequency characteristics of a semiconductor diode. A new model parameter τ is introduced to describe the dynamic charge redistribution time for a diode. By partitioning the total base charge into quasi-static (QS) and nonquasi-static (NQS) terms, a single-τ (level 2) diode model is first derived. By further dividing the NQS charge, a double-τ (level 3) diode model is proposed to describe different reverse recovery processes. In addition, a voltage-dependent equation is incorporated to the double-τ model into account for the dynamic charge partitioning. We show that the SPICE diode (level 1) model is included by setting τ to zero as a special case of the proposed models. The new diode model has been implemented in MISIM, a model independent SPICE-like simulation framework. Significant improvement in accuracy over the traditional SPICE diode model in both time and frequency domain has been demonstrated, while achieving the same or even better simulation speed and reliability View full abstract»

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Aims & Scope

The purpose of this Transactions is to publish papers of interest to individuals in the areas of computer-aided design of integrated circuits and systems.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief

VIJAYKRISHNAN NARAYANAN
Pennsylvania State University
Dept. of Computer Science. and Engineering
354D IST Building
University Park, PA 16802, USA
vijay@cse.psu.edu