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Electron Devices, IEEE Transactions on

Issue 8 • Date Aug. 2013

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  • Table of contents

    Page(s): C1 - 2442
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  • IEEE Transactions on Electron Devices publication information

    Page(s): C2
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  • A Warm Welcome to a New T-ED Editor

    Page(s): 2443
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  • Low-Field Behavior of Source-Gated Transistors

    Page(s): 2444 - 2449
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (922 KB) |  | HTML iconHTML  

    A physical description of low-field behavior of a Schottky source-gated transistor (SGT) is outlined where carriers crossing the source barrier by thermionic emission are restricted by JFET action in the pinch-off region at the drain end of the source. This mode of operation leads to transistor characteristics with low saturation voltage and high output impedance without the need for field relief at the edge of the Schottky source barrier and explains many characteristics of SGT observed experimentally. 2-D device simulations with and without barrier lowering due to the Schottky effect show that the transistors can be designed so that the current is independent of source length and thickness variations in the semiconductor. This feature together with the fact that the current in an SGT is independent of source-drain separation hypothesizes the fabrication of uniform current sources and other large-area analog circuit blocks with repeatable performance even in imprecise technologies such as high-speed printing. View full abstract»

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  • Characterization of RF-MOSFETs in Common-Source Configuration at Different Source-to-Bulk Voltages From S-Parameters

    Page(s): 2450 - 2456
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    Using a new test fixture that allows us to bias the bulk terminal through an additional compensated DC probe, a two-port S-measurement-based methodology to characterize RF-MOSFETs in common-source configuration is herein presented. In addition to obtaining S-parameters at different bulk-to-source voltages using a single two-port configured test-fixture, the proposal allows the analysis of the electrical parameters of a MOSFET that are influenced by the substrate effect when the frequency rises. Physically expected results are obtained for device's model parameters, allowing to accurately reproduce S-parameters up to 20 GHz. Furthermore, extracted parameters, such as threshold voltage, are in agreement with those obtained using well-established DC methods. This method allows one to characterize a four-terminal MOSFET from two-port small-signal measurements. View full abstract»

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  • Interface Trap Density of Gate-All-Around Silicon Nanowire Field-Effect Transistors With TiN Gate: Extraction and Compact Model

    Page(s): 2457 - 2463
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    Si/SiO2 interface trap charge distribution of cylindrical cross-sectioned gate-all-around silicon nanowire field-effect transistor is extracted by using three-dimensional simulation. While the interface chemistry of conventional gatestack ( Si/SiO2 polysilicon) in conventional planar devices is well documented, not much work is available on interface trap distribution Dit of alternate gatestacks (gatestacks employing alternate gate materials) in silicon nanowire MOSFET devices. Furthermore, a compact drain current model with interface trap charge parameter is presented. The model is based on gradual channel approximation and uses self-consistent calculation of interface trap charge and surface potential to reproduce experimental current-voltage characteristics. View full abstract»

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  • Tunable Bandgap in Bilayer Armchair Graphene Nanoribbons: Concurrent Influence of Electric Field and Uniaxial Strain

    Page(s): 2464 - 2470
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    In this paper, the effect of uniaxial strain on the electronic properties of bilayer armchair graphene nanoribbons (BLAGNRs) is theoretically investigated for the first time. Our calculations based on density functional theory (DFT) reveal the tunable nature of the electronic properties of BLAGNRs with the application of uniaxial strain. We further explore the simultaneous effect of perpendicular electric field and uniaxial strain on the electronic bandgap. The results show that as long as the strain induced bandgap is smaller than a critical value of 0.2 eV, the electric field can significantly modulate the bandgap. In addition, we modified nearest neighbor tight-binding (TB) parameters to include the effect of the hydrogen passivation, which results in an excellent agreement between the electronic bandstructures obtained from DFT and TB calculations. Finally, by employing the nonequilibrium Green's function formalism, an on-off conductance ratio as high as 105 is predicted for strained BLAGNRs. View full abstract»

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  • Complementary Role of Field and Temperature in Triggering ON/OFF Switching Mechanisms in {\rm Hf}/{\rm HfO}_{2} Resistive RAM Cells

    Page(s): 2471 - 2478
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    We present an investigation on the role of temperature and electric field as driving forces in the initiation of the resistive switching processes. The impact of temperature in both on- and off-states is analyzed in detail, using an electrothermal numerical model formulation. dc and pulsed temperature-dependent data, collected on scaled crossbar test structure cells, serially connected with an on-chip control transistor, are used to extract material information and are furthermore analyzed in conjunction with model outputs. With these results, further discussion is presented, suggesting points of attention for scaled cell design in the below-10-nm realm. View full abstract»

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  • The Effect of Germanium Fraction on High-Field Band-to-Band Tunneling in {\rm p}^{+} -SiGe/ {\rm n}^{+} -SiGe Junctions in Forward and Reverse Biases

    Page(s): 2479 - 2484
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1747 KB) |  | HTML iconHTML  

    The dependence of band-to-band tunneling in p+-Si1-xGex/n+-Si1-xGex homojunctions on Ge fraction and electric field is investigated in the range 2-3×108 V/m. Negative differential resistance (NDR) in forward bias is observed for each device with the highest peak tunneling-current density of 8.2 kA/cm2 without any postannealing step. Reverse-biased band-to-band tunneling, as relevant for tunneling field-effect transistors, is also measured. Tunneling via junction defects can mask band-to-band tunneling and the observation of NDR at forward bias confirms negligible tunneling via those defects. Both forward-biased and reverse-biased data are compared with models versus electric field and Ge fraction. View full abstract»

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  • Interplay Between Process-Induced and Statistical Variability in 14-nm CMOS Technology Double-Gate SOI FinFETs

    Page(s): 2485 - 2492
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (7170 KB) |  | HTML iconHTML  

    This paper presents a comprehensive simulation study of the interactions between long-range process and short-range statistical variability in a 14-nm technology node silicon-on-insulator FinFET. First, the individual and combined impact of the relevant variability sources, including random discrete dopants, fin line edge roughness (LER), gate LER, and metal gate granularity are studied for the nominal 20-nm physical gate-length FinFET design. This is followed by a comprehensive study of the interactions of the channel length, fin width and fin height systematic process variations with the combined statistical variability sources. The simulations follow a 3×3×3=27 experiment design that covers the process variability space, and 1000 statistical simulations are carried out at each node of the experiment. Both metal-gate-first and metal-gate-last technologies are considered. It is found that statistical variability is significantly dependent on the process-induced variability. The applicability of the Pelgrom law to the FinFET statistical variability, subject to long-range process variations, is also examined. Mismatch factor is strongly dependent on the process variations. View full abstract»

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  • Experimental Comparison Between Trigate p-TFET and p-FinFET Analog Performance as a Function of Temperature

    Page(s): 2493 - 2497
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1266 KB) |  | HTML iconHTML  

    This paper presents, for the first time, the experimental comparison between the p-type trigate FinFET and trigate p-TFET analog performances for devices fabricated on the same wafer. A careful analysis of the electrical characteristics is performed to choose the best bias conditions for the analog comparison between these devices. A higher intrinsic voltage gain is obtained for p-TFET devices because of their better output conductance, which is more than four orders of magnitude better than the one obtained for p-FinFET transistors at the same bias conditions from room temperature up to 150 °C. View full abstract»

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  • Wideband Impedance Model for Coaxial Through-Silicon Vias in 3-D Integration

    Page(s): 2498 - 2504
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    Coaxial through-silicon via (TSV) is a promising 3-D integration solution, which can offer lower coupling with its surrounding environment and achieve better electromagnetic compatibility and signal integrity than other TSV structures. In this paper, an analytical wideband equivalent circuit model is proposed for the impedance modeling of coaxial TSVs in 3-D integration. Closed-form formulas for calculations of the per-unit-length resistance and the inductance of both the isolation dielectric filled and silicon filled coaxial TSVs are derived from the theory of quasi-magnetostatic fields. These formulas appropriately capture the skin effect in metal as well as the eddy current effect in silicon. Therefore, they yield accurate results comparable with the full-wave solutions in a wideband frequency range. View full abstract»

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  • New Analysis Method for Time-Dependent Device-To-Device Variation Accounting for Within-Device Fluctuation

    Page(s): 2505 - 2511
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1621 KB) |  | HTML iconHTML  

    Variability of nanometer-size devices is a major challenge for circuit design. Apart from the as-fabricated variability, the postfabrication degradation introduces a time-dependent variability, originating from statistical distribution of charge location and number. The existing characterization techniques do not always capture the maximum degradation. Some of them does not separate the device-to-device variation from the charging fluctuation within the same device, either. The objective of this paper is to develop a new analysis method for characterizing time-dependent device-to-device variation, accounting for within-device fluctuation (TVF). The TVF captures the maximum degradation, separate device-to-device variation from within-device fluctuation, and reduce the data points by three orders of magnitude. It is shown that the popular data acquisition at discrete time points does not capture the fluctuation well and drain current must be measured continuously. The TVF shows that degradation has two components-a fluctuation with time and one whose discharge is not observed under a given bias. Although both of them increase with stress time, the correlation between them is weak, indicating two different origins. View full abstract»

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  • Sub-60-nm Extremely Thin Body {\rm In}_{x}{\rm Ga}_{1-x}{\rm As} -On-Insulator MOSFETs on Si With Ni-InGaAs Metal S/D and MOS Interface Buffer Engineering and Its Scalability

    Page(s): 2512 - 2517
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1586 KB) |  | HTML iconHTML  

    We report the operation of sub-60-nm deeply scaled InGaAs- and InAs-on-insulator (-OI) MOSFETs on Si substrates with MOS interface buffer engineering and Ni-InGaAs metal source/drain (S/D). InAs-OI MOSFETs provide 400% Ion enhancement, compared with an In0.53Ga0.47As control device with the same drain-induced-barrier-lowering (DIBL) of 100 mV/V, which is attributable to the mobility enhancement and the S/D parasitic resistance (RSD) reduction. In addition, InAs-OI MOSFETs with the MOS interface buffers show excellent electrostatic characteristics. InAs-OI MOSFETs with a channel length (Lch) of 55 nm shows small DIBL of 84 mV/V and subthreshold slope (S.S.) of 105 mV/dec, both of which do not significantly degrade with a decrease of Lch, thanks to the extremely thin channel thickness. In addition, from the simulation study, we have found that further vertical scaling and back biasing techniques can improve the control of short channel effect in InAs-OI MOSFETs. View full abstract»

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  • Scalable Virtual-Ground Multilevel-Cell Floating-Gate Flash Memory

    Page(s): 2518 - 2524
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1415 KB) |  | HTML iconHTML  

    An adequate gate coupling ratio (GCR) and compensation for floating-gate to floating-gate (FG-to-FG) coupling interference must be maintained to enable further scaling of virtual-ground multilevel-cell (MLC) FG flash memory. A high GCR of 0.6 is obtained using a novel bowl-shaped FG structure cell technology without sacrificing cell size. Increasing the GCR is important for reducing FG-to-FG coupling interference and achieving low-voltage operation. A novel array segmented virtual-ground architecture with bit-line isolation between neighboring segments and two-step programming with the channel hot electron injection threshold voltage compensation technique are proposed to reduce the number of neighboring cells that are programmed after programming a given cell, as well as the amount of threshold voltage (Vth) shift of the neighboring cells. Adoption of this programming approach realizes a reduction in the Vth shift caused by the FG-to-FG coupling interference in the bit-line direction, compared with conventional programming approaches, and the Vth shift is almost completely eliminated in the word-line direction without sacrificing program throughput. The proposed virtual-ground MLC FG cell, which is as small as 3F2/bit ( F is the minimum feature size) is successfully implemented into a test chip with good reliability. View full abstract»

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  • 2-D Compact Model for Drain Current of Fully Depleted Nanoscale GeOI MOSFETs for Improved Analog Circuit Design

    Page(s): 2525 - 2531
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (898 KB) |  | HTML iconHTML  

    Compact models for MOS devices are extremely useful as they can be incorporated in circuit simulators with sufficient accuracy. We present for the first time a 2-D surface-potential-based compact model for the drain current of nanoscale germanium-on-insulator (GeOI) MOSFETs including the interface-trapped and fixed-oxide charge densities at both front- and back-gates. The proposed drain current model is accurate, computationally efficient, and suitable for circuit simulation in the nanometer regime because no iterative loop is used anywhere. The drain current model includes velocity saturation, channel length modulation, carrier mobility degradation, and also the drain-induced barrier lowering. The model shows excellent concordance with the reported experimental transfer characteristic curves for both the high and low drain voltages and also exhibits good agreement for derivatives of drain current when compared with our TCAD simulation data for GeOI devices with channel length of 30 nm over a wide range of gate and drain bias conditions. Furthermore, our studies reveal that GeOI devices outperform silicon-on-insulator (SOI) counterparts in terms of analog figures of merit, such as transconductance, voltage gain, transconductance generation factor, and cut-off frequency, except the output conductance. View full abstract»

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  • Minority Carrier Transport and Their Lifetime in InGaAs/GaAsP Multiple Quantum Well Structures

    Page(s): 2532 - 2536
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    Minority carrier transport across InGaAs/GaAsP multiple quantum wells is studied by measuring the response of p-i-n and n-i-p GaAs solar cell structures. It is observed that the spectral response depends critically upon the width of the GaAsP barriers and the device polarity. Electron tunneling is not as efficient as hole tunneling due to a higher conduction band barrier. The spectral response depends on the relative magnitude of the carrier lifetime as compared with the tunneling lifetime. This paper deduces an estimated electron lifetime of 110 ns in In0.14Ga0.86As wells and 25 ns in In0.17Ga0.83As wells, which agree with published results. View full abstract»

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  • Hydrogenated IGZO Thin-Film Transistors Using High-Pressure Hydrogen Annealing

    Page(s): 2537 - 2541
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    Hydrogenation of thin-film indium-gallium-zincoxide (IGZO) is carried out by applying a high-pressure hydrogen annealing (HPHA) process under 5-atm pressure at different temperatures of 260°C, 270°C, and 280°C. The HPHA effectively increases the carrier concentration and the Hall mobility up to ~ 1019 cm-3 and ~ 6.4 cm2/Vs, respectively. The HPHA-IGZO films exhibit smoother surfaces as compared with the as-grown films. The HPHA performs at a temperature of 260 °C that greatly enhances the electrical characteristics of IGZO TFTs, leading to a saturation field effect mobility of 7.4 cm2/Vs, a subthreshold slope of 0.37 V/decade, a threshold voltage of 2.2 V, and an ION/IOFF of 2.0×106. View full abstract»

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  • Solution-Processed Logic Gates Based On Nanotube/Polymer Composite

    Page(s): 2542 - 2547
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (433 KB) |  | HTML iconHTML  

    Hysteresis-free logic gates capable of operation at 100 kHz are fabricated basing on local-gate thin-film transistors with their channel featuring solution-processed composite films of single-walled carbon nanotubes (SWCNTs) and poly(9,9-dioctylfluorene-co-bithiophene) (F8T2). Using dip-coating for deposition of composite films, high-density SWCNTs are found to be embedded in an F8T2 layer and thus being kept from the underlying AlOx gate dielectric by a certain distance. The presence of the F8T2 interlayer effectively suppresses hysteresis although it also weakens the gate electrostatic control. The fabricated transistors are characterized by nil hysteresis, high carrier mobility, large ON/OFF current ratio, low operation voltage, small subthreshold swing, and remarkable scalability. These properties are crucial for the realization of the well-performing logic circuits. View full abstract»

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  • Measuring the Thermal Resistance in Light Emitting Diodes Using a Transient Thermal Analysis Technique

    Page(s): 2548 - 2555
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (843 KB) |  | HTML iconHTML  

    We explore a modified thermal resistance analysis by induced transient method applied to light emitting diodes (LEDs) to discretize the junction-to-package thermal resistance. The temperature response of LED and package configuration is evaluated for discrete contributions from identifiable spatial domains in the multilayered device and package structure to obtain their thermal resistances and thermal capacitances using a Laplace transform-based method. The technique successfully extracts the junction-to-package thermal parameters of a variety of LED package configurations from the experimental temperature transient measurements of the LED junction and provides a straightforward method by which these parameters can be obtained. View full abstract»

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  • Modification of a Driving Waveform in an AC Plasma Display Panel With Sc-doped MgO Protecting Layer

    Page(s): 2556 - 2560
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1261 KB) |  | HTML iconHTML  

    In this paper, the change in addressing characteristics of an AC Plasma display panel with Sc-doped MgO protecting layer are investigated with the variation of operation temperature, addressing waiting time, and scan voltage level during address period using ramp addressing pulse. The addressing voltage in the cell which is addressed long time after reset period is higher but showed narrower distribution of addressing discharge event than other cell. This phenomenon is assumed as a result of the increased wall voltage loss and the enhancement of priming effect due to the electron emission from the Sc-doped MgO protecting layer. A modification of driving waveform for scan electrode is suggested to minimize the wall voltage loss and utilize the priming effect due to the electron emission from the protecting layer, and the improvement in addressing characteristics is presented. View full abstract»

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  • Low-Power CMOS Image Sensor Based on Column-Parallel Single-Slope/SAR Quantization Scheme

    Page(s): 2561 - 2566
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2249 KB) |  | HTML iconHTML  

    This paper presents a low-power megapixel image sensor design. In this paper, a column-parallel 11-bit two-step quantization scheme is proposed. It consists of a 3-bit single-slope analog-to-digital converter (ADC) and an 8-bit successive approximation register (SAR) ADC. The power consumption of the column-parallel circuitry is significantly reduced when compared with the traditional single-slope ADC and other low-power ADC schemes because smaller SAR ADC reference voltages are selected after quantizing the first three most significant bits. In addition, as only an 8-bit SAR ADC is required in the proposed quantization scheme, the capacitor array matching can be greatly relaxed compared with an 11-bit SAR ADC thus, resulting in noncalibration feature. A 1200 × 800 pixel resolution color CMOS image sensor (CIS) is fabricated using TSMC 0.18-μm CIS technology. The measurement result shows that the total power consumption figure-of-merit of this research is only 1.33 mW/megapixel/frame under 3.3-V (analog)/1.8-V (digital) power supply. View full abstract»

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  • Characterization of the First FBK High-Density Cell Silicon Photomultiplier Technology

    Page(s): 2567 - 2573
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (595 KB) |  | HTML iconHTML  

    In this paper, we present the results of the characterization of the first high-density (HD) cell silicon photomultipliers produced at FBK. The most advanced prototype manufactured with this technology has a cell size of 15 × 15 μm2 featuring a nominal fill factor of 48%. To reach this high area coverage, we developed a new border structure to confine the high electric-field region of each single-photon avalanche diode. The measured detection efficiency approaches 30% in the green part of the light spectrum and it is above 20% from 400 to 650 nm. At these efficiency values, the correlated noise is very low, giving an excess charge factor below 1.1. We coupled a 2 × 2 × 10- mm3 LYSO scintillator crystal to a 2.2 × 2.2- mm2 silicon photomultiplier, obtaining very promising results for PET application: energy resolution of less than 11% full-width at half maximum (FWHM) with negligible loss of linearity and coincidence resolving time of 200-ps FWHM at 20°C. View full abstract»

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  • Investigation of Photo-Induced Hysteresis and Off-Current in Amorphous In-Ga-Zn Oxide Thin-Film Transistors Under UV Light Irradiation

    Page(s): 2574 - 2579
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (913 KB) |  | HTML iconHTML  

    We investigated the hysteresis and off-current (Ioff) of amorphous In-Ga-Zn oxide thin-film transistors illuminated by 400 nm light at various intensities. Both hysteresis and Ioff are induced by the ionized oxygen vacancy (Vo2+) that forms at the interface between the gate insulator and active layer. In our measurements, Ioff was much less than the estimated photocurrent. Ioff showed a rapid nonlinear increase with light intensity, while the photocurrent of a conventional crystalline semiconductor is expected to show a linear relationship. Furthermore, a numerical analysis suggested that the response time of Vo2+ should be considered when analyzing the hysteresis of these devices. View full abstract»

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  • Characteristics of the GaAs Photoconductive Semiconductor Switch Operated in Linear-Alike Mode

    Page(s): 2580 - 2585
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (954 KB) |  | HTML iconHTML  

    The photoconductive semiconductor switches (PCSSs) have two operating modes, i.e., linear mode and nonlinear mode (also “lock-on” mode). The low bias voltage and high trigger energy are needed when the switch is operated in a linear mode, but the high bias voltage and low trigger energy are needed when the switch is operated in a nonlinear mode. When the GaAs PCSS is triggered under the condition of the low bias voltage and low trigger energy, the on-state characteristic of the switch is similar to that in the linear mode but different from the nonlinear mode. We refer to this mode as “linear-alike mode.” In this paper, a research on the GaAs PCSS triggered by a laser diode in different low bias voltages is reported. The performance of linear-alike mode is analyzed and an equation used to calculate the on-state current is put forward, on the basis of which a method to measure the ionization rate is presented. View full abstract»

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Aims & Scope

IEEE Transactions on Electron Devices publishes original and significant contributions relating to the theory, modeling, design, performance and reliability of electron and ion integrated circuit devices and interconnects.

 

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Meet Our Editors

Editor-in-Chief
John D. Cressler
School of Electrical and Computer Engineering
Georgia Institute of Technology