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Computers & Digital Techniques, IET

Issue 3 • Date May 2013

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Displaying Results 1 - 4 of 4
  • Contention-aware selection strategy for application-specific network-on-chip

    Publication Year: 2013 , Page(s): 105 - 114
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (1256 KB)  

    Network-on-chip (NoC) performance largely depends on the underlying deadlock-free and efficient routing algorithm. The effectiveness of any adaptive routing algorithm strongly depends on the underlying selection strategy. When the routing function returns a set of admissible output channels with cardinality greater than one, a selection function is used to select the output channel to which the packet will be forwarded. In this study a novel selection strategy, LATEX, is proposed that can be used with any adaptive routing algorithm for specified applications. The objective of the proposed selection strategy is to efficiently balance traffic load and reach better performance results. Performance evaluation is carried out by using a flit-accurate simulator under two real traffic scenarios. Result experiments show that the proposed selection strategy applied to several routing algorithms significantly improves average delay, max delay and power consumption. View full abstract»

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  • Interconnection system for the spiNNaker biologically inspired multi-computer

    Publication Year: 2013 , Page(s): 115 - 121
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (479 KB)  

    SpiNNaker is a large-scale multi-core computing engine designed to model heavily distributed fine-grain problems. The machine is constructed hierarchically: 1 monitor and 16 worker processors form a single node of a toroidal compute `surface'. The six high-speed bi-directional links of each node are used for triangular edge connections that provide alternative routes around problematic links. The system itself is scalable from one node up to 216 resulting in a maximum of 220 worker processors. SpiNNaker is an isotropic homogeneous network of processors that deliberately includes no central overseer. A consequence of this isotropy is an absence of perimeter and hence no natural position for peripheral I/O connections. This study describes the practical techniques and details employed in two components of the system: (a) SpiNNlink is the proposed board-to-board interconnection system that multiplexes 48 separate 250 Mbps SpiNNaker links through six off-board connections without compromising the overall system bisection bandwidth, forms an isotropic meta-network on top of SpiNNaker without requiring any cooperation from system software, and remains transparent to the SpiNNaker network; and (b) SpiNNterceptor is the proposed peripheral I/O subsystem developed as a layer on top of SpiNNlink that provides over 18 Gbps of minimally disruptive communication between SpiNNaker applications and externally connected equipment. View full abstract»

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  • Customised soft processor design: a compromise between architecture description languages and parameterisable processors

    Publication Year: 2013 , Page(s): 122 - 131
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (616 KB)  

    Processor customisation is an effective technique to enhance performance across an application domain. In this study, the authors present a new customised soft processor development environment called polytechnique customised soft processor (PolyCuSP), which bridges the gap between architecture description languages (ADLs) and extensible soft processors. The main objective of this environment is to facilitate rapid design space exploration while preserving a wide range of customisation flexibility. For this purpose, PolyCuSP offers full flexibility in instruction-set description, while limiting the datapath customisation to a predefined set of tunable microarchitectural parameters. The environment avoids extensive datapath description that is unnecessary for usual microarchitectural customisation techniques in order to simplify the development process. A new XML-based description format is introduced for instruction-set modelling. Experimental results evaluate and compare the design and customisation complexities offered by PolyCuSP with competitive approaches. Results demonstrate the efficiency of applying customisation techniques in the proposed environment. For the Sobel edge detection algorithm, the results show that microarchitectural tuning and instruction-set architecture customisation improve the performance-per-cost ratio by an average of 44 and 27%, respectively. Furthermore, in a case study of a tone-mapping algorithm, PolyCuSP achieves an average improvement of 38% in performance-per-cost ratio over an ADL-based design applying the same customisations. View full abstract»

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  • Single-configuration fault detection in applicationdependent testing of field programmable gate array interconnects

    Publication Year: 2013 , Page(s): 132 - 141
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (318 KB)  

    This study presents a new method for application testing of field programmable gate array (FPGA) interconnects at run time. This method utilises new features related to the function for the programming of the look up tables (LUTs), the utilisation (by logic activation/deactivation) of the nets in a interconnect configuration as well as the primary (unused) input/outputs (IOs) of the FPGAs. A new LUT programming function is introduced; the proposed method retains the original interconnect configuration and modifies the function of the LUTs using the so-called 1-bit sum function (1-BSF); the 1-BSF detects all possible stuck-at and bridging faults (of all cardinalities) by utilising the all zeros' vector and a walking-1 test set. As validated by simulation for benchmark circuits (implemented on the Xilinx Virtex4 and Virtex5), the proposed method (with a polynomial time complexity) results in a single test configuration with 100% coverage. These results also show that the proposed method requires a larger number of test vectors and an availability of unused IOs. View full abstract»

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Aims & Scope

IET Computers & Digital Techniques publishes technical papers describing recent research and development work in all aspects of digital system-on-chip design and test of electronic and embedded systems.

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