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Very Large Scale Integration (VLSI) Systems, IEEE Transactions on

Issue 7 • Date July 2013

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Displaying Results 1 - 25 of 28
  • Table of contents

    Publication Year: 2013 , Page(s): C1 - C4
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  • IEEE Transactions on Very Large Scale Integration (VLSI) Systems publication information

    Publication Year: 2013 , Page(s): C2
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  • Nonvolatile Nanopipelining Logic Using Multiferroic Single-Domain Nanomagnets

    Publication Year: 2013 , Page(s): 1181 - 1188
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (1073 KB) |  | HTML iconHTML  

    Multiferroic single-domain nanomagnetics is a promising emerging nanotechnology poised to usher in ultralow energy nanomagnetic nonvolatile logic circuits in numerous medical applications, such as implants and prosthesis, where battery longevity is paramount. This paper evaluates the fundamental mode of signal propagation over ferromagnetically and antiferromagnetically coupled wires and interacti... View full abstract»

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  • Impact of III–V and Ge Devices on Circuit Performance

    Publication Year: 2013 , Page(s): 1189 - 1200
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (939 KB) |  | HTML iconHTML  

    III-V and germanium (Ge) field-effect transistors (FETs) have been studied as candidates for post Si CMOS. In this paper, the performance of various digital blocks and static random access memory (SRAM) with different combinations of Si, III-V and Ge devices are studied. SPICE-compatible III-V n-channel FET (nFET) and Ge p-channel FET (pFET) models are developed for the analysis. The delay and ene... View full abstract»

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  • Design of Testable Reversible Sequential Circuits

    Publication Year: 2013 , Page(s): 1201 - 1209
    Cited by:  Papers (7)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (847 KB) |  | HTML iconHTML  

    In this paper, we propose the design of two vectors testable sequential circuits based on conservative logic gates. The proposed sequential circuits based on conservative logic gates outperform the sequential circuits implemented in classical gates in terms of testability. Any sequential circuit based on conservative logic gates can be tested for classical unidirectional stuck-at faults using only... View full abstract»

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  • Test Path Selection for Capturing Delay Failures Under Statistical Timing Model

    Publication Year: 2013 , Page(s): 1210 - 1219
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (432 KB) |  | HTML iconHTML  

    This paper proposes a test path selection approach for capturing delay failures caused by the accumulated distributed small delay variations. First, a universal path candidate set U, which contains testable long paths, is generated. Second, given a path number threshold, path selection from U is performed with the objective of maximizing the capability to capture potential delay fail... View full abstract»

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  • Automatic Test Program Generation Using Executing-Trace-Based Constraint Extraction for Embedded Processors

    Publication Year: 2013 , Page(s): 1220 - 1233
    Cited by:  Papers (3)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (926 KB) |  | HTML iconHTML  

    Software-based self-testing (SBST) has been a promising method for processor testing, but the complexity of the state-of-art processors still poses great challenges for SBST. This paper utilizes the executing trace collected during executing training programs on the processor under test to simplify mappings and functional constraint extraction for ports of inner components, which facilitate struct... View full abstract»

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  • Piecewise Linear Modulation Technique for Spread Spectrum Clock Generation

    Publication Year: 2013 , Page(s): 1234 - 1245
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (1949 KB) |  | HTML iconHTML  

    We propose a novel modulation profile for a spread spectrum clock generator (SSCG). The proposed piecewise linear (PWL) modulation profile significantly reduces electromagnetic interference with a simple implementation. Two SSCGs with two- and three-slope-PWL modulation profiles are used. Both SSCGs consist of the proposed spread spectrum control profile generator and a phase-locked loop that incl... View full abstract»

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  • Efficient Vector Graphics Rasterization Accelerator Using Optimized Scan-Line Buffer

    Publication Year: 2013 , Page(s): 1246 - 1259
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (3459 KB) |  | HTML iconHTML  

    This paper presents a small and fast VLSI architecture of a vector graphics rasterization accelerator. To decide the filling regions of a graphics object, a large on-chip scan-line buffer (SB) is very often used and frequently accessed to derive the pixel's winding count. This paper, first, proposes a special 2-bit coding scheme for buffer entry along with active-edge-table rescan to record the in... View full abstract»

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  • Write Current Self-Configuration Scheme for MRAM Yield Improvement

    Publication Year: 2013 , Page(s): 1260 - 1270
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (945 KB) |  | HTML iconHTML  

    Magnetic random access memory (MRAM) is an emerging nonvolatile memory, which is widely studied for its high speed, high density, small cell size, and almost unlimited endurance. However, for deep-submicrometer process technologies, significant variation in the MRAM cells' operating condition results in write failures in cells and reduces the production yield. Memory designers have to characterize... View full abstract»

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  • Task Allocation on Nonvolatile-Memory-Based Hybrid Main Memory

    Publication Year: 2013 , Page(s): 1271 - 1284
    Cited by:  Papers (3)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (935 KB) |  | HTML iconHTML  

    In this paper, we consider the task allocation problem on a hybrid main memory composed of nonvolatile memory (NVM) and dynamic random access memory (DRAM). Compared to the conventional memory technology DRAM, the emerging NVM has excellent energy performance since it consumes orders of magnitude less leakage power. On the other hand, most types of NVMs come with the disadvantages of much shorter ... View full abstract»

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  • BilRC: An Execution Triggered Coarse Grained Reconfigurable Architecture

    Publication Year: 2013 , Page(s): 1285 - 1298
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (1245 KB) |  | HTML iconHTML  

    We present Bilkent reconfigurable computer (BilRC), a new coarse-grained reconfigurable architecture (CGRA) employing an execution-triggering mechanism. A control data flow graph language is presented for mapping the applications to BilRC. The flexibility of the architecture and the computation model are validated by mapping several real-world applications. The same language is also used to map ap... View full abstract»

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  • Fault-Tolerant Embedded-Memory Strategy for Baseband Signal Processing Systems

    Publication Year: 2013 , Page(s): 1299 - 1307
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (1576 KB) |  | HTML iconHTML  

    The growing density of integration and the increasing percentage of system-on-chip area occupied by embedded memories has led to an increase in the expected number of memory faults. The soft memory repair strategy proposed in this paper employs existing forward error correction at the system level and mitigates the impact of memory faults through permutation of high-sensitivity regions. The effect... View full abstract»

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  • Collaborative Multiobjective Global Routing

    Publication Year: 2013 , Page(s): 1308 - 1321
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (831 KB) |  | HTML iconHTML  

    This paper presents a collaborative procedure for multiobjective global routing. Our procedure takes multiple global routing solutions, which are generated independently (e.g., by one router that runs in different modes concurrently or by different routers running in parallel), as input. It then performs multiobjective optimization based on Pareto algebra and quickly generates multiple global rout... View full abstract»

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  • Energy-Efficient Digital Signal Processing via Voltage-Overscaling-Based Residue Number System

    Publication Year: 2013 , Page(s): 1322 - 1332
    Cited by:  Papers (4)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (691 KB) |  | HTML iconHTML  

    In this paper, we apply the voltage overscaling (VOS) technique to the residue-number-system (RNS)-based digital signal processing system for achieving high energy efficiency. To mitigate the soft errors caused by VOS, we propose a new method, called joint RNS-RPR (JRR), which is the combination of RNS and the reduced precision redundancy (RPR) technique. The JRR technology inherits the properties... View full abstract»

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  • IEEE 1500 Compatible Multilevel Maximal Concurrent Interconnect Test

    Publication Year: 2013 , Page(s): 1333 - 1337
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (334 KB) |  | HTML iconHTML  

    On-chip interconnect structures become much more complicated and dominate system performance in multicore system-on-chips. Oscillation ring (OR) test is an efficient test method for most types of faults in the interconnect structures, and previous studies show that both 100% fault coverage and the optimum diagnosis resolution for various fault models are achievable. The cost of OR test is decided ... View full abstract»

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  • Block-Circulant RS-LDPC Code: Code Construction and Efficient Decoder Design

    Publication Year: 2013 , Page(s): 1337 - 1341
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (839 KB) |  | HTML iconHTML  

    This brief presents a method for constructing block-circulant (BC) Reed-Solomon-based low-density parity-check (RS-LDPC) codes and an efficient decoder design. The proposed construction method results in a BC form of a parity-check matrix from a random parity-check matrix for RS-LDPC codes. A decoder architecture and switch network for BC-RS-LDPC code are then developed based on the new BC parity-... View full abstract»

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  • Enhanced Secure Architecture for Joint Action Test Group Systems

    Publication Year: 2013 , Page(s): 1342 - 1345
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (384 KB) |  | HTML iconHTML  

    The implementation of debugging tools through joint action test group (JTAG) has led to increased exposure of intellectual property through the interface. In this brief, the first hardware implementation of a flexible multilevel access security system for the JTAG interface is detailed. The proposed method is user-privilege aware, which allows for higher granularity for controlling user access of ... View full abstract»

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  • Throughput/Resource-Efficient Reconfigurable Processor for Multimedia Applications

    Publication Year: 2013 , Page(s): 1346 - 1350
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (891 KB) |  | HTML iconHTML  

    This brief presents the implementation and evaluation of an 8-bit adaptable processor core to be part of the power-throughput-area efficient multimedia oriented reconfigurable architecture reconfigurable array. The design of the processor core was custom implemented in IBM's 90 nm CMOS technology and occupies 0.115 mm2 silicon area with approximately 70% area utilized by core circuits. ... View full abstract»

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  • Error Rate-Based Wear-Leveling for nand Flash Memory at Highly Scaled Technology Nodes

    Publication Year: 2013 , Page(s): 1350 - 1354
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (469 KB) |  | HTML iconHTML  

    This brief presents a NAND Flash memory wear-leveling algorithm that explicitly uses memory raw bit error rate (BER) as the optimization target. Although NAND Flash memory wear-leveling has been well studied, all the existing algorithms aim to equalize the number of programming/erase cycles among all the memory blocks. Unfortunately, such a conventional design practice becomes increasingly subopti... View full abstract»

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  • Reduced Power Transition Fault Test Sets for Circuits With Independent Scan Chain Modes

    Publication Year: 2013 , Page(s): 1354 - 1359
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (255 KB) |  | HTML iconHTML  

    This brief considers circuits with multiple scan chains where each scan chain can operate in shift, functional, or hold mode independently of the other scan chains. For circuits where the hardware overhead of controlling the scan chains independently is acceptable, this brief describes a procedure whose goal is to generate a test set that achieves the same transition fault coverage as a test set t... View full abstract»

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  • Transition Fault Simulation Considering Broadside Tests as Partially-Functional Broadside Tests

    Publication Year: 2013 , Page(s): 1359 - 1363
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (162 KB) |  | HTML iconHTML  

    The scan-in states of functional broadside tests are reachable states, which are states that the circuit can enter during functional operation. This is used for ensuring functional operation conditions during the functional clock cycles of the tests. For a partially-functional broadside test, the scan-in state has a known Hamming distance to a reachable state. This ensures measurable deviations fr... View full abstract»

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  • Fault Demotion Using Reconfigurable Slack (FaDReS)

    Publication Year: 2013 , Page(s): 1364 - 1368
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (400 KB) |  | HTML iconHTML  

    We propose an active dynamic redundancy-based fault-handling approach exploiting the partial dynamic reconfiguration capability of static random-access memory-based field-programmable gate arrays. Fault detection is accomplished in a uniplex hardware arrangement while an autonomous fault isolation scheme is employed, which neither requires test vectors nor suspends the computational throughput. Th... View full abstract»

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  • ADDLL for Clock-Deskew Buffer in High-Performance SoCs

    Publication Year: 2013 , Page(s): 1368 - 1373
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (865 KB) |  | HTML iconHTML  

    In this brief, we propose an all-digital delay locked loop (ADDLL) for a clock-deskew buffer. A low static phase offset at a high operating frequency is achieved by adopting a high-resolution window phase detector (PD) and a tristate-inverter-based ladder type coarse delay line (CDL). The proposed PD generates a high-resolution detection window that is adaptive to the process-voltage-temperature v... View full abstract»

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  • IEEE Transactions on Very Large Scale Integration (VLSI) Systems information for authors

    Publication Year: 2013 , Page(s): 1374
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    Freely Available from IEEE

Aims & Scope

Design and realization of microelectronic systems using VLSI/ULSI technologies require close collaboration among scientists and engineers in the fields of systems architecture, logic and circuit design, chips and wafer fabrication, packaging, testing, and systems applications. Generation of specifications, design, and verification must be performed at all abstraction levels, including the system, register-transfer, logic, circuit, transistor, and process levels.

To address this critical area through a common forum, the IEEE Transactions on VLSI Systems was founded. The editorial board, consisting of international experts, invites original papers which emphasize the novel system integration aspects of microelectronic systems, including interactions among system design and partitioning, logic and memory design, digital and analog circuit design, layout synthesis, CAD tools, chips and wafer fabrication, testing and packaging, and system level qualification. Thus, the coverage of this Transactions focuses on VLSI/ULSI microelectronic system integration.

Topics of special interest include, but are not strictly limited to, the following: • System Specification, Design and Partitioning, • System-level Test, • Reliable VLSI/ULSI Systems, • High Performance Computing and Communication Systems, • Wafer Scale Integration and Multichip Modules (MCMs), • High-Speed Interconnects in Microelectronic Systems, • VLSI/ULSI Neural Networks and Their Applications, • Adaptive Computing Systems with FPGA components, • Mixed Analog/Digital Systems, • Cost, Performance Tradeoffs of VLSI/ULSI Systems, • Adaptive Computing Using Reconfigurable Components (FPGAs) 

Full Aims & Scope

Meet Our Editors

Editor-in-Chief

Krishnendu Chakrabarty
Department of Electrical Engineering
Duke University
Durham, NC 27708 USA
Krish@duke.edu