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Electron Devices, IEEE Transactions on

Issue 7 • Date July 2013

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  • Table of contents

    Publication Year: 2013 , Page(s): C1 - 2094
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  • IEEE Transactions on Electron Devices publication information

    Publication Year: 2013 , Page(s): C2
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  • What is in a Page Charge?

    Publication Year: 2013 , Page(s): 2095
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  • A Physical and SPICE Mobility Degradation Analysis for NBTI

    Publication Year: 2013 , Page(s): 2096 - 2103
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (876 KB) |  | HTML iconHTML  

    The importance of mobility degradation (Δμeff) due to Negative Bias Temperature Instability (NBTI) stress is studied for precise modeling of p-MOSFET drain current degradation (ΔID). An improvement to the SPICE mobility model is presented to incorporate Δμeff , and the modified model is validated against experimental ΔID and transconductance degradation (Δgm) over time, in the subthreshold to strong inversion region, across different SiON and high-k metal gate (HKMG) devices. To gain further insight into NBTI mobility degradation, the well-known physics-based mobility model consisting of three scattering components is revalidated across different devices. This analysis is beneficial for device and circuit simulations in Technology CAD and SPICE environments, respectively, for different process technologies. View full abstract»

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  • Simulation of High-Efficiency Crystalline Silicon Solar Cells With Homo–Hetero Junctions

    Publication Year: 2013 , Page(s): 2104 - 2110
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1281 KB) |  | HTML iconHTML  

    A novel solar cell structure consisting of both homojunction and heterojunction (homo-hetero junctions), which possesses a potential to realize high photoelectric conversion efficiency, is investigated by the numerical simulation tool AFORS-HET. We demonstrate that the homo-hetero junctions solar cell has a higher fill factor than the solar cell with heterojunction with intrinsic thin layer (HIT), due to the reduced series resistance, which results in a better conversion efficiency, whereas their interfacial density of states (DOS) values are identical. Through a detailed study of the effect of inserting a homojunction, we find that the field-effect passivation can adequately explain the interesting behaviors that the open-circuit voltage increases and the emitter saturation current density declines when increasing the doping concentration in the P-type crystalline silicon layer. In addition, as compared with the HIT solar cell, the homo-hetero junctions solar cell is less sensitive to the DOS due to the field-effect passivation, leading to a comparable open-circuit voltage even if its total interfacial DOS is 10 times higher. View full abstract»

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  • Model Order Reduction for Multiband Quantum Transport Simulations and its Application to p-Type Junctionless Transistors

    Publication Year: 2013 , Page(s): 2111 - 2119
    Cited by:  Papers (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (857 KB) |  | HTML iconHTML  

    An efficient method is developed for multiband simulation of quantum transport in nanowire electronic devices within nonequilibrium Green's function formalism. The efficiency relies on a model order reduction technique, which projects the k · p Hamiltonian into a much smaller subspace constructed by sampling the Bloch modes of each cross-section layer. Several sampling approaches are discussed to obtain a minimum and accurate basis with reduced computational overhead. The technique is verified by calculating the valence bands of silicon nanowires (SiNWs) and by solving I-V curves of p-type SiNW transistors. This enables us to study for the first time the performances of large cross-section p-type junctionless (JL) transistors in the quantum ballistic transport limit. The influences of doping density, transport direction, channel length, and cross-section size are examined. We find that larger doping densities may lead to worse sub-threshold slopes due to the enhanced source-to-drain tunneling. Compared with their counterparts, i.e., classical inversion-mode (IM) transistors, they have better sub-threshold behaviors, but they do not necessarily provide a better ON/OFF ratio except when the channel is short or thin. In addition, unlike IM transistors, [110] and [111] channel directions in JL transistors are very robust against channel thicknes scaling. View full abstract»

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  • Modeling and Design Space of Junctionless Symmetric DG MOSFETs With Long Channel

    Publication Year: 2013 , Page(s): 2120 - 2127
    Cited by:  Papers (6)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1818 KB) |  | HTML iconHTML  

    In this paper, we investigate the technological constrains and design limitations of ultrathin body junctionless double gate MOSFET (JL DG MOSFET). Relationships between the silicon thickness and the doping concentration compatible with design requirements in terms of OFF-state-current and voltages are obtained and validated with TCAD simulations. This set of analytical expressions can be used as a guideline for technology optimization of JL DG MOSFETs. View full abstract»

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  • Quantum Mechanical Performance Predictions of p-n-i-n Versus Pocketed Line Tunnel Field-Effect Transistors

    Publication Year: 2013 , Page(s): 2128 - 2134
    Cited by:  Papers (10)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1038 KB) |  | HTML iconHTML  

    The tunnel field-effect transistor (TFET) is a promising candidate to replace the metal-oxide-semiconductor field-effect transistor in advanced technology nodes, because of its potential to obtain sub-60 mV/dec subthreshold swings. However, it is challenging to reach sufficiently high on-currents in TFETs. Therefore, on-current boosters are actively being researched. In this paper, a p-n-i-n TFET, containing a vertical pocket at the source-channel junction, is studied with quantum mechanical simulations and compared with a line tunneling TFET, containing horizontal pockets in the source region. The comparison is carried out both for all-Si and all-Ge, while an extrapolation is made for smaller bandgap materials. The p-n-i-n TFET is found to perform better than a p-i-n configuration, thanks to the increased electric field at the source-pocket junction. Compared to the p-n-i-n TFET, the line TFET has an even higher on-current and lower subthreshold swing, attributed to the closer proximity of the tunnel junction to the gate. For the all-Ge case, the difference between the two configurations is found to decrease when direct transitions are taken into account semi-classically. View full abstract»

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  • Germanium Multiple-Gate Field-Effect Transistor With In Situ Boron-Doped Raised Source/Drain

    Publication Year: 2013 , Page(s): 2135 - 2141
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1953 KB) |  | HTML iconHTML  

    We report the first demonstration of a p-channel Ω-gate Germanium (Ge) multiple-gate field-effect transistor (MuGFET) on a Germanium-on-Insulator (GeOI) substrate with in situ Boron (B)-doped Ge (Ge:B) raised source/drain (RSD). Detailed process optimization on epitaxial growth of Ge on patterned GeOI samples is discussed. Process integration of Ge:B RSD into Ge MuGFETs using a CMOS compatible process flow is documented. Electrical characteristics of Ge MuGFETs with RSD are reported. View full abstract»

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  • Atomistic Study of the Lattice Thermal Conductivity of Rough Graphene Nanoribbons

    Publication Year: 2013 , Page(s): 2142 - 2147
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    Following our recent study on the electronic properties of rough nanoribbons , in this paper the role of geometrical and roughness parameters on the thermal properties of armchair graphene nanoribbons is studied. Employing a fourth nearest-neighbor force constant model in conjuction with the nonequilibrium Green's function method the effect of line-edge-roughness on the lattice thermal conductivity of rough nanoribbons is investigated. The results show that a reduction of about three orders of magnitude of the thermal conductivity can occur for ribbons narrower than 10 nm. The results indicate that the diffusive thermal conductivity and the effective mean free path are directly proportional to the ribbon's width and the roughness correlation length, but inversely proportional to the roughness amplitude. Based on the numerical results an analytical model for the thermal conductivity of narrow armchair graphene nanoribbons is proposed in this paper. The developed model can be used in the analysis of graphene-based nano transistors and thermoelectric devices, where the appropriate selection of geometrical and roughness parameters are essential for optimizing the thermal properties. View full abstract»

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  • On the Distribution of NBTI Time Constants on a Long, Temperature-Accelerated Time Scale

    Publication Year: 2013 , Page(s): 2148 - 2155
    Cited by:  Papers (5)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (968 KB) |  | HTML iconHTML  

    Recent investigations on individual defects contributing to negative bias temperature instability (NBTI) showed that the emission and capture time constants are thermally activated via an Arrhenius law. We apply this finding to conventional micrometer-sized devices where NBTI is the response of up to millions of defects. We rapidly switch the device temperature using an on-chip heating structure in order to accelerate NBTI stress and recovery and acquire experimental data on an up to 18 decades long time scale. On this extended time scale, we find that the distribution of NBTI defect time constants is log-normal with large mean and variance which follows directly from a normal distribution of energy barriers in Arrhenius law. As such, our work clearly identifies the role of temperature for NBTI and suggests a method for accurate life-time estimations. View full abstract»

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  • Parameterization of Free Carrier Absorption in Highly Doped Silicon for Solar Cells

    Publication Year: 2013 , Page(s): 2156 - 2163
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1177 KB) |  | HTML iconHTML  

    Free carrier absorption (FCA) is a parasitic absorption process in highly doped silicon that might significantly reduce the amount of photons, potentially generating electron-hole pairs. Existing FCA parameterizations are mostly setup by evaluating absorption data in the range λ ≥ 4 μm. If applied in the wavelength range λ = 1.0-2.0 μm, including the relevant range for silicon solar cells, most parameterizations are not appropriate to describe FCA accurately. In this paper, new parameters are presented using optical simulation on the base of experimental reflection data to enhance the quantification of FCA losses in the considered wavelength range. View full abstract»

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  • Compact Zero-Temperature Coefficient Modeling Approach for MOSFETs Based on Unified Regional Modeling of Surface Potential

    Publication Year: 2013 , Page(s): 2164 - 2170
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (734 KB) |  | HTML iconHTML  

    A compact zero-temperature coefficient (ZTC) modeling approach is demonstrated for generic MOSFETs. Instead of manually extracting ZTC points through C-V or I-V data over a range of operating temperatures, the ZTC model marks the cross-over ZTC points by Newton-Raphson solutions to the ZTC voltages based on the compact charge/current models. It calculates the ZTC voltages in the accumulation (Vztc,sa) and depletion (Vztc,ds) regions based on the unified regional modeling of surface potential for the gate capacitance at zero drain bias (Vds=0). It is extended to the ZTC voltage (Vztc,ds) for gate capacitance in the depletion and saturation regions at any Vds, and the ZTC voltage (Vztc) for drain current in the linear and saturation regions at any Vds. The proposed approach can be adopted to create a process window with constant ZTC contours for different process parameters, such as body doping and gate-oxide thickness at any drain biases. The process windows provide useful information in determining the optimum process parameters and operating voltages for circuit design in ruggedized electronics that operate at high-temperature conditions. View full abstract»

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  • Engineering Nanowire n-MOSFETs at L_{g}< 8~{\rm nm}

    Publication Year: 2013 , Page(s): 2171 - 2177
    Cited by:  Papers (4)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1723 KB) |  | HTML iconHTML  

    As metal-oxide-semiconductor field-effect transistors (MOSFETs) channel lengths (Lg) are scaled to lengths shorter than Lg <; 8 nm source-drain tunneling starts to become a major performance limiting factor. In this scenario, a heavier transport mass can be used to limit source-drain (S-D) tunneling. Taking InAs and Si as examples, it is shown that different heavier transport masses can be engineered using strain and crystal-orientation engineering. Full-band extended device atomistic quantum transport simulations are performed for nanowire MOSFETs at Lg <; 8 nm in both ballistic and incoherent scattering regimes. In conclusion, a heavier transport mass can indeed be advantageous in improving ON-state currents in ultrascaled nanowire MOSFETs. View full abstract»

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  • Atomically Flat Low-Resistive Germanide Contacts Formed by Laser Thermal Anneal

    Publication Year: 2013 , Page(s): 2178 - 2185
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1648 KB) |  | HTML iconHTML  

    In this paper, state-of-the-art laser thermal annealing is used to form germanide contacts on n-doped Ge and is systematically compared with results generated by conventional rapid thermal annealing. Surface topography, interface quality, crystal structure, and material stoichiometry are explored for both annealing techniques. For electrical characterization, specific contact resistivity and thermal stability are extracted. It is shown that laser thermal annealing can produce a uniform contact with a remarkably smooth substrate interface with specific contact resistivity two to three orders of magnitude lower than the equivalent rapid thermal annealing case. It is shown that a specific contact resistivity of 2.84 × 10-7 Ω·cm2 is achieved for optimized laser thermal anneal energy density conditions. View full abstract»

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  • Evaluation of Digital Circuit-Level Variability in Inversion-Mode and Junctionless FinFET Technologies

    Publication Year: 2013 , Page(s): 2186 - 2193
    Cited by:  Papers (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2638 KB) |  | HTML iconHTML  

    In this paper, we develop an evaluation framework to assess variability in nanoscale inversion-mode (IM) and junctionless (JL) fin field-effect transistors (FinFETs) due to line edge roughness (LER) and random dopant fluctuation (RDF) for both six transistor (6T) static random access memory (SRAM) design and large-scale digital circuits. From a device-level perspective, JL FinFETs are severely impacted by process variations: up to 40% and 60% fluctuation in threshold voltage is observed from LER RDF. Conversely, results show that variability-induced shifts and broadening of timing and power in large-scale digital circuits are not significant and can be accommodated in the design budget. However, we find that LER has a large impact on static noise margin analysis of 6T SRAMs. Required Vccmin values for SRAMs using JL devices reach up to 2× those implemented in conventional IM technologies. The yield for JL SRAM is completely compromised in the presence of realistic levels of LER and RDF. Fortunately, the impact of variability is somewhat reduced with scaling for JL designs; both LER and RDF induce less variation for the 15-nm node compared with the 32-nm node. The observed reduction in Vccmin with technology scaling suggests that digital circuits implemented with JL FinFETs may eventually offer the same level of operability as those based on IM FinFETs, especially in the presence of circuit-level SRAM robustness optimizations. View full abstract»

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  • State Dynamics and Modeling of Tantalum Oxide Memristors

    Publication Year: 2013 , Page(s): 2194 - 2202
    Cited by:  Papers (5)
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (1428 KB) |  | HTML iconHTML  

    A key requirement for using memristors in circuits is a predictive model for device behavior that can be used in simulations and to guide designs. We analyze one of the most promising materials, tantalum oxide, for high density, low power, and high-speed memory. We perform an ensemble of measurements, including time dynamics across nine decades, to deduce the underlying state equations describing the switching in Pt/TaOx/Ta memristors. A predictive, compact model is found in good agreement with the measured data. The resulting model, compatible with SPICE, is then used to understand trends in terms of switching times and energy consumption, which in turn are important for choosing device operating points and handling interactions with other circuit elements. View full abstract»

    Open Access
  • New Erase Constraint for the Junction-Less Charge-Trap Memory Array in Cylindrical Geometry

    Publication Year: 2013 , Page(s): 2203 - 2208
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2237 KB) |  | HTML iconHTML  

    This paper presents a detailed simulation analysis of the erase performance of junction-less charge-trap memory arrays in the cylindrical geometry, showing that a saturation of the erased threshold voltage occurs as a result of incomplete inversion of the intercell regions when positive charge is stored in the cells. This erase saturation issue is investigated as a function of string and cell parameters, revealing lower erase capabilities for large cell-to-cell separation, small substrate radius, and small equivalent-oxide thickness of the gate stack. These results add new constraints to the design of cylindrical junction-less memory technologies. View full abstract»

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  • InP-DHBT-on-BiCMOS Technology With f_{T}/f_{\max } of 400/350 GHz for Heterogeneous Integrated Millimeter-Wave Sources

    Publication Year: 2013 , Page(s): 2209 - 2216
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2467 KB) |  | HTML iconHTML  

    This paper presents a novel InP-SiGe BiCMOS technology using wafer-scale heterogeneous integration. The vertical stacking of the InP double heterojunction bipolar transistor (DHBT) circuitry directly on top of the BiCMOS wafer enables ultra-broadband interconnects with <; 0.2 dB insertion loss from 0-100 GHz. The 0.8 × 5 μm2 InP DHBTs show fT/fmax of 400/350 GHz with an output power of more than 26 mW at 96 GHz. These are record values for a heterogeneously integrated transistor on silicon. As a circuit example, a 164-GHz signal source is presented. It features a voltage-controlled oscillator in BiCMOS, which drives a doubler-amplifier chain in InP DHBT technology. View full abstract»

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  • Silicon Substrate Engineered High-Voltage High-Temperature GaN-DHFETs

    Publication Year: 2013 , Page(s): 2217 - 2223
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1854 KB) |  | HTML iconHTML  

    Low-cost GaN-on-Si-based transistors are targeted to function at high ambient temperatures. With this perspective, it is aimed to evaluate the high-temperature (HT) capabilities of GaN-on-Si double-heterostructure field-effect transistors. It is highlighted that HT device operation degrades both ON and OFF states that are directly related to the increase in the on-resistance and the decrease in device breakdown voltage; 2-DEG mobility drops with increasing temperature and is responsible for ON-state degradation. Regarding the OFF-state operation, it is observed that at low-voltage operation and with increasing temperature, there is an increase in the OFF-state leakage current because of thermal-assisted electrical conduction across the III-N layers and various interfaces. The main breakdown limiting mechanism at any temperature is, however, buffer leakage along the AlN/Si interface. Because this parasitic conduction, a negative temperature coefficient of breakdown voltage of approximately -1 V/°C is observed. For devices after Si removal, the leakage across the AlN/Si interface is interrupted and therefore HT OFF-state characteristics show high potential to be used at high operating voltage. A breakdown voltage as high as ~1800V is observed after Si removal compared with ~500 V with Si at 150°C. View full abstract»

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  • Electrothermal Simulation and Thermal Performance Study of GaN Vertical and Lateral Power Transistors

    Publication Year: 2013 , Page(s): 2224 - 2230
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1267 KB) |  | HTML iconHTML  

    In this paper, we present self-consistent electrothermal simulations of single-finger and multifinger GaN vertical metal-oxide-semiconductor field-effect transistors (MOSFETs) and lateral AlGaN/GaN high-electron-mobility transistors (HEMTs) and compare their thermal performance. The models are first validated by comparison with experimental dc characteristics, and then used to study the maximum achievable power density of the device without the peak temperature exceeding a safe operation limit of 150°C (P150°C). It is found that the vertical MOSFETs have the potential to achieve a higher P150°C than the lateral HEMTs, especially for higher breakdown voltages and higher scaling level designs. View full abstract»

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  • Investigations of AlGaN/AlN/GaN MOS-HEMTs on Si Substrate by Ozone Water Oxidation Method

    Publication Year: 2013 , Page(s): 2231 - 2237
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1470 KB) |  | HTML iconHTML  

    Al0.3Ga0.7N/AlN/GaN metal-oxide-semiconductor high electron mobility transistors (HEMTs) grown on Si substrates by using ozone water oxidation method are investigated. Superior improvements of 52.2% in two-terminal gate-drain breakdown voltage (BVGD), 30.3% in drain-source current density (IDS) at VGS = 0 V (IDSS0), 43.6% in maximum IDS (IDS,max), 34.7% in maximum extrinsic transconductance (gm,max), and 52.7%/34.3% in unity-gain cutoff/maximum oscillation frequency (fT/fmax) are achieved as compared with a reference Schottky-gated HEMT. Thermal stability is studied by conducting temperature-dependent characterizations of devices at ambient temperatures of 300-550 K. Time-dependent electrical reliability analyses for the devices stressed in off-state (VGS = -20 V and VDS = 0 V) for 0-60 h and on-state (VGS = 2 V and VDS = 20 V) for 0-20 h are also made to physically investigate the dominant degradation mechanisms. Excellent reliability and thermal stability at 300-550 K are achieved by the present design. View full abstract»

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  • Electrical Characterization of GaP-Silicon Interface for Memory and Transistor Applications

    Publication Year: 2013 , Page(s): 2238 - 2245
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1945 KB) |  | HTML iconHTML  

    Process conditions of gallium phosphide (GaP) metal-organic chemical vapor deposition growth on silicon (Si) are optimized by material characterization. Thorough investigation of GaP-Si interface at this optimized growth condition is carried out by electrical characterization with the perspective of applying this heterostructure system for improving the performance of logic transistors and retention time of capacitorless single-transistor dynamic RAM (1T-DRAM). Fabricated GaP-Si heterojunction diodes exhibit an ON-OFF ratio of 108 with similar reverse current as the ideal device simulation results signify immunity to the existing antiphase domains. Finally, MOSFET devices with GaP source-drain having subthreshold swing of 70 mV/dec and an ON-OFF ratio of 105 are demonstrated. View full abstract»

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  • Nonparabolic Multivalley Quantum Correction Model for InGaAs Double-Gate Structures

    Publication Year: 2013 , Page(s): 2246 - 2250
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (529 KB) |  | HTML iconHTML  

    An extension of the modified local density approximation (MLDA) to account for quantum confinement effects in narrow-band multivalley semiconductors is presented. The original MLDA model is also extended to account for confinement in double-gate and fin-shaped FET devices. The extended model is validated against self-consistent Poisson-Schrödinger results for various double-gate metal-oxide-semiconductor structures with InGaAs as the semiconductor material. View full abstract»

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  • High- \kappa ~{\rm Eu}_{2}{\rm O}_{3} and {\rm Y}_{2}{\rm O}_{3} Poly-Si Thin-Film Transistor Nonvolatile Memory Devices

    Publication Year: 2013 , Page(s): 2251 - 2255
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (994 KB) |  | HTML iconHTML  

    In this paper, we have successfully fabricated low-temperature polycrystalline silicon thin-film transistor (LTPS-TFT) nonvolatile memory devices employing high-κ Eu2O3 and Y2O3 films as the charge trapping layer. The LTPS-TFT memory device uses band-to-band tunneling-induced hot hole injection and gate Fowler-Nordheim injection as the program and erase methods, respectively. Compared with the Y2O3 film, the LTPS-TFT memory device using an Eu2O3 charge-trapping layer exhibited a lower subthreshold swing and a larger memory window, a smaller charge loss, and a better endurance performance, presumably because of the higher charge-trapping efficiency of the Eu2O3 film. View full abstract»

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Aims & Scope

IEEE Transactions on Electron Devices publishes original and significant contributions relating to the theory, modeling, design, performance and reliability of electron and ion integrated circuit devices and interconnects.

 

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Meet Our Editors

Acting Editor-in-Chief

Dr. Paul K.-L. Yu

Dept. ECE
University of California San Diego