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IEEE Transactions on Computers

Issue 10 • Oct 1993

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Displaying Results 1 - 15 of 15
  • Testing of fault-tolerant hardware through partial control of inputs

    Publication Year: 1993, Page(s):1267 - 1271
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (488 KB)

    The problem of testing fault-tolerant redundant digital systems is investigated. To test redundant systems through normal voter outputs, independent control of the output of each replicated unit is required. In the past it was assumed that independent control of the output of a replicated unit requires independent control of all of its inputs. The authors show that partial control of inputs is act... View full abstract»

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  • A quantitative evaluation of cache types for high-performance computer systems

    Publication Year: 1993, Page(s):1154 - 1162
    Cited by:  Papers (18)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (760 KB)

    Parallel accesses to the table lookaside buffer (TLB) and cache array are crucial for high-performance computer systems, and the choice of cache types is one of the most important factors affecting cache performance. The authors classify caches according to both index and tag. Since both index and tag could be either virtual (V) or real (R), their classification results in four combinations or cac... View full abstract»

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  • Bounds on the performance of message routing heuristics

    Publication Year: 1993, Page(s):1253 - 1256
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (412 KB)

    Let S be a set of messages to be routed on an N×N omega network. In addition, suppose that S contains communication conflicts. One strategy to deal with such conflicts is to partition S into some number of subsets, called rounds, such that each subset is conflict-free. The messages are then routed through the network by successively routing the messages in each subset. The minimum round part... View full abstract»

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  • Fault-tolerant design strategies for high reliability and safety

    Publication Year: 1993, Page(s):1195 - 1206
    Cited by:  Papers (17)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1000 KB)

    Several fundamental results related to reliability and safety are analyzed. Modular redundant systems consisting of multiple identical modules and an arbiter are considered. It is shown that for a given level of redundancy, a large number of implementation alternatives exist with varying degree of reliability and safety. Strategies are formulated that achieve a maximal combination of reliability a... View full abstract»

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  • Design of efficient error-correcting balanced codes

    Publication Year: 1993, Page(s):1261 - 1266
    Cited by:  Papers (10)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (516 KB)

    New constructions of t-error correcting balanced codes, for 1⩽t⩽4, are presented. In a balanced code, all the words have an equal number of 1's and 0's. In many cases, the information rates of the new codes are better than the existing codes given in the literature. The proposed codes also have efficient encoding and decoding algorithms View full abstract»

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  • A Boolean neural network approach for the traveling salesman problem

    Publication Year: 1993, Page(s):1271 - 1278
    Cited by:  Papers (14)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (684 KB)

    It is shown that the Boolean-neural network can be used to solve NP-complete problems. The problem under consideration is the traveling salesman problem. The Boolean neural network has been modified to include the iterative procedure for solving combinatorial optimization problems. An architecture that utilizes this modified Boolean neural network (MBNN) is proposed for solving this problem. The s... View full abstract»

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  • A reduced-area scheme for carry-select adders

    Publication Year: 1993, Page(s):1163 - 1170
    Cited by:  Papers (125)  |  Patents (10)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (760 KB)

    The carry-select or conditional-sum adders require carry-chain evaluations for each block for both the values of block-carry-in, 0 and 1. The author introduces a scheme to generate carry bits with block-carry-in 1 from the carries of a block with block-carry-in 0. This scheme is then applied to carry-select and parallel-prefix adders to derive a more area-efficient implementation for both the case... View full abstract»

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  • Assessing reliability of multistage interconnection networks

    Publication Year: 1993, Page(s):1207 - 1221
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1476 KB)

    Efficient methods for determining the lower and upper bounds on the probabilities of source-to-terminal communication in a multistage interconnection network are developed. A novel lower bounding strategy (shifting) and a novel upper bounding strategy (renormalization) are presented; both can be computed in polynomial time. These strategies can be combined with existing methods based on coherence,... View full abstract»

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  • A modified Massey-Omura parallel multiplier for a class of finite fields

    Publication Year: 1993, Page(s):1278 - 1280
    Cited by:  Papers (75)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (248 KB)

    A Massey-Omura parallel multiplier of finite fields GF(2m ) contains m identical blocks whose inputs are cyclically shifted versions of one another. It is shown that for fields GF(2m) generated by irreducible all one polynomials, a portion of the block is independent of the input cyclic shift; hence, the multiplier contains redundancy. By removing the redundancy, a modified p... View full abstract»

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  • A parallel computational model for integrated speech and natural language understanding

    Publication Year: 1993, Page(s):1171 - 1183
    Cited by:  Papers (3)  |  Patents (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1128 KB)

    Presents a parallel approach for integrating speech and natural language understanding. The method emphasizes a hierarchically-structured knowledge base and memory-based parsing techniques. Processing is carried out by passing multiple markers in parallel through the knowledge base. Speech specific problems such as insertion, deletion, substitution, and word boundary detection have been analyzed a... View full abstract»

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  • Approximation, dimension reduction, and nonconvex optimization using linear superpositions of Gaussians

    Publication Year: 1993, Page(s):1222 - 1233
    Cited by:  Papers (15)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1040 KB)

    This paper concerns neural network approaches to function approximation and optimization using linear superposition of Gaussians (or what are popularly known as radial basis function (RBF) networks). The problem of function approximation is one of estimating an underlying function f, given samples of the form {(yi, xi); i=1,2,···,n; with yi=f(x... View full abstract»

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  • The completion time of programs on processors subject to failure and repair

    Publication Year: 1993, Page(s):1184 - 1194
    Cited by:  Papers (17)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (940 KB)

    The authors describe a technique for computing the distribution of the completion time of a program on a server subject to failure and repair. Several realistic aspects of the system are included in the model. The server behavior is modeled by a semi-Markov process in order to accommodate nonexponential repair-time distributions. More importantly, the effect on the job completion time of the work ... View full abstract»

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  • Parallel high-radix nonrestoring division

    Publication Year: 1993, Page(s):1234 - 1246
    Cited by:  Papers (4)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1084 KB)

    An algorithm for high-radix nonrestoring division is proposed which combines a cost-efficient quotient estimation technique with collapsing of the division into one operation each iteration. The quotient estimation technique is a direct combinatorial algorithm which allows a more generalized partial remainder than similar studies. In addition, the successor partial remainder is calculated directly... View full abstract»

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  • Creating disjoint paths in Gamma interconnection networks

    Publication Year: 1993, Page(s):1247 - 1252
    Cited by:  Papers (4)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (596 KB)

    The Gamma interconnection network (GIN) is composed of 3×3 basic building blocks, with interconnecting patterns between stages following the plus-minus-2i functions. The authors consider modifications to the GIN by altering the interconnecting patterns between stages so as to achieve high terminal reliability between any source-destination pair, resulting in the reliable GIN (REGI... View full abstract»

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  • Borrow: a fault-tolerance scheme for wavefront array processors

    Publication Year: 1993, Page(s):1257 - 1261
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (448 KB)

    A hardware fault-tolerance mechanism for wavefront array processors is proposed and evaluated. A faulty processing element borrows a working one to reperform the computations and achieve reliable results. The performance level is a stronger function of the fault pattern rather than the actual number of faults. The scheme adopts simple localized or step-wise localized control for its implementation View full abstract»

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Aims & Scope

The IEEE Transactions on Computers is a monthly publication with a wide distribution to researchers, developers, technical managers, and educators in the computer field.

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Meet Our Editors

Editor-in-Chief
Paolo Montuschi
Politecnico di Torino
Dipartimento di Automatica e Informatica
Corso Duca degli Abruzzi 24 
10129 Torino - Italy
e-mail: pmo@computer.org