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IEEE Design & Test

Issue 2 • Date April 2013

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Displaying Results 1 - 25 of 26
  • [Front cover]

    Publication Year: 2013, Page(s): C1
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  • While the world benefi ts from what's new, ieee can focus you on what's next [advertisement]

    Publication Year: 2013, Page(s): C2
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  • [Masthead]

    Publication Year: 2013, Page(s): 1
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  • Table of contents

    Publication Year: 2013, Page(s): 2
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  • Departments [Table of Contents]

    Publication Year: 2013, Page(s): 3
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  • A look at trusted SoC with untrusted components

    Publication Year: 2013, Page(s): 4
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  • Guest Editors' Introduction: Trusted System-on-Chip with Untrusted Components

    Publication Year: 2013, Page(s):5 - 7
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  • Practical, Lightweight Secure Inclusion of Third-Party Intellectual Property

    Publication Year: 2013, Page(s):8 - 16
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (605 KB) | HTML iconHTML

    The security of computing systems relies on trust in hardware. This trust can no longer be assumed due to vulnerabilities in hardware designs. Security methodologies have been proposed for mitigating these threats, offering a variety of security guarantees and wide variance in terms of design-time and runtime costs. From an engineering standpoint it is not clear which of the plethora of solutions ... View full abstract»

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  • HELP: A Hardware-Embedded Delay PUF

    Publication Year: 2013, Page(s):17 - 25
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (811 KB) | HTML iconHTML

    Physical Unclonable Functions enable a secure alternative method to traditional key storage and authentication schemes. This paper presents a novel PUF design that utilizes the existing path delays of a design to generate a random and stable bitstring of desired length with minimal area and performance overhead. View full abstract»

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  • A Clock Sweeping Technique for Detecting Hardware Trojans Impacting Circuits Delay

    Publication Year: 2013, Page(s):26 - 34
    Cited by:  Papers (15)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (633 KB) | HTML iconHTML

    Clock sweeping can be used to generate signatures for the purpose of detecting hardware Trojans. With the help of simulations and FPGA results, this article demonstrates the effectiveness of their proposed clock-sweeping technique under process variations, even for Trojans as small as a few gates. View full abstract»

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  • Securing Processors Against Insider Attacks: A Circuit-Microarchitecture Co-Design Approach

    Publication Year: 2013, Page(s):35 - 44
    Cited by:  Papers (9)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (780 KB) | HTML iconHTML

    Modification to traditional SoC design flow can enable effective protection against maliciously inserted rogue functionality during design and fabrication. This article presents a joint circuit-architecture-level design approach that helps in preventing or detecting Trojan attacks. View full abstract»

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  • Hardware Trojan Insertion by Direct Modification of FPGA Configuration Bitstream

    Publication Year: 2013, Page(s):45 - 54
    Cited by:  Papers (10)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (836 KB) | HTML iconHTML

    In this work, we have demonstrated the feasibility of hardware Trojan insertion in circuits mapped on FPGAs by direct modification of the FPGA configuration bitstream. The main challenge of this attack proved to be the lack of sufficient information in the public domain about the bitstream format and the internal architecture and configurability of the FPGA. Nevertheless, we were able to show that... View full abstract»

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  • Eliminating Timing Information Flows in a Mix-Trusted System-on-Chip

    Publication Year: 2013, Page(s):55 - 62
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (465 KB) | HTML iconHTML

    Editor's notes: Integration of untrusted third-party IPs into an SoC design is a major challenge in establishing trustworthiness of the entire SoC. This article presents an approach to ensure information flow isolation between trusted and untrusted IP cores. View full abstract»

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  • Call for Tutorial and Survey Articles

    Publication Year: 2013, Page(s):63 - 64
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  • IEEE Semantic Technology

    Publication Year: 2013, Page(s): 65
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  • Creating Structural Patterns for At-Speed Testing: A Case Study

    Publication Year: 2013, Page(s):66 - 76
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1248 KB) | HTML iconHTML

    Speed binning (or testing for functional frequency) often requires at-speed testing with functional patterns. Using structural patterns instead is an interesting alternative with respect to cost and overall coverage of nodes. This study analyzes the efficiency of structural test patterns when testing for frequency. Experiments with both path delay and transition delay patterns are discussed for mu... View full abstract»

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  • Fast-Yet-Accurate Statistical Soft-Error-Rate Analysis Considering Full-Spectrum Charge Collection

    Publication Year: 2013, Page(s):77 - 86
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (448 KB) | HTML iconHTML

    Soft errors are a growing concern in highly scaled CMOS technologies; estimating error rates for a given design remains very challenging. This article presents a fast statistical soft-error-rate analysis approach that is nearly as accurate as computationally complex Monte Carlo SPICE simulation. View full abstract»

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  • Diverse Double Modular Redundancy: A New Direction for Soft-Error Detection and Correction

    Publication Year: 2013, Page(s):87 - 95
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (248 KB) | HTML iconHTML

    By introducing diversity between original and redundant modules, diverse double modular redundancy is a promising solution to mitigate the impact of soft errors. View full abstract»

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  • IEEE Phaser Data

    Publication Year: 2013, Page(s): 96
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  • CEDA Currents

    Publication Year: 2013, Page(s):97 - 98
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  • Discover more. IEEE Educational Activities

    Publication Year: 2013, Page(s): 99
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  • Test Technology TC Newsletter

    Publication Year: 2013, Page(s):100 - 101
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  • IEEE Was Here

    Publication Year: 2013, Page(s): 102
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  • Let's stop trusting software with our sensitive data

    Publication Year: 2013, Page(s):103 - 104
    Cited by:  Papers (1)
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  • IEEE Xplore Digital Library

    Publication Year: 2013, Page(s): C3
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Aims & Scope

IEEE Design & Test offers original works describing the models, methods and tools used to design and test microelectronic systems from devices and circuits to complete systems-on-chip and embedded software. The magazine focuses on current and near-future practice, and includes tutorials, how-to articles, and real-world case studies. The magazine seeks to bring to its readers not only important technology advances but also technology leaders, their perspectives through its columns, interviews and roundtable discussions. Topics include semiconductor IC design, semiconductor intellectual property blocks, design, verification and test technology, design for manufacturing and yield, embedded software and systems, low-power and energy efficient design, electronic design automation tools, practical technology, and standards.  

It was published as IEEE Design & Test of Computers between 1984 and 2012.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief
Joerg Henkel
Chair for Embedded Systems (CES)
Karlsruhe Institute of Technology (KIT)