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Components, Packaging and Manufacturing Technology, IEEE Transactions on

Issue 6 • Date June 2013

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  • [Front cover]

    Page(s): C1
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  • IEEE Transactions on Components, Packaging and Manufacturing Technology publication information

    Page(s): C2
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  • Table of contents

    Page(s): 897 - 898
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  • Platinum Diffusion Barrier Breakdown in a-Si/Au Eutectic Wafer Bonding

    Page(s): 899 - 903
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    Eutectic bonding in semiconductor fabrication requires a large degree of control over the stoichiometry and precision film thickness of the bonding materials. To reduce the migration of the bonding layers, diffusion barriers are typically utilized. Here, we demonstrate that a widely utilized diffusion barrier, Pt, does not prevent migration of Si in Si/Au eutectic bonding. We observe that this barrier breaks down at approximately 375°C, above the Au-Si eutectic temperature (363°C), and encourages consumption of the silicon substrate leading to uncontrolled stoichiometry variations and creation of microvoids. This failure results in reductions of bond strength and hermeticity. As an alternative, silicon dioxide is observed to prevent the silicon diffusion and subsequent substrate loss. View full abstract»

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  • High Temperature Interconnect and Die Attach Technology: Au–Sn SLID Bonding

    Page(s): 904 - 914
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    Au–Sn solid–liquid interdiffusion (SLID) bonding is a novel and promising interconnect and die attach technology for high temperature (HT) applications. In combination with silicon carbide (SiC), Au–Sn SLID has the potential to be a key technology for the next generation of HT electronic devices. However, limited knowledge about Au–Sn SLID bonding for HT applications is a major restriction to fully realizing the HT potential of SiC devices. Two different processing techniques—electroplating of Au/Sn layers and sandwiching of eutectic Au–Sn preform between electroplated Au layers—have been studied in a simplified metallization system. The latter process was further investigated in two different ${rm Cu}/{rm Si}_{3}{rm N}_{4}/{rm Cu}/{rm Nihbox{-}P}/{rm Auhbox{-}Sn}/{rm Ni}/{rm Ni}_{2}{rm Si}/{rm SiC}$ systems (different Au-layer thickness). Die shear tests and cross-sections have been performed on as-bonded, thermally cycled, and thermally aged samples to characterize the bonding properties associated with the different processing techniques, metallization schemes, and environmental stress tests. A uniform Au-rich bond interface was produced (the $zeta$ phase with a melting point of 522$^{circ}{rm C}$). The importance of excess Au on both substrate and chip side in the final bond is demonstrated. It is shown that Au–Sn SLID can absorb thermo-mechanical stresses induced by large coefficient of thermal expansion mismatches (up to 12 ppm/K) in a packaging system during HT thermal cycling. The bonding strength of Au–Sn SLID is shown to be superb, exceeding 78 MPa. However, after HT thermal ageing, the $zeta$ phase was first- converted into the more Au-rich $beta$ phase. This created physical contact between the Sn and Ni atoms, resulting in brittle ${rm Ni}_{x}{rm Sn}_{y}$ phases, reducing the bond strength. Density functional theory calculations have been performed to demonstrate that the formation of ${rm Ni}_{x}{rm Sn}_{y}$ in preference to the Au-rich Au–Sn phases is energetically favorable. View full abstract»

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  • Low-Pressure Joining of Large-Area Devices on Copper Using Nanosilver Paste

    Page(s): 915 - 922
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    Low-temperature joining technology using nanosilver paste has been widely demonstrated for attaching power chips on silver or gold metallized substrates. In this paper, we investigate the processing conditions of nanosilver paste for bonding large-area chips on a plain copper surface. A double-print, low-pressure-assisted sintering process is developed for attaching the chips on copper. An evaluation criterion used in the process development is the bond strength of mechanical chips that are made of alumina and sintered on direct-bond-copper (DBC) substrates. The bond strength, measured by the die-shear test, is found to be in excess of 40 and 77 MPa at sintering pressures of 3 and 12 MPa, respectively, during sintering. Characterization of the bondline microstructure reveals a void-free sintered joint, the density of which increases, with increasing sintering pressure. Sintering in air causes partial oxidation of the copper surface, but the oxide can be easily removed by dipping in 1% hydrochloric acid solution. To evaluate the impact of the bonding and acid-cleaning process on device characteristics, a large-area insulated-gate-bipolar-transistor (IGBT) chip is bonded to DBC substrate and then wire-bonded for electrical testing. Test results shows that the die-attach process does not alter the IGBT performance. View full abstract»

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  • Low-Temperature and Low-Pressure Die Bonding Using Thin Ag-Flake and Ag-Particle Pastes for Power Devices

    Page(s): 923 - 929
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    The operating temperature of new-generation power semiconductors is expected to exceed 150$^{circ}{rm C}$. To develop a low heat-resistant die-attachment technology that can be processed at relatively low temperatures, four Ag filler-based die-bonding materials are investigated. They include Ag micrometer-particles, Ag nanoparticles, Ag micrometer-flakes, and Ag nano-thick-flakes, and are mixed with a solvent to formulate into pastes. These Ag pastes are printed onto three types of substrate, bare Cu and Cu with Au and Ag finishes, and then the bonding experiments are carried out at temperatures of 160$^{circ}{rm C}$–220 $^{circ}{rm C}$ for 60 min. At 200$^{circ}{rm C}$ and 220$^{circ}{rm C}$, the die bonding onto the Cu substrate with Ag finish using the Ag micrometer-flake paste is found to have an excellent shear strength of 36.0 and 39.1 MPa while the die bonding using the other three pastes all have shear strengths below 20 MPa. This can be explained in terms of the bonded interface area formed with the Ag micrometer-flake paste, which is significantly larger than those formed with the other three Ag pastes. Therefore, the Ag micrometer-flake paste promises to provide sufficient die-bonding strength at low temperatures. View full abstract»

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  • Experimental Study of Thermosonic Gold Bump Flip-Chip Bonding With a Smooth End Tool

    Page(s): 930 - 934
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    Thermosonic flip-chip (TSFC) bonding is a flexible and rapidly developing package technology, in which ultrasonic energy is used to reduce bonding temperature, time, and force. In this paper, a laboratory TSFC bonder with a smooth end tool and without vacuum or a die collet was developed to bond a gold bump to a silver pad in order to understand the effect of ultrasonic energy on flip-chip bonding strength. With a laser Doppler vibrometer, the ultrasonic vibration of the tool and flip chip were measured during the bonding process. In addition, the energy loss between the tool and chip was observed. The relationship between energy loss, ultrasonic propagation, bump deformation, and bonding parameters was discussed. The effects of bonding parameters on bonding strength and vibration transferred from the tool to chip were experimentally investigated. Results show that energy losses prevent over-bonding phenomenon caused by an excess of ultrasonic power. Good bonding strength can be achieved by optimizing bonding parameters using a tool without a vacuum or collet. Compared to vacuum-based or groove tools, smooth-end tools are able to automatically control the ultrasonic energy applied at the bonding interface. View full abstract»

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  • 3-D Multilayer Copper Interconnects for High-Performance Monolithic Devices and Passives

    Page(s): 935 - 942
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    This paper presents a new and efficient low-cost multilayer 3-D copper interconnect process for monolithic devices and passives. It relies on the BPN and SU-8 photoresists, associated with an optimized electroplating process to form multilevel 3-D interconnects in a single metallization step. The SU-8 is used as a permanent thick dielectric layer that is patterned underneath specific locations to create the desired 3-D interconnect shape. A 3-D seed layer is deposited above the SU-8 and the substrate to ensure 3-D electroplating current flow. The BPN is used as a thick mold for copper electroplating with an aspect ratio as high as 16:1. An optimized 3-D copper electroplating process is later used to grow 3-D interconnects, ensuring transition between all metallic layers. Finally, high-Q (55 at 5 GHz) power inductors are designed and integrated above a 50 W RF power laterally diffused metal oxide semiconductor device using this process. View full abstract»

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  • Performance and Robustness of 3-D Integrated SRAM Considering Tier-to-Tier Thermal and Supply Crosstalk

    Page(s): 943 - 953
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    This paper analyzes the effect of tier-to-tier thermal and supply crosstalk on the performance and robustness of the static random access memory (SRAM) within a 3-D stack under crosstalk influence of the logic cores. Our framework integrates distributed process variation aware circuit analysis, RC-based thermal simulation, and distributed RLC-based power delivery network simulation. The analysis shows when the logic cores and SRAMs are integrated in 3-D stack, the thermal and supply crosstalk degrade the SRAM performance and noise margin during read and write operations. View full abstract»

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  • Packaging Process for Grating-Coupled Silicon Photonic Waveguides Using Angle-Polished Fibers

    Page(s): 954 - 959
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    A novel process for fiber-packaging submicrometer silicon waveguides is presented. The process uses fibers polished at an angle to reflect light between a horizontal core and the slightly off-vertical input and output path of a grating coupler. The necessity for a reflective coating on the fiber facet is overcome through the use of total internal reflection and a novel technique of epoxy distribution based on capillary action. Simulations of alignment tolerance are presented, along with measurements confirming the applicability of passive alignment. A peak coupling efficiency within 0.2 dB of the theoretical maximum for the grating coupler is achieved. View full abstract»

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  • Mechanical, Electrical, and Thermal Coupled-Field Simulation of a Molten Metal Bridge During Contact Separation

    Page(s): 960 - 966
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    The purpose of this paper is to present a numerical simulation of the behavior of a molten metal bridge during contact separation. Sequential coupling allows for studying the interactions between mechanical, electrical, and thermal phenomena occurring under a low current flow (between 5 and 25 A). The 2-D axisymmetric geometry model considers a sphere pressed on a plane. The model takes into account the temperature dependence of material properties. Contact resistance, separation acceleration, and current rate are obtained by experiments and are also applied to the model. The structural deformations and the voltage and temperature distributions are calculated with the help of the finite element method. Results show that the time is less than 30 $mu{rm s}$ from the separation of contact to the generation of a molten metal bridge under current loads of 5–25 A; the index change relation is shown between temperature of central node and separation time; the current density has a nonuniform distribution along the section of a molten metal bridge; whatever be the initial loads, melting and vaporizing voltages of a molten metal bridge are, respectively, 0.38 and 0.66 V, which are basically consistent with the literature. View full abstract»

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  • Performance and Reliability Analysis of Hybrid Concentrating Photovoltaic/Thermal Collectors With Tree-Shaped Channel Nets' Cooling System

    Page(s): 967 - 977
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    Excess temperatures on concentrating photovoltaic (PV) modules can lead to a decrease in electrical efficiency and irreversible structural damage. Therefore, designing an appropriate cooling system becomes necessary for the lifetime and performance of concentrating PV (CPV) modules. The basic design considerations for cooling systems include low and uniform cell temperatures, minimal pumping power, high PV efficiencies, and system reliability. In this paper, a 3-D multiphysics computational model for a hybrid concentrating photovoltaic/thermal (HCPV/T) water collector is developed. The collector consists of a solar concentrator, 40 silicon cells connected in series, and a multichannel liquid cooling system with heat-recovery capability. A conjugate heat transfer model is used, assuming laminar flow through either parallel or tree-shaped branching cooling channels. The temperature distributions within the PV cells are determined for different cooling strategies. Comparisons are made by considering the thermal and electrical performances, such as PV cell temperature, electrical efficiency, and outlet water temperature, between a system incorporating tree-shaped channel networks and one having straight parallel channel cooling arrays. For identical convective surface area and pumping pressures in both configurations, the tree-shaped branched channel cooling networks yield lower PV cell temperatures and more uniform temperature distributions within the PV cells. Additionally, a finite-element mechanical analysis is used to estimate the fatigue life of the PV modules based on the temperature profiles obtained from both cooling channel configurations under a specified pumping pressure. The model results predict that the fatigue life of the module with the branched channels is almost twice that of the module with straight channels. View full abstract»

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  • Experimental and Numerical Studies of Finned L-Shape Heat Pipe for Notebook-PC Cooling

    Page(s): 978 - 988
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    This paper presents the experimental, numerical, and analytical investigations on the horizontal L-shape heat pipe for the notebook-CPU cooling. Simulations are carried out for both the 2-D and 3-D cases. In a 3-D model, the heat pipe as a whole is modeled based on the heat transfer by conduction. The heat pipe is assumed to be a conducting medium without taking into account the events occurring inside the heat pipe. A 2-D model based on the characterization of the working fluid inside the heat pipe is the other developed model. The 2-D finite element simulation is performed under natural and forced convection modes, by using ANSYS-FLOTRAN. Moreover, the design of experiment software is employed to optimize the coolant airflow rate and the heat input to get the best performance of heat pipe. The wall temperatures, velocity, and pressure distributions of the vapor and the liquid are analyzed. The heat inputs of the minimum thermal resistance in both natural and forced convection are found to be 20 and 35 W, respectively. The simulation and experimental wall temperatures are found to be a good match. Accordingly, the numerical solution is in agreement with the analytical solution in terms of vapor and liquid pressure drops. View full abstract»

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  • Coelectrodeposited Solder Composite Films for Advanced Thermal Interface Materials

    Page(s): 989 - 996
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    A novel coelectrodeposition process was explored to form composite solder thin films as advanced bonding layers with potentially superior thermal and mechanical properties. The solder electrolyte was modified with SiC and graphite particles to electroplate the solder composite films. The stability of the particles was enhanced with cetyltrimethylammonium bromide (CTAB) as the surfactant. CTAB also enhanced the positive charge of the surface, measured as zeta potential, to further improve the electrophoretic deposition of the particles. Dynamic light scattering was used, for the first time, to characterize the particle size distribution and zeta potential for the graphite-tin electrolyte suspensions. Incorporation of CTAB enhanced the zeta potential from 17 to 33 mV and improved the particle dispersion resulting in much homogeneous plating with higher particle content in the films. X-ray diffraction, energy dispersive spectroscopy, and scanning electron microscopy were utilized to characterize the plated composites. Bonding was demonstrated with solder composites having high particle loading. Pressure-assisted bonding enhanced solder wetting on particles and improved the bonding characteristics. View full abstract»

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  • Thermal Dynamical Identification of Light-Emitting Diodes by Step-Based Realization and Convex Optimization

    Page(s): 997 - 1007
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    A new method for modeling the thermal response of semiconductor devices such as light-emitting diodes (LEDs) from temperature measurements is presented. The method uses a realization-theoretic approach to identification combined with convex optimization methods. Linear matrix inequalities are constructed to guarantee that the identified discrete-time model has strictly real eigenvalues between 0 and 1, so that, when converted to continuous time, the model will have strictly real time constants. Additional optional time-domain constraints are developed to guarantee a predetermined steady-state value, guarantee no undershoot or overshoot in the transient response, and/or guarantee a positive time-constant spectrum. The method is applied to the thermal response of a high-power LED. Temperature measurements of the semiconductor device are used to model the time constants of the thermal response and characterize the relative contribution of each time constant to temperature increase. Experiments indicate how the proposed method can be used to detect thermal defects. It is shown that models with five time constants can model the thermal effects of the LEDs used with high accuracy. The proposed method is applicable to larger order systems with multiple simultaneous temperature measurements. View full abstract»

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  • Dielectric Resonators With High Q -Factor for Tunable Low Phase Noise Oscillators

    Page(s): 1008 - 1015
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    This paper demonstrates the realization of tunable microwave low phase noise oscillators. A ceramic-based dielectric resonator enclosed in a metallic cavity with an unloaded $Q$ of 13000 is proposed. The relationship between geometric parameters and resonant frequency is determined. The dielectric puck is then incorporated into multilayer printed circuit boards by using substrate-integrated waveguide techniques. The results show that the resonator resonates at ${rm TE}_{01delta}$ mode with a frequency of 13.3 GHz. Therefore, 13.3 GHz dielectric resonator oscillators with both mechanic and electronic tuning are built. The oscillator includes a pseudomorphic high-electron-mobility transistor low-noise amplifier and an electronic phase shifter. The measured phase noise of the oscillator is ${-}{rm 121.7}~{rm dBc}/{rm Hz}$ at a 10-kHz offset. The calculated and measured phase noise results show a difference of 3 dB. View full abstract»

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  • Common-Mode Noise Reduction Schemes for Weakly Coupled Differential Serpentine Delay Microstrip Lines

    Page(s): 1016 - 1027
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    This paper proposes design schemes to reduce the common mode noise from weakly coupled differential serpentine delay microstrip lines (DSDMLs). The proposed approach is twofold: we leverage strongly coupled vertical-turn-coupled traces (VTCTs) instead of weakly coupled VTCTs (conventional pattern) and add guard traces. Time-and frequency-domain analyses of the proposed schemes for reducing the common-mode noise are performed by studying the transmission waveform and the differential-to-common mode conversion using the circuit solver HSPICE and the 3-D full-wave simulator HFSS, respectively. Compared to the conventional design of the weakly coupled DSDMLs, the proposed solutions yield a reduction of about 54% of the peak-to-peak amplitude of the common-mode noise, while the differential impedance remains matched along the complete length of the DSDML. Moreover, the range of frequencies, over which the magnitude of the differential-to-common mode conversion is now significantly reduced, is very wide, i.e., about 0.3–10 GHz. Furthermore, the differential insertion and reflection loss introduced by the newly proposed designs are almost the same as the ones achieved by using the conventional design. Finally, a favorable comparison between simulated and measured results confirms the excellent common-mode noise reduction performance of the proposed schemes. View full abstract»

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  • Passivity-Preserving Parameterized Model Order Reduction Using Singular Values and Matrix Interpolation

    Page(s): 1028 - 1037
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    We present a parameterized model order reduction method based on singular values and matrix interpolation. First, a fast technique using grammians is utilized to estimate the reduced order, and then common projection matrices are used to build parameterized reduced order models (ROMs). The design space is divided into cells, and a Krylov subspace is computed for each cell vertex model. The truncation of the singular values of the merged Krylov subspaces from the models located at the vertices of each cell yields a common projection matrix per design space cell. Finally, the reduced system matrices are interpolated using positive interpolation schemes to obtain a guaranteed passive parameterized ROM. Pertinent numerical results validate the proposed technique. View full abstract»

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  • Broadband Characterization of Coplanar Waveguide Interconnects With Rough Conductor Surfaces

    Page(s): 1038 - 1046
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    This paper presents a method to simulate the effects of conductor surface roughness on conductor-backed coplanar waveguide (CB-CPW) interconnects using 3-D full wave simulation tools. In this paper, a high-frequency structure simulator (HFSS) from ANSYS has been implemented for rough surfaces with Gaussian correlation functions. The rough surfaces that exist between the dielectric and copper foils are modeled using a statistical random process approach. The varying heights for the random rough surface with specified autocorrelation function (ACF), root mean square height (Hrms), and correlation length (λ) are generated using Matlab, and these data are used in HFSS to model and simulate the performance of the CB-CPW interconnect with rough conductor surfaces. The results show that both Hrms and λ influence the overall attenuation coefficient, and the trends are consistent with the other studies in this area. The method presented in this paper provides designers with a technique to characterize the effect of conductor surface roughness for different types of transmission lines with varying substrates and extent of conductor roughness. View full abstract»

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  • Macromodeling of Multilayered Power Distribution Networks Based on Multiconductor Transmission Line Approach

    Page(s): 1047 - 1056
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    Typical modeling algorithms for multilayered irregular shaped power distribution networks are based on a finite difference solution of the Helmholtz equation. In this paper, the finite difference solution is demonstrated to be equivalent to a discretization of the Telegraphers partial differential equations for multiconductor transmission lines (MTL). With this concept, an efficient macromodeling algorithm for multilayered structures based on MTL theory is presented. The electromagnetic coupling between the plane layers due to wraparound currents is captured by the inductive and capacitive coupling between the multiconductor lines. A delay extraction-based macromodel is used to represent the MTL in SPICE that can better capture the distributed effects of the structure than existing lumped models. This approach is successfully implemented for multilayered structures with irregular geometries and is shown to be more accurate and efficient compared with existing SPICE lumped models. View full abstract»

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  • Effects of Lignin Derivatives on Cross-Link Density and Dielectric Properties in the Epoxy-Based Insulating Materials for Printed Circuit Boards

    Page(s): 1057 - 1062
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    Bio-plastics are made from renewable biomass sources. We focus on lignin and develop epoxy resins containing lignin derivatives. We describe the preparation and application of epoxy resin containing lignin as a matrix. Soda-lignin (SLG) is obtained from black liquor in a soda pulp process. First, we use a lignin manufacturing process in which a methanol extraction method enabled reduction in the molecular and hydroxyl equivalent weights of lignin and removal of ${rm SiO}_{2}$ and cellulose. Second, we investigate the ratio of diglycidyl ether of bisphenol-A (DGEBA) and methanol extraction SLG (me-SLG). From the viewpoint of cross-linking density and dielectric properties, 100/84 phr in the DGEBA/me-SLG casting system is found to be preferable. Finally, we try to fabricate an insulating material made up of DGEBA/me-SLG for an aluminum-based printed circuit board, and it achieves standard values. View full abstract»

    Open Access
  • Application of Sequence-Dependent Traveling Salesman Problem in Printed Circuit Board Assembly

    Page(s): 1063 - 1076
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    Optimization issues regarding the automated assembly of printed circuit boards attracted the interest of researchers for several decades. This is because even small gains in assembly time result in very important benefits in mass production. In this paper, the focus is on a particular placement machine type that has a rotational turret and a stationary component magazine. So far, this type of machine received little attention among the researchers. In this paper, the feeder configuration, placement sequencing, and assembly time minimization problems are formulated explicitly and completely (without simplifying assumptions) using nonlinear integer programming. In addition, the placement sequencing problem is shown to be a recently introduced new generalization of the traveling salesman problem (the sequence-dependent traveling salesman). These formulations show the complexity of the problems and the need for effective heuristic designs for solving them. We propose three heuristics that improve previously suggested solution methods and give comparable results when compared to simulated annealing that is a widely accepted good performing metaheuristic on combinatorial optimization problems. The heuristics are experimentally shown to improve previous methods significantly in assembly time that implies a huge economic benefit. The heuristics proposed could also be applied to other placement machines with similar operation principles. View full abstract»

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  • IEEE Components, Packaging, and Manufacturing Technology Society information for authors

    Page(s): C3
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  • IEEE Components, Packaging, and Manufacturing Technology Society Information

    Page(s): C4
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Aims & Scope

IEEE Transactions on Components, Packaging, and Manufacturing Technology publishes research and application articles on modeling, design, building blocks, technical infrastructure, and analysis underpinning electronic, photonic and MEMS packaging.

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Meet Our Editors

Managing Editor
R. Wayne Johnson
Auburn University