# IEEE Transactions on Computers

## Filter Results

Displaying Results 1 - 16 of 16
• ### Architecting against Software Cache-Based Side-Channel Attacks

Publication Year: 2013, Page(s):1276 - 1288
Cited by:  Papers (10)
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Using cache-like architectural components including data caches, instruction caches, or branch target buffers as a side channel, software cache-based side-channel attacks are able to derive secret keys used in cryptographic operations through legitimate software activities. Existing software solutions are typically application specific and incur substantial performance overhead. Recent hardware pr... View full abstract»

• ### A Systematic Methodology to Generate Decomposable and Responsive Power Models for CMPs

Publication Year: 2013, Page(s):1289 - 1302
Cited by:  Papers (30)
| |PDF (3222 KB) | HTML Media

Power modeling based on performance monitoring counters (PMCs) attracted the interest of researchers since it became a quick approach to understand the power behavior of real systems. Consequently, several power-aware policies use models to guide their decisions. Hence, the presence of power models that are informative, accurate, and capable of detecting power phases is critical to improve the suc... View full abstract»

• ### Expandable and Cost-Effective Network Structures for Data Centers Using Dual-Port Servers

Publication Year: 2013, Page(s):1303 - 1317
Cited by:  Papers (32)
| |PDF (1484 KB) | HTML

A fundamental goal of data center networking is to efficiently interconnect a large number of servers with the low equipment cost. Several server-centric network structures for data centers have been proposed. They, however, are not truly expandable and suffer a low degree of regularity and symmetry. Inspired by the commodity servers in today's data centers that come with dual port, we consider ho... View full abstract»

• ### Generalization of an Enhanced ECC Methodology for Low Power PSRAM

Publication Year: 2013, Page(s):1318 - 1331
Cited by:  Papers (1)
| |PDF (1714 KB) | HTML Media

Error control codes (ECCs) have been widely used to maintain the reliability of memories, but ordinary ECC codes are not suitable for memories with long codewords. For portable products, power reduction in memories with DRAM-like cells can be done by reducing the refresh frequency, but the loss of data integrity should be taken care of seriously. To solve these issues, we have proposed a parallel ... View full abstract»

• ### Hybrid CPU Management for Adapting to the Diversity of Virtual Machines

Publication Year: 2013, Page(s):1332 - 1344
Cited by:  Papers (1)
| |PDF (1188 KB) | HTML Media

As an important cornerstone for clouds, virtualization plays a vital role in building this emerging infrastructure. Virtual machines (VMs) with a variety of workloads may run simultaneously on a physical machine in the cloud platform. The scheduling algorithm used in Xen schedules virtual CPUs (VCPUs) of a VM asynchronously and guarantees the proportion of the CPU time allocated to the VM. This pr... View full abstract»

• ### Improved Three-Way Split Formulas for Binary Polynomial and Toeplitz Matrix Vector Products

Publication Year: 2013, Page(s):1345 - 1361
Cited by:  Papers (15)
| |PDF (1990 KB) | HTML

In this paper, we consider three-way split formulas for binary polynomial multiplication and Toeplitz matrix vector product (TMVP). We first recall the best known three-way split formulas for polynomial multiplication: the formulas with six recursive multiplications given by Sunar in a 2006 IEEE Transactions on Computers paper and the formula with five recursive multiplications proposed by Bernste... View full abstract»

• ### L-Networks: A Topological Model for Regular 2D Interconnection Networks

Publication Year: 2013, Page(s):1362 - 1375
Cited by:  Papers (6)
| |PDF (870 KB) | HTML Media

A complete family of Cayley graphs of degree four, denoted as L-networks, is considered in this paper. L-networks are 2D mesh-based topologies with wrap-around connections. L-networks constitute a graph-based model which englobe many previously proposed 2D interconnection networks. Some of them have been extensively used in the industry as the underlying topology for parallel and distributed compu... View full abstract»

• ### Low-Cost Concurrent Error Detection for Floating-Point Unit (FPU) Controllers

Publication Year: 2013, Page(s):1376 - 1388
Cited by:  Papers (3)
| |PDF (1434 KB) | HTML

We present a nonintrusive concurrent error detection (CED) method for protecting the control logic of a contemporary floating-point unit (FPU). The proposed method is based on the observation that control logic errors lead to extensive data path corruption and affect, with high probability, the exponent part of the IEEE-754 floating-point representation. Thus, exponent monitoring can be utilized t... View full abstract»

• ### Modular Design of High-Throughput, Low-Latency Sorting Units

Publication Year: 2013, Page(s):1389 - 1402
Cited by:  Papers (12)
| |PDF (2156 KB) | HTML

High-throughput and low-latency sorting is a key requirement in many applications that deal with large amounts of data. This paper presents efficient techniques for designing high-throughput, low-latency sorting units. Our sorting architectures utilize modular design techniques that hierarchically construct large sorting units from smaller building blocks. The sorting units are optimized for situa... View full abstract»

• ### On Designing Protocols for Noncooperative, Multiradio Channel Assignment in Multiple Collision Domains

Publication Year: 2013, Page(s):1403 - 1416
Cited by:  Papers (1)
| |PDF (796 KB) | HTML

Channel assignment is a crucial problem for wireless networks, especially for noncooperative wireless networks, in which nodes are selfish. While there have been a few studies of noncooperative, multiradio channel assignment, most existing studies are restricted to single collision domains only. In this paper, we study the design of incentive-compatible protocols for noncooperative, multiradio cha... View full abstract»

• ### Optimizing Nonindexed Join Processing in Flash Storage-Based Systems

Publication Year: 2013, Page(s):1417 - 1431
Cited by:  Papers (5)
| |PDF (1609 KB) | HTML Media

Flash memory-based disks (or simply flash disks) have been widely used in today's computer systems. With their continuously increasing capacity and dropping price, it is envisioned that some database systems will operate on flash disks in the near future. However, the I/O characteristics of flash disks are different from those of magnetic hard disks. Motivated by this, we study the core of query p... View full abstract»

• ### ReCREW: A Reliable Flash-Dissemination System

Publication Year: 2013, Page(s):1432 - 1446
| |PDF (1403 KB) | HTML

In this paper, we explore a new form of dissemination that arises in distributed, mission-critical applications called Flash Dissemination. This involves the rapid dissemination of rich information to a large number of recipients in a very short period of time. A key characteristic of Flash Dissemination is its unpredictability (e.g., natural hazards), but when invoked it must harness all possible... View full abstract»

• ### RFID Support for Accurate 3D Localization

Publication Year: 2013, Page(s):1447 - 1459
Cited by:  Papers (14)
| |PDF (3575 KB) | HTML

This paper pursues RFID support for localization, aiming to pinpoint an object in 3D space. Given a set of RFID tags and/or readers deployed as reference points at known locations in a hexahedron (like shipping container or storage room), a passive and an active localization schemes are considered in this paper. Being the very first range-free 3D localization, our schemes depend solely on RFID tag... View full abstract»

• ### Binary Integer Decimal-Based Floating-Point Multiplication

Publication Year: 2013, Page(s):1460 - 1466
Cited by:  Papers (6)
| |PDF (1095 KB) | HTML

This paper presents a multiplier that operates on binary integer decimal (BID) encoded decimal floating-point (DFP) numbers. It uses a single binary multiplier with carry-save feedback for both significand multiplication and rounding, and it is compliant with the IEEE 754-2008 Standard. Optimizations decrease the BID multiplier's area and critical path delay. View full abstract»

• ### Multiway Splitting Method for Toeplitz Matrix Vector Product

Publication Year: 2013, Page(s):1467 - 1471
Cited by:  Papers (15)
| |PDF (257 KB) | HTML

Computing the product of a Toeplitz matrix and a vector arises in various applications including cryptography. In this paper, we consider Toeplitz matrices and vectors with entries in $({hbox{rlap{I}kern 2.0pt{hbox{F}}}}_2)$. For improved efficiency in such computations, large Toeplitz matrices and vectors are recursively split and special formulas with subquadratic arithmetic complexity are appli... View full abstract»

• ### Strong Diagnosability and Conditional Diagnosability of Multiprocessor Systems and Folded Hypercubes

Publication Year: 2013, Page(s):1472 - 1477
Cited by:  Papers (26)
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Using the comparison diagnosis model, this study proposes some useful sufficient conditions for determining the strong diagnosability ts(G) and the conditional diagnosability tc(G) of a system G. Applying these results to an n-dimensional folded hypercube FQn shows that ts(FQn) = n + 1 for n ≥ 5 and tc(FQn) = 3n - 2 for n &#x... View full abstract»

## Aims & Scope

The IEEE Transactions on Computers is a monthly publication with a wide distribution to researchers, developers, technical managers, and educators in the computer field.

Full Aims & Scope

## Meet Our Editors

Editor-in-Chief
Paolo Montuschi
Politecnico di Torino
Dipartimento di Automatica e Informatica
Corso Duca degli Abruzzi 24
10129 Torino - Italy
e-mail: pmo@computer.org