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Solid-State Circuits, IEEE Journal of

Issue 6 • Date June 2013

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Displaying Results 1 - 25 of 26
  • Table of contents

    Page(s): C1 - C4
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  • IEEE Journal of Solid-State Circuits publication information

    Page(s): C2
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  • Table of contents

    Page(s): 1325 - 1326
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  • Full-Duplex Crystalless CMOS Transceiver With an On-Chip Antenna for Wireless Communication in a Hybrid Engine Controller Board

    Page(s): 1327 - 1342
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (3426 KB) |  | HTML iconHTML  

    A full-duplex transceiver for wireless inter-chip data communication in an engine controller board of hybrid electric vehicles is demonstrated. The amplitude shift keying (ASK) transceiver incorporates a clock data recovery circuit for crystalless operation as well as for simultaneous generation of a 24-GHz local oscillator signal and a 400-MHz clock for data recovery. The transceiver also integrates an on-chip antenna and a duplexer. The bit error rate (BER) degradation of RX due to the full duplex operation of transceiver with an on-chip antenna is negligible when the input power is greater than -44 dBm necessary to achieve a BER of less than 10-12. This is the first demonstration of full duplex operation for an integrated circuit incorporating an on-chip antenna. The transceiver is fabricated in a 130-nm CMOS technology and consumes 245 mW. View full abstract»

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  • A Low Power BAW Resonator Based 2.4-GHz Receiver With Bandwidth Tunable Channel Selection Filter at RF

    Page(s): 1343 - 1356
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2741 KB) |  | HTML iconHTML  

    A low power sub-sampling multi-channel 2.4-GHz receiver front-end is presented. Bulk Acoustic Wave (BAW) resonators which intrinsically exhibit high quality factor (Q) are exploited in the frequency synthesis to provide low phase noise signal with low power consumption. A low power solution to perform channel selection and filtering directly at RF by employing current reuse and using a BAW resonator is proposed. The filter is capable of tuning the bandwidth and thus making the front-end to be suitable for multi-band/multi-standard applications. The overall performance of the front-end is improved by additional discrete time filtering which also down-converts the wanted channel to baseband in quadrature. The proposed front-end is designed and integrated in a 0.18-μm CMOS process. Measurements reveal that the front-end is capable of providing very narrow band filtering down to 300 kHz. The rejection at 10-MHz offset is 62 dB with conversion gain of 44.2 dB. View full abstract»

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  • The Outphasing RF Power Amplifier: A Comprehensive Analysis and a Class-B CMOS Realization

    Page(s): 1357 - 1369
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2368 KB) |  | HTML iconHTML  

    We present a theoretically comprehensive treatment of outphasing systems that utilize radio-frequency high-efficiency PAs. We separately analyze encoding and clipping distortions and how they accounts for most of the nonlinearities in outphasing systems. With that insight, we have designed an inherently linear outphasing system at high efficiency. We have implemented these techniques in a 90-nm Class-B prototype that uses signal-dependent time-varying circuits under close digital control to achieve 56%, 44%, and 30% efficiency for GSM, EDGE, and WCDMA modulations, while demonstrating linearity commensurate with demanding specifications on adjacent channel leakage. View full abstract»

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  • Tunable N-Path Notch Filters for Blocker Suppression: Modeling and Verification

    Page(s): 1370 - 1382
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    N-path switched-RC circuits can realize filters with very high linearity and compression point while they are tunable by a clock frequency. In this paper, both differential and single-ended N-path notch filters are modeled and analyzed. Closed-form equations provide design equations for the main filtering characteristics and nonidealities such as: harmonic mixing, switch resistance, mismatch and phase imbalance, clock rise and fall times, noise, and insertion loss. Both an eight-path single-ended and differential notch filter are implemented in 65-nm CMOS technology. The notch center frequency, which is determined by the switching frequency, is tunable from 0.1 to 1.2 GHz. In a 50-Ω environment, the N-path filters provide power matching in the passband with an insertion loss of 1.4-2.8 dB. The rejection at the notch frequency is 21-24 dB, P1 dB > +2 dBm, and IIP3 > +17 dBm. View full abstract»

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  • A 12-Gb/s Multichannel I/O Using MIMO Crosstalk Cancellation and Signal Reutilization in 65-nm CMOS

    Page(s): 1383 - 1397
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (4194 KB) |  | HTML iconHTML  

    A crosstalk cancellation and signal reutilization (XTCR) analog front-end implemented with infinite impulse response (IIR) networks dramatically improves signal integrity across multiple closely-spaced single-ended PCB traces. The XTCR technique has been designed to address multiple high-speed I/Os from the ground up. To verify this technique a 4 channel prototype was implemented in 65 nm CMOS. This 4 channel prototype design handles crosstalk cancellation for single-ended I/Os operating at 12 Gb/s. At this speed, the prototype XTCR design improves the measured average horizontal and vertical-eye openings by 37.5% and 26.4% at 10-8 BER, while consuming only 0.96 pJ/b/lane. View full abstract»

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  • A Bang-Bang Clock and Data Recovery Using Mixed Mode Adaptive Loop Gain Strategy

    Page(s): 1398 - 1415
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (4062 KB) |  | HTML iconHTML  

    A Bang-Bang Clock and Data Recovery (CDR) with adaptive loop gain strategy is presented. The proposed strategy enhances CDR jitter performance even if jitter spectrum information is limited a priori. By exploiting the inherent hard-nonlinearity of Bang-Bang Phase Detector (BBPD), the CDR loop gain is adaptively adjusted based on a posteriori jitter spectrum estimation. Maximizing advantages of analog and digital implementations, the proposed mixed-mode technique achieves PVT insensitive and power efficient loop gain adaptation for high speed applications even in limited ft technologies. A modified CML D-latch improves CDR input sensitivity and BBPD performance. A folded-cascode- based Charge Pump (CP) is proposed to minimize CP latency. The 5 G/10 G CDR prototype is fabricated in 0.18 μm CMOS technology to demonstrate the effectiveness of the proposed techniques for applications with high ratio of data-rate to ft. The proposed CDR recovers data with BER <; 2·10-13 and generates only 1.04 ps RMS and 7.5 ps peak-peak jitter. Jitter Tolerance (JTOL) test shows that the proposed CDR enhances low frequency jitter tracking and high frequency jitter filtering simultaneously for various jitter profiles. The CDR power consumption is 110.6 mW where only 3.9 mW is used for loop gain adaptation circuitry. View full abstract»

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  • Clock Multiplication Techniques Using Digital Multiplying Delay-Locked Loops

    Page(s): 1416 - 1428
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    A highly-digital clock multiplication architecture that achieves excellent jitter and mitigates supply noise is presented. The proposed architecture utilizes a calibration-free digital multiplying delay-locked loop (MDLL) to decouple the tradeoff between time-to-digital converter (TDC) resolution and oscillator phase noise in digital phase-locked loops (PLLs). Both reduction in jitter accumulation down to sub-picosecond levels and improved supply noise rejection over conventional PLL architectures is demonstrated with low power consumption. A digital PLL that employs a 1-bit TDC and a low power regulator that seeks to improve supply noise immunity without increasing loop delay is presented and used to compare with the proposed MDLL. The prototype MDLL and DPLL chips are fabricated in a 0.13 μm CMOS technology and operate from a nominal 1.1 V supply. The proposed MDLL achieves an integrated jitter of 400 fs rms at 1.5 GHz output frequency from a 375 MHz reference clock, while consuming 890 μ W. The worst-case supply noise sensitivity of the MDLL is 20 fspp/mVpp which translates to a jitter degradation of 3.8 ps in the presence of 200 mV supply noise. The proposed clock multipliers occupy active die areas of 0.25 mm2 and 0.2 mm2 for the MDLL and DPLL, respectively. View full abstract»

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  • A 6-b 4.1-GS/s Flash ADC With Time-Domain Latch Interpolation in 90-nm CMOS

    Page(s): 1429 - 1441
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2865 KB) |  | HTML iconHTML  

    A 6-b 4.1-GS/s flash ADC was fabricated using a 90-nm CMOS with a time-domain latch interpolation technique that reduces the number of front-end dynamic comparators by half. The reduced number of comparators lowers power consumption, load capacitance to the T/H circuit, and the overhead of comparator calibration. The measured peak INL and DNL after comparator calibration are 0.74 and 0.49 LSB, respectively. The measured SNDR and SFDR are 31.2 and 38.3 dB, respectively, with a 2.02-GHz input at 4.1-GS/s operation while consuming 76 mW of total power. This ADC achieves a figure of merit of 0.625 pJ/conversion-step at 4.1 GS/s. View full abstract»

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  • A 10-b 1-GHz 33-mW CMOS ADC

    Page(s): 1442 - 1452
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1780 KB) |  | HTML iconHTML  

    This paper describes a pipelined analog-to-digital converter that resolves 4 b in its first stage and amplifies the residue by a factor of 2, thereby relaxing the opamp linearity, voltage swing, and gain requirements. Calibration in the digital domain removes the effect of capacitor mismatches and corrects for the gain error. Using a one-stage opamp with a gain of 10 and realized in 65-nm CMOS technology, the ADC digitizes a 490-MHz input with a signal-to-(noise+distortion) ratio of 52.4 dB, achieving a figure of merit of 97 fJ/conversion-step. View full abstract»

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  • A Resolution-Reconfigurable 5-to-10-Bit 0.4-to-1 V Power Scalable SAR ADC for Sensor Applications

    Page(s): 1453 - 1464
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    A power-scalable SAR ADC for sensor applications is presented. The ADC features a reconfigurable 5-to-10-bit DAC whose power scales exponentially with resolution. At low resolutions where noise and linearity requirements are reduced, supply voltage scaling is leveraged to further reduce the energy-per-conversion. The ADC operates up to 2 MS/s at 1 V and 5 kS/s at 0.4 V, and its power scales linearly with sample rate down to leakage levels of 53 nW at 1 V and 4 nW at 0.4 V. Leakage power-gating during a SLEEP mode in between conversions reduces total power by up to 14% at sample rates below 1 kS/s. Prototyped in a low-power 65 nm CMOS process, the ADC in 10-bit mode achieves an INL and DNL of 0.57 LSB and 0.58 LSB respectively at 0.6 V, and the Nyquist SNDR and SFDR are 55 dB and 69 dB respectively at 0.55 V and 20 kS/s. The ADC achieves an optimal FOM of 22.4 fJ/conversion-step at 0.55 V in 10-bit mode. The combined techniques of DAC resolution and voltage scaling maximize efficiency at low resolutions, resulting in an FOM that increases by only 7x over the 5-bit scaling range, improving upon a 32x degradation that would otherwise arise from truncation of bits from an ADC of fixed resolution and voltage. View full abstract»

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  • A Second-Order ΔΣ ADC Using Noise-Shaped Two-Step Integrating Quantizer

    Page(s): 1465 - 1474
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1946 KB) |  | HTML iconHTML  

    In this paper, a new second-order discrete-time ΔΣ ADC using a noise-shaped two-step integrating quantizer is presented. The first quantization step (coarse) is utilized with a flash ADC. The second quantization step (fine) is implemented using a noise-shaped integrating quantizer. As a result, both high resolution and first-order noise shaping is achieved. High quantization resolution enhances the modulator stability whereas the extra order of noise-shaping improves the overall performance. The proposed ΔΣ ADC incorporating the noise-shaped two-step integrating quantizer manifests a second-order noise-shaping with a first-order loop filter. To accommodate the large number of quantization levels of the feedback-DAC, a new feedback topology is presented which uses both analog and digital signals. The prototype ADC is implemented in 0.13 μm CMOS and demonstrates peak SNDR of 70.7 dB while consuming 8.1 mW under a 1.2 V supply, with an OSR of 8 at 80 MHz sampling frequency. View full abstract»

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  • A 10-b Two-Stage DAC with an Area-Efficient Multiple-Output Voltage Selector and a Linearity-Enhanced DAC-Embedded Op-Amp for LCD Column Driver ICs

    Page(s): 1475 - 1486
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    This work proposes a 10-b two-stage DAC with an area-efficient multiple-output voltage selector and a linearity-enhanced DAC-embedded op-amp for LCD column driver ICs. The proposed voltage selector is divided into two stages, MSB and LSB decoders; this design requires fewer switches compared with tree-type voltage selectors, enabling a smaller die area. The proposed 6-b two-voltage selector occupies only 61% of the area needed for a 6-b tree-type two-voltage selector. This study also develops a generalized architecture for an area-efficient voltage selector for multiple outputs. To improve the linearity of the DAC-embedded op-amp, the differential pairs operate at the edge of the saturation region. The 10-b DAC prototypes were produced with 0.35- μm/0.5- μm CMOS technology with the worst DNL/INL being 0.44/0.58 LSB. View full abstract»

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  • An Orthogonal Current-Reuse Amplifier for Multi-Channel Sensing

    Page(s): 1487 - 1496
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2027 KB) |  | HTML iconHTML  

    We demonstrate a micropower low-noise CMOS amplifier array that reuses bias current to improve the fundamental noise-power tradeoffs of fully-differential amplifier designs. The presented circuit implements current-reuse by stacking the differential input pairs of four amplifiers. The output drain currents of each channel's differential pair are used as the tail currents for the differential pairs of the succeeding channel. Orthogonal current-reuse improves the noise and power tradeoff by sharing bias devices to conserve headroom. With four channels (n = 4), there are 16 unique output currents (2n) from the stack, each of which is a linear combination of the four inputs. Amplified versions of the original input signals are reconstructed by appropriately combining the small-signal output currents in output stages that operate at much lower bias currents. With an input-referred noise of 3.7 μVrms and a bandwidth of 19.9 kHz, a single channel achieves a noise efficiency factor (NEF) of 3.0. Amortizing the bias current across the amplifier's four channels yields an effective NEF of 1.64. The total power consumption is 15.6 μW, or 3.9 μW per path from a 1.5 V supply. Orthogonal biasing suppresses crosstalk between the channels, providing an isolation of 40 dB under 3-σ mismatch. The implemented circuit was fabricated in a standard 130 nm CMOS process and occupies an area of 0.125 mm2. The proposed technique is useful for a variety of applications ranging from low-power neural recording arrays to multiphase radio baseband amplifiers. View full abstract»

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  • A Low-Power DCVSL-Like GIDL-Free Voltage Driver for Low-Cost RFID Nonvolatile Memory

    Page(s): 1497 - 1510
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    The realization of a low-cost passive radio frequency identification (RFID) tag requires the ability to fabricate the system in a bulk CMOS process without any additional process steps. A recently presented single-poly C-Flash memory bitcell provides an ultralow-power option for implementation of a nonvolatile memory array for use in an RFID system, using only core masks. This cell requires the application of a 10-V potential difference between the cell's control lines for program and erase operations. Providing the required voltages, while using only standard devices results in several design challenges for the voltage drivers, such as the elimination of gate-induced drain leakage (GIDL) currents. In this paper, we present a pair of voltage driver architectures that utilize novel techniques to overcome these challenges. In addition, for the first time, we present an in-depth analysis of the dynamic behavior of standard level shifters. This analysis is applied to our proposed GIDL-free level shifters to provide a sizing methodology for optimization of the area, energy-per-operation, and delay of these circuits. The drivers were designed and fabricated in a TowerJazz 0.18- μm bulk CMOS technology, providing the required functionality with a low static-power figure of 47-49 pW and 0.03-0.36 pJ energy-per-operation. View full abstract»

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  • A 1 Mb Nonvolatile Embedded Memory Using 4T2MTJ Cell With 32 b Fine-Grained Power Gating Scheme

    Page(s): 1511 - 1520
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    A 1 Mb nonvolatile embedded memory using a four transistor and two spin-transfer-torque (STT) magnetic tunnel junction (MTJ) cell is designed and fabricated to demonstrate its zero standby power and high performance. The power supply voltages of 32 cells along a word line (WL) are controlled simultaneously by a power line (PL) driver to eliminate the standby power without impact on the access time. This fine-grained power gating scheme also optimizes the trade-off between macro size and operation power. The butterfly curve for the cell is measured to be asymmetric as predicted, enhancing the cell's static noise margin (SNM) for data retention. The scaling of 1 Mb macro size is compared with that of the 6T SRAM counterpart, indicating that the former will become smaller than the latter at 45 nm technology node and beyond by moderately thinning its tunnel dielectrics (MgO) in accordance with the shrink of the MTJ's cross sectional area. The operation current of the macro is also shown to be almost unchanged over generations, while that of the 6T SRAM increases exponentially due to the degradation of MOSFET off-current as the device scales. View full abstract»

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  • A High Layer Scalability TSV-Based 3D-SRAM With Semi-Master-Slave Structure and Self-Timed Differential-TSV for High-Performance Universal-Memory-Capacity-Platforms

    Page(s): 1521 - 1529
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2329 KB) |  | HTML iconHTML  

    TSV-based 3D die-stacking technology enables the reuse of pre-designed, pre-tested logic dies stacked with multiple memory layers (NSTACK) in various configurations to form a universal-memory-capacity platform (UMCP). However, conventional 3D memories suffer speed, power and yield overheads due to the large parasitic load of TSV and cross-layer PVT variations when implemented in large NSTACK with wide IO, especially using via-last TSVs. This work proposes a semi-master-slave (SMS) memory structure with self-timed differential-TSV signal transfer (STDT) scheme to improve the speed, power, and yield of 3D memory devices, while providing high scalability in NSTACK for 3D-UMCP. The SMS scheme achieves the following: 1) a constant-load logic-SRAM interface across various NSTACK; 2) high tolerance for variations in cross-layer PVT, and 3) at-speed pre-bonding KGD sorting. The STDT scheme employs a TSV-load tracking scheme to achieve small TSV voltage swing for suppressing power and speed overheads of cross-layer TSV signal communication resulting from large TSV parasitic loads, particularly in UMCP designs with scalable NSTACK and wide-IO. To verify the viability of the proposed structure and scheme, we developed a 2-layer 32 kb 3D-SRAM testchip with layer-scalable test-modes using a via-last TSV process with die-to-die bonding. This testchip confirmed the functionality and demonstrated superior scalability in NSTACK with small speed overheads. View full abstract»

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  • 1.2-V Supply, 100-nW, 1.09-V Bandgap and 0.7-V Supply, 52.5-nW, 0.55-V Subbandgap Reference Circuits for Nanowatt CMOS LSIs

    Page(s): 1530 - 1538
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1419 KB) |  | HTML iconHTML  

    This paper presents bandgap reference (BGR) and sub-BGR circuits for nanowatt LSIs. The circuits consist of a nano-ampere current reference circuit, a bipolar transistor, and proportional-to-absolute-temperature (PTAT) voltage generators. The proposed circuits avoid the use of resistors and contain only MOSFETs and one bipolar transistor. Because the sub-BGR circuit divides the output voltage of the bipolar transistor without resistors, it can operate at a sub-1-V supply. The experimental results obtained in the 0.18-μm CMOS process demonstrated that the BGR circuit could generate a reference voltage of 1.09 V and the sub-BGR circuit could generate one of 0.548 V. The power dissipations of the BGR and sub-BGR circuits corresponded to 100 and 52.5 nW. View full abstract»

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  • Correction to “A Linearized, Low Phase Noise VCO Based 25 GHz PLL With Autonomic Biasing”

    Page(s): 1539
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (135 KB)  

    The authors of the above-named article [ibid., vol. 48, no. 5, pp. 1138-1150, May 2013] used a different variable, tB, for the bias tuning knob in equation (3) as compared to in the rest of the paper. Using the consistent variable, Vg, bias, for the bias tuning knob, the equation is revised. View full abstract»

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  • Correction to "A 0.016 mm² 144-µW Three-Stage Amplifier Capable of Driving 1-to-15 nF Capacitive Load With >0.95-MHz GBW"

    Page(s): 1539
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    In the above-named article [ibid., vol. 48, no. 2, pp. 527-540, Feb. 2013], US Patent 7,646,247 (Jan. 12, 2010) was cited in the description of Fig. 8, for a more general description about the utilization and advantages of the Gma stage. However, the article by U. Dasgupta "Issues in "Ahuja" frequency compensation technique," (Proc. IEEE Int. Symp. Radio-Frequency Integration Technology, 2009, pp. 326-329) exhibits the circuit implementation of the Gma stage (improved Ahuja compensation circuit), which, for that reason, should have been referenced for completeness, as well. The authors would like to thank Dr. U. Dasgupta for pointing out this missing information. View full abstract»

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  • Correction to “A 2 Gb/s Throughput CMOS Transceiver Chipset With In-Package Antenna for 60 GHz Short-Range Wireless Communication”

    Page(s): 1540
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    The authors made an error in Fig. 19 in the above-named article [ibid., vol. 47, no. 12, pp. 3160–3171, Dec. 2012]. The figure is the same as Fig. 13 by mistake. The correct figure "Data rate/throughput measurement setup" is shown here. The authors apologize for any confusion. View full abstract»

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  • Patent Abstracts

    Page(s): 1541 - 1551
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    Freely Available from IEEE
  • IEEE Asian Solid-State Circuits Conference

    Page(s): 1552
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    Freely Available from IEEE

Aims & Scope

The IEEE Journal of Solid-State Circuits publishes papers each month in the broad area of solid-state circuits with particular emphasis on transistor-level design of integrated circuits.

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Meet Our Editors

Editor-in-Chief
Michael Flynn
University of Michigan