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Computers & Digital Techniques, IET

Issue 1 • Date Jan. 2013

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Displaying Results 1 - 6 of 6
  • Algebraic approach to time borrowing

    Page(s): 1 - 10
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (491 KB)  

    This study describes a novel application of max-plus linear algebra to the timing of digital hardware. The authors give a rigorous, algorithmic approach to `time borrowing' - a technique whereby the use of a multi-phase clock can allow for a more flexible, efficient use of time. In this approach the system is clocked periodically, but within each clock cycle processes interact asynchronously, allowing longer processes to be juxtaposed with shorter processes. The authors have shown that this problem can be solved completely using linear algebra defined over the max-plus semi-ring. This work establishes the mathematical foundation of an earlier, heuristic approach to the problem. View full abstract»

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  • Power bumps and through-silicon-vias placement with optimised power mesh structure for power delivery network in three-dimensional-integrated circuits

    Page(s): 11 - 20
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (787 KB)  

    Three-dimensional-integrated circuits (3D-ICs) bring new issues for power delivery network design because of larger current density and more complicated power delivery paths compared to 2D-IC. The power delivery network consists of power bumps, through-silicon-vias (TSVs), and power wires. IR-drop at each node varies with the number and position of power bumps and TSVs. These three power resources affect IR-drop of 3D-ICs. In this study, the authors propose power delivery network design methodology to optimise power resources wherease IR-drop constraint is satisfied. The simulation results show that the proposed method minimises the number of power bumps and TSVs compared to the conventional method. View full abstract»

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  • Static test compaction for mixed broadside and skewed-load transition fault test sets

    Page(s): 21 - 28
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (209 KB)  

    Test sets that consist of both broadside and skewed-load tests provide improved delay fault coverage for standard-scan circuits. This study describes a static test compaction procedure for such test sets. The unique feature of the procedure is that it can modify the type of a test (from broadside to skewed-load or from skewed-load to broadside) if this contributes to test compaction. Given a test set W, the basic static test compaction procedure described in this study considers for inclusion in the compacted test set both a broadside and a skewed-load test based on every test wW. It selects the test type that detects the higher number of faults. An improved procedure considers a broadside and a skewed-load test based on a test wW only if w detects a minimum number of faults (without changing its type). Experimental results demonstrate that the static test compaction procedure is typically able to reduce the sizes of mixed test sets further than a procedure that does not modify test types. The procedure modifies the types of significant numbers of tests before including them in the compacted test set. View full abstract»

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  • High-performance FPGA implementations of the cryptographic hash function JH

    Page(s): 29 - 40
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (822 KB)  

    Hash functions are included in almost all cryptographic schemes and security protocols for providing authentication services. JH is a new hash function, introduced in 2008 and it is among the five finalists of the international competition for developing the new hash standard SHA-3. In this study, one non-pipelined and four pipelined architectures are introduced for developing high-performance field-programmable gate array (FPGA) designs of the JH function. Special effort has been paid and various design alternatives have been studied to derive efficient FPGA implementations in terms of frequency, area and throughput/area cost factor. Compared with the best existing non-pipelined FPGA implementations, the throughput/area is improved by 48, 13.5 and 17.8% in Xilinx Virtex-4, Virtex-5 and Virtex-6 families, respectively, and by 6.8 and 21.2% in ALTERA Stratix-III and Stratix-IV, respectively. Also, the improvements of the throughput/area factor of the introduced pipelined architectures over the existing ones are 37.5, 73.1, 15 and 26.3% in Virtex-5, Virtex-6, Stratix-III and Stratix-IV technologies, respectively. View full abstract»

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  • Design and evaluation of fine-grain-mode transition method based on dynamic memory access analysing for variable stages pipeline processor

    Page(s): 41 - 47
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (516 KB)  

    This study proposes a fine-grain-mode transition method for variable stages pipeline (VSP) processor. The method is based on dynamic memory access analysing and it reduces energy consumption. A VSP processor varies the pipeline depth dynamically according to workload. When the workload is heavy, the processor shifts into a high-speed mode that drives a deep pipeline at a high clock frequency. When the workload is light, the processor shifts into a low-energy mode that unifies pipeline stages to make the pipeline shallower and drives it at a low clock frequency. The conventional mode transition method cannot follow sharp workload changes because it takes a long time to predict workload. The fine-grain pipeline depth control, this study proposes, is based on a high-speed workload prediction mechanism using memory access frequency, and it uses a novel method to conceal the overhead because of changing the pipeline depth. Simulation results show that the authors approach can reduce the energy-delay product 10% below what it would be with the conventional approach. View full abstract»

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  • Three-factor control protocol based on elliptic curve cryptosystem for universal serial bus mass storage devices

    Page(s): 48 - 56
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (299 KB)  

    This study proposes a three-factor control protocol for universal serial bus (USB) on an elliptic curve cryptosystem (ECC). USB is a universal interface used in an enormous number of devices. It has become the most popular interface standard for computer connections. However, since USB provides high transmission speed and is very convenient to carry, many workplace and commercial establishments have prohibited their employees from using USB devices. This precaution is an important way to prevent confidential data leaks via USB devices, as USB connections lack security management. Therefore the authors use a three-factor control protocol to ensure the security of USB connections. The proposed authentication protocol combines biometric, password and smart card to provide high security on the USB mutual authentication. To provide secure and efficient transmission between the user and the USB server, the proposed protocol adopts ECC to encrypt data. Compared to other encryption methods, the proposed protocol uses much smaller key sizes. As a further benefit, this protocol reduces the smart card computational cost and provides an efficient transmission for USB devices. This new scheme improves the security, efficiency and usability of the authentication process. More studies on USB are needed. View full abstract»

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IET Computers & Digital Techniques publishes technical papers describing recent research and development work in all aspects of digital system-on-chip design and test of electronic and embedded systems.

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