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Very Large Scale Integration (VLSI) Systems, IEEE Transactions on

Issue 6 • Date June 2013

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Displaying Results 1 - 21 of 21
  • Table of contents

    Publication Year: 2013 , Page(s): C1 - C4
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  • IEEE Transactions on Very Large Scale Integration (VLSI) Systems publication information

    Publication Year: 2013 , Page(s): C2
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  • Circuit-Level Timing Error Tolerance for Low-Power DSP Filters and Transforms

    Publication Year: 2013 , Page(s): 989 - 999
    Cited by:  Papers (5)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (869 KB) |  | HTML iconHTML  

    In this paper, we present a novel circuit-level timing error mitigation technique, which aims to increase energy-efficiency of digital signal processing datapaths without loss of robustness. Timing errors are detected using razor flip-flops on critical-paths, and the error-rate feedback is used to control a dynamic voltage scaling control loop. In place of conventional razor error correction by replay, we propose a new approach to bound the magnitude of intermittent timing errors at the circuit level. A timing guard-band is created by shaping the path delay distribution such that the critical paths correspond to a group of least-significant bit registers. These end-points are ensured to be critical by modifying the topology of the final stage carry-merge adder, and by using tool-based device sizing. Hence, timing violations lead to weakly correlated logical errors of small magnitude in a mean-squared-error sense. We examine this approach in an finite-impulse response (FIR) filter and a 2-D discrete cosine transform implementation, in 32-nm CMOS. Power saving compared to a conventional design at iso-frequency is 21%-23% at the typical corner, while retaining a voltage guard-band to protect against fast transient changes in switching activity and supply noise. The impact on minimum clock period is small (16%-20%), as it does not necessitate the use of ripple-carry adders and also requires only a bare minimum of additional design effort. View full abstract»

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  • Hardware Variability-Aware Duty Cycling for Embedded Sensors

    Publication Year: 2013 , Page(s): 1000 - 1012
    Cited by:  Papers (3)
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    Instance and temperature-dependent power variation has a direct impact on quality of sensing for battery-powered long-running sensing applications. We measure and characterize the active and leakage power for an ARM Cortex M3 processor and show that, across a temperature range of 20 -60, there is a 10% variation in active power, and a variation in leakage power. We introduce variability-aware duty cycling methods and a duty cycle (DC) abstraction for TinyOS which allows applications to explicitly specify the lifetime and minimum DC requirements for individual tasks, and dynamically adjusts the DC rates so that the overall quality of service is maximized in the presence of power variability. We show that variability-aware duty cycling yields a improvement in total active time over schedules based on worst case estimations of power, with an average improvement of across a wide variety of deployment scenarios based on the collected temperature traces. Conversely, datasheet power specifications fail to meet required lifetimes by 7%-15%, with an average 37 days short of the required lifetime of 1 year. Finally, we show that a target localization application using variability-aware DC yields a 50% improvement in quality of results over one based on worst case estimations of power consumption. View full abstract»

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  • MAEPER: Matching Access and Error Patterns With Error-Free Resource for Low Vcc L1 Cache

    Publication Year: 2013 , Page(s): 1013 - 1026
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    Large SRAMs are the practical bottleneck to achieve a low supply voltage, because they suffer from process variation-induced bit errors at a low supply voltage. In this paper, we present an error-resilient cache architecture that resolves the drawback of previous approaches, i.e., the performance degradation at a low supply voltage which is caused by cache misses in accesses to faulty resources. We utilize cache access locality and error-free resources in a cost-effective manner. First, we classify cache lines into fully and partially accessed groups and apply appropriate methods to each group. For the partially accessed group, we propose a method of matching memory access behavior and error locations with intra-cache line word-level remapping. In order to reduce the area overhead used to store the cache access information history, we present an access pattern-learning line-fill buffer (LFB). For the fully accessed group, we propose the utilization of error-free assist functions in the cache, i.e., a LFB and victim cache with no process variation-induced error at the target minimum supply voltage. We also present an error-aware prefetch method that allows us to utilize the error-free victim cache to achieve a further reduction in cache misses due to faulty resources. Experimental results show that the proposed method gives an average 32.6% reduction in cycles per instruction at an error rate of 0.2% with a small area overhead of 8.2%. View full abstract»

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  • Self-Repairing Digital System With Unified Recovery Process Inspired by Endocrine Cellular Communication

    Publication Year: 2013 , Page(s): 1027 - 1040
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2829 KB) |  | HTML iconHTML  

    Self-repairing digital systems have recently emerged as the most promising alternative for fault-tolerant systems. However, such systems are still impractical in many cases, particularly due to the complex rerouting process that follows cell replacement. They lose efficiency when the circuit size increases, due to the extra hardware in addition to the functional circuit and the unutilization of normal operating hardware for fault recovery. In this paper, we propose a system inspired by endocrine cellular communication, which simplifies the rerouting process in two ways: 1) by lowering the hardware overhead along with the increasing size of the circuit and 2) by reducing the hardware unutilized for fault recovery while maintaining good fault-coverage. The proposed system is composed of a structural layer and a gene-control layer. The structural layer consists of novel modules and their interconnections. In each module of our system, the encoded data, called the genome, contains information about the function and the connection. Therefore, a faulty module can be replaced and the whole system's functions and connections are maintained by simply assigning the same encoded data to a spare (stem) module. In existing systems, a huge amount of hardware, such as a dynamic routing system, is required for such an operation. The gene-control layer determines the neighboring spare module in the structural layer to replace the faulty module without collision. We verified the proposed mechanism by implementing the system with a field-programmable gate array with the application of a digital clock whose status can be monitored with light-emitting-diodes. In comparison with existing methods, the proposed architecture and mechanism are efficient enough for application with real fault-tolerant systems dealing with harsh and remote environments, such as outer space or deep sea. View full abstract»

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  • Dual-Level Adaptive Supply Voltage System for Variation Resilience

    Publication Year: 2013 , Page(s): 1041 - 1052
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    VLSI circuits of the 45-nm technology and beyond are increasingly affected by process variations as well as aging effects. Overcoming the variations inevitably requires additional power expense, which in turn aggravates the power and heat problem. Adaptive supply voltage (ASV) is an arguably power-efficient approach for variation resilience since it attempts to allocate power resources only to where the negative effect of variations is strong. We propose a dual-level ASV (dual-ASV) system for designs containing many timing critical paths. This system can simultaneously provide ASV at both coarse-grained and fine-grained levels, and has limited power routing overhead. The dual-ASV system is compared with conventional ASV through SPICE simulations on benchmark circuits. The results indicate that the dual-ASV system consumes significantly less power and achieves similar performance in the presence of variations. View full abstract»

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  • Addressing Transient and Permanent Faults in NoC With Efficient Fault-Tolerant Deflection Router

    Publication Year: 2013 , Page(s): 1053 - 1066
    Cited by:  Papers (6)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2022 KB) |  | HTML iconHTML  

    Continuing decrease in the feature size of integrated circuits leads to increases in susceptibility to transient and permanent faults. This paper proposes a fault-tolerant solution for a bufferless network-on-chip, including an on-line fault-diagnosis mechanism to detect both transient and permanent faults, a hybrid automatic repeat request, and forward error correction link-level error control scheme to handle transient faults and a reinforcement-learning-based fault-tolerant deflection routing (FTDR) algorithm to tolerate permanent faults without deadlock and livelock. A hierarchical-routing-table-based algorithm (FTDR-H) is also presented to reduce the area overhead of the FTDR router. Synthesized results show that, compared with the FTDR router, the FTDR-H router can reduce the area by 27% in an 88 network. Simulation results demonstrate that under synthetic workloads, in the presence of permanent link faults, the throughput of an 8 8 network with FTDR and FTDR-H algorithms are 14% and 23% higher on average than that with the fault-on-neighbor (FoN) aware deflection routing algorithm and the cost-based deflection routing algorithm, respectively. Under real application workloads, the FTDR-H algorithm achieves 20% less hop counts on average than that of the FoN algorithm. For transient faults, the performance of the FTDR router can achieve graceful degradation even at a high fault rate. We also implement the fault-tolerant deflection router which can achieve 400 MHz in TSMC 65-nm technology. View full abstract»

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  • Combined Architecture/Algorithm Approach to Fast FPGA Routing

    Publication Year: 2013 , Page(s): 1067 - 1079
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    We propose a new field-programmable gate array (FPGA) routing approach, which, when combined with a low-cost architecture change, results in a 40% reduction in router runtime, at the cost of a 6% area overhead and with no increase in critical path delay. Our approach begins with PathFinder-style routing, which we run on a coarsened representation of the routing architecture. This leads to fast generation of a partial routing solution where the signals are assigned to groups of wire segments rather than individual wire segments. A Boolean satisfiability (SAT)-based stage follows, generating a legal routing solution from the partial solution. We explore approximately 165 000 FPGA switch block architectures, showing that the choice of the architecture has a significant impact on the complexity of the SAT formulation, and by extension, on routing runtime. Our approach points to a new research direction, namely, reducing FPGA computer-aided design runtime by exploring FPGA architectures and algorithms together. View full abstract»

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  • IsoNet: Hardware-Based Job Queue Management for Many-Core Architectures

    Publication Year: 2013 , Page(s): 1080 - 1093
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1072 KB) |  | HTML iconHTML  

    Imbalanced distribution of workloads across a chip multiprocessor (CMP) constitutes wasteful use of resources. Most existing load distribution and balancing techniques employ very limited hardware support and rely predominantly on software for their operation. This paper introduces IsoNet, a hardware-based conflict-free dynamic load distribution and balancing engine. IsoNet is a lightweight job queue manager responsible for administering the list of jobs to be executed, and maintaining load balance among all CMP cores. By exploiting a micro-network of load-balancing modules, the proposed mechanism is shown to effectively reinforce concurrent computation in many-core environments. Detailed evaluation using a full-system simulation framework indicates that IsoNet significantly outperforms existing techniques and scales efficiently to as many as 1024 cores. Furthermore, to assess its feasibility, the IsoNet design is synthesized, placed, and routed in 45-nm VLSI technology. Analysis of the resulting low-level implementation shows that IsoNet's area and power overhead are almost negligible. View full abstract»

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  • Data Allocation Optimization for Hybrid Scratch Pad Memory With SRAM and Nonvolatile Memory

    Publication Year: 2013 , Page(s): 1094 - 1102
    Cited by:  Papers (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (466 KB) |  | HTML iconHTML  

    Embedded systems normally have a tight energy budget. Since the on-chip cache typically consumes 25%-50% of the processor's area and energy consumption, scratch pad memory (SPM), which is a software-controlled on-chip memory, has been widely adopted in many embedded systems due to its smaller area and lower power consumption. However, as the speed of the CMOS transistors increases along with density, leakage power consumption is becoming a critical issue for memory components with a large number of transistors. In this paper, we propose a novel hybrid SPM which consists of static random-access memory (SRAM) and nonvolatile memory (NVM) to take advantage of the ultralow leakage power and high density of latter. A novel dynamic data management algorithm is also proposed to make use of the full potential of NVM. According to the experimental results, with the help of the proposed algorithm, the novel hybrid SPM architecture can reduce the memory access time by 18.17%, the dynamic energy by 24.29%, and the leakage power by 37.34% compared with a baseline pure SRAM SPM with the same area. View full abstract»

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  • Scalable Signal Selection for Post-Silicon Debug

    Publication Year: 2013 , Page(s): 1103 - 1115
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1586 KB) |  | HTML iconHTML  

    As modern integrated circuits increase in size and complexity, more and more verification effort is necessary to ensure their error-free operation. This has motivated designers to apply post-silicon debugging techniques to their designs, such as by embedding trace instrumentation within. However, a key drawback to this approach is that only a small subset of a chip's internal signals can be traced, but selecting the most effective signals to observe must be determined before fabrication and before the nature of any errors is known. This paper explores the tradeoff between the scalability of automated signal selection algorithms, and the amount of circuit observability that they offer. Three selection methods are presented: a technique that optimizes for observability directly; a method based on the graph-centrality of the circuit's connectivity; and a hybrid technique that combines both algorithms through exploiting the circuit hierarchy. To quantify the observability of each technique, we define the debug difficulty metric to measure how accurately the traced data can be used to resolve a circuit's state behavior. Although we find that the graph-based method offers the least observability of the three algorithms, it was the only method that could be applied to our largest benchmark of over 50 000 flip-flops, computing a selection in less than 90 s. Last, we present a novel application that can only be enabled by these scalable algorithms-speculative debug insertion for field-programmable gate arrays. View full abstract»

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  • Per-Device Adaptive Test for Analog/RF Circuits Using Entropy-Based Process Monitoring

    Publication Year: 2013 , Page(s): 1116 - 1128
    Cited by:  Papers (2)
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    We present an adaptive test flow for mixed-signal circuits that aims at optimizing the test set on a per-device basis so that more test resources can be devoted to marginal devices while passing devices that are not marginal with less testing. Cumulative statistics of the process are monitored using a differential entropy-based approach and updated only when necessary. Thus, process shift is captured and continuously incorporated into the analysis. We also include provisions to identify potentially defective devices and test them more extensively since these devices do not conform to learned collective information. We conduct experiments on an low-noise amplifier circuit in simulations, and apply our techniques to production data of two distinct industrial circuits. Both the simulation results and the results on large-scale production data show that adaptive test provides the best tradeoff between test time and test quality as measured in terms of defective parts per million. View full abstract»

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  • Crosstalk- and Process Variations-Aware High-Quality Tests for Small-Delay Defects

    Publication Year: 2013 , Page(s): 1129 - 1142
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    The population of small-delay defects (SDDs) in integrated circuits increases significantly as technology scales to 65 nm and below. Therefore, testing for SDDs is necessary to ensure the quality and reliability of high-performance integrated circuits fabricated with the latest technologies. Commercial timing-aware automatic test pattern generation (ATPG) tools have been developed for SDD detection. However, they only use static timing analysis reports in the form of standard delay format for path-length calculation and neglect important underlying causes, such as process variations, crosstalk, and power-supply noise, which can also induce small delays into the circuit and impact the timing of targeted paths. In this paper, we present an efficient pattern evaluation and selection procedure for screening SDDs that are caused by physical defects and by delays added to paths by process variations and crosstalk. In this procedure, the best patterns for SDDs are selected from a large repository test set. Experimental results demonstrate that our method sensitizes more LPs, detects more SDDs with a much smaller pattern count, and needs less CPU runtime compared with a commercial timing-aware ATPG tool. View full abstract»

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  • Asynchronous Fine-Grain Power-Gated Logic

    Publication Year: 2013 , Page(s): 1143 - 1153
    Cited by:  Papers (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (638 KB) |  | HTML iconHTML  

    This paper presents a novel low-power logic family, called asynchronous fine-grain power-gated logic (AFPL). Each pipeline stage in the AFPL circuit is comprised of efficient charge recovery logic (ECRL) gates, which implement the logic function of the stage, and a handshake controller, which handles handshaking with the neighboring stages and provides power to the ECRL gates. In the AFPL circuit, ECRL gates acquire power and become active only when performing useful computations, and idle ECRL gates are not powered and thus have negligible leakage power dissipation. The partial charge reuse (PCR) mechanism can be incorporated in the AFPL circuit. With the PCR mechanism, part of the charge on the output nodes of an ECRL gate entering the discharge phase can be reused to charge the output nodes of another ECRL gate about to evaluate, reducing the energy dissipation required to complete the evaluation of an ECRL gate. Moreover, AFPL-PCR adopts an enhanced C-element, called C*-element, in its handshake controllers such that an ECRL gate in AFPL-PCR can enter the sleep mode early once its output has been received by the downstream pipeline stage. To mitigate the hardware overhead of the AFPL circuit, two techniques of circuit simplification have been developed. View full abstract»

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  • All-Digital Fast-Locking Pulsewidth-Control Circuit With Programmable Duty Cycle

    Publication Year: 2013 , Page(s): 1154 - 1164
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    This paper proposes an all-digital fast-locking pulsewidth-control circuit with programmable duty cycle. In comparison with prior state-of-the-art methods, our use of two delay lines and a time-to-digital detector allows the pulsewidth-control circuit to operate over a wide frequency range with fewer delay cells, while maintaining the same level of accuracy. This paper presents a new duty-cycle setting circuit that calculates the desired output duty cycle without the need for a look-up table. The circuit was fabricated under the two-stage matrix converter 0.18-CMOS process. Results show that the proposed circuit performs well for an input operating frequency ranging from 200 to 600 MHz, and an input duty cycle ranging from 30% to 70%. It achieves a programmable output duty cycle ranging from 31.25% to 68.75% in increments of 6.25%. View full abstract»

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  • Efficient Implementation of Reconfigurable Warped Digital Filters With Variable Low-Pass, High-Pass, Bandpass, and Bandstop Responses

    Publication Year: 2013 , Page(s): 1165 - 1169
    Cited by:  Papers (5)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (483 KB) |  | HTML iconHTML  

    In this brief, an efficient implementation of reconfigurable warped digital filter with variable low-pass, high-pass, bandpass, and bandstop responses is presented. The warped filters, obtained by replacing each unit delay of a digital filter with an all-pass filter, are widely used for various audio processing applications. However, warped filters require first-order all-pass transformation to obtain variable low-pass or high-pass responses, and second-order all-pass transformation to obtain variable bandpass or bandstop responses. To overcome this drawback, the proposed method combines the warped filters with the coefficient decimation technique. The proposed architecture provides variable low-pass or high-pass responses with fine control over cut-off frequency and variable bandwidth bandpass or bandstop responses at an arbitrary center frequency without updating the filter coefficients or filter structure. The design example shows that the proposed variable digital filter is simple to design and offers substantial savings in gate counts and power consumption over other approaches. View full abstract»

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  • Fast Scan-Chain Ordering for 3-D-IC Designs Under Through-Silicon-Via (TSV) Constraints

    Publication Year: 2013 , Page(s): 1170 - 1174
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (340 KB) |  | HTML iconHTML  

    This brief addresses the problem of scan-chain ordering under a limited number of through-silicon vias (TSVs), and proposes a fast two-stage algorithm to compute a final order of scan flip-flops. To enable 3-D optimization, a greedy algorithm, multiple fragment heuristic, is modified and combined with a dynamic closest-pair data structure, FastPair, to derive a good initial solution in stage one. Stage two initiates two local refinement techniques, 3-D planarization and 3-D relaxation, to reduce the wire (and/or power) cost and to relax the number of TSVs in use to meet TSV constraints, respectively. Experimental results show that the proposed algorithm results in comparable performance (in terms of wire cost only, power cost only, and both wire-and-power cost) to a genetic-algorithm method but runs two-order faster, which makes it practical for TSV-constrained scan-chain ordering for 3-D-IC designs. View full abstract»

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  • Minimizing Energy of Integer Unit by Higher Voltage Flip-Flop: V_{\rm DD\min} -Aware Dual Supply Voltage Technique

    Publication Year: 2013 , Page(s): 1175 - 1179
    Cited by:  Papers (1)
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    To achieve the most energy-efficient operation, this brief presents a circuit design technique for separating the power supply voltage (VDD) of flip-flops (FFs) from that of combinational circuits, called the higher voltage FF (HVFF). Although VDD scaling can reduce the energy, the minimum operating voltage (VDDmin) of FFs prevents the operation at the optimum supply voltage that minimizes the energy, because the VDDmin of FFs is higher than the optimum supply voltage. In HVFF, the VDD of combinational logic gates is reduced below the VDDmin of FFs while keeping the VDD of FFs at their VDDmin. This makes it possible to minimize the energy without power and delay penalties at the nominal supply voltage (1.2 V) as well as without FF topological difications. A 16-bit integer unit with HVFF is fabricated in a 65-nm CMOS process, and measurement results show that HVFF reduces the minimum energy by 13% compared with the conventional operation, which is 1/10 times smaller than the energy at the nominal supply voltage. View full abstract»

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  • IEEE Transactions on Very Large Scale Integration (VLSI) Systems information for authors

    Publication Year: 2013 , Page(s): 1180
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  • IEEE Transactions on Very Large Scale Integration (VLSI) Systems society information

    Publication Year: 2013 , Page(s): C3
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Aims & Scope

Design and realization of microelectronic systems using VLSI/ULSI technologies require close collaboration among scientists and engineers in the fields of systems architecture, logic and circuit design, chips and wafer fabrication, packaging, testing, and systems applications. Generation of specifications, design, and verification must be performed at all abstraction levels, including the system, register-transfer, logic, circuit, transistor, and process levels.

To address this critical area through a common forum, the IEEE Transactions on VLSI Systems was founded. The editorial board, consisting of international experts, invites original papers which emphasize the novel system integration aspects of microelectronic systems, including interactions among system design and partitioning, logic and memory design, digital and analog circuit design, layout synthesis, CAD tools, chips and wafer fabrication, testing and packaging, and system level qualification. Thus, the coverage of this Transactions focuses on VLSI/ULSI microelectronic system integration.

Topics of special interest include, but are not strictly limited to, the following: • System Specification, Design and Partitioning, • System-level Test, • Reliable VLSI/ULSI Systems, • High Performance Computing and Communication Systems, • Wafer Scale Integration and Multichip Modules (MCMs), • High-Speed Interconnects in Microelectronic Systems, • VLSI/ULSI Neural Networks and Their Applications, • Adaptive Computing Systems with FPGA components, • Mixed Analog/Digital Systems, • Cost, Performance Tradeoffs of VLSI/ULSI Systems, • Adaptive Computing Using Reconfigurable Components (FPGAs) 

Full Aims & Scope

Meet Our Editors

Editor-in-Chief

Krishnendu Chakrabarty
Department of Electrical Engineering
Duke University
Durham, NC 27708 USA
Krish@duke.edu