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Electron Devices, IEEE Transactions on

Issue 6 • Date June 2013

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  • Table of contents

    Page(s): C1 - 1798
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  • IEEE Transactions on Electron Devices publication information

    Page(s): C2
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  • Small-Signal Capacitance and Current Parameter Modeling in Large-Scale High-Frequency Graphene Field-Effect Transistors

    Page(s): 1799 - 1806
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    An analytical model of the small-signal current and capacitance characteristics of radio frequency graphene field-effect transistors (GFETs) is presented. The model is based on explicit distributions of chemical potential in graphene channels (including ambipolar conductivity at high source-drain bias) obtained in the framework of drift-diffusion current continuity equation solution. Small-signal transconductance and output conductance characteristics are modeled by considering the two modes of drain current saturation, including drift velocity saturation or electrostatic pinchoff. Analytical closed expression for the complex current gain and the cutoff frequency of high-frequency GFETs are obtained. This model allows to describe an impact of parasitic resistances, capacitances, interface traps on extrinsic current gain, and cutoff frequency. View full abstract»

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  • Device and Circuit Performance Estimation of Junctionless Bulk FinFETs

    Page(s): 1807 - 1813
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    The design and characteristics of junctionless (JL) bulk FinFET devices and circuits are compared with the conventional inversion-mode (IM) bulk FinFET using 3-D quantum transport device simulation. The JL bulk FinFET shows better short channel characteristics, including drain-induced barrier lowering, subthreshold slope, and threshold voltage (Vth) roll-off characteristics at supply voltage (VDD) 1 V. Analyses of electron density and electricfield distributions in on-state and off-state also show that the JL devices have better on-off current ratios. Regarding design aspects, the effects of channel doping concentration (Nch) and Fin height (H)/width (W) on device Vth are also compared. In addition, the Vth of the proposed JL bulk FinFET can be easily tuned by an additional parameter, substrate doping concentration (Nsub). Inverter performance and static random access memory (SRAM) circuit performance are also compared using a coupled device-circuit simulation. The high-to-low delay time (tHL) and low-to-high delay time (tLH) of the inverter with JL bulk FinFET are smaller than the inverter with IM bulk FinFET. The JL bulk FinFET SRAM cell also provides a similar static transfer characteristic to those of IM bulk FinFET SRAM cell, which show large potential in digital circuit application. View full abstract»

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  • Comprehensive Analysis of Short-Channel Effects in Ultrathin SOI MOSFETs

    Page(s): 1814 - 1819
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    This paper analyzes the 2-D short-channel effect in ultrathin SOI MOSFETs. An empirical, channel length-dependent scale length is extracted from the lateral field slope of a series of numerically simulated devices. We show how this scale length is related to the short-channel threshold voltage roll-off and minimum channel length with and without a substrate bias. The benefit of a reverse substrate bias is investigated and understood in terms of the field and distribution of inversion charge in the silicon film. In particular, how a bulk-like short-channel effect is achieved when an accumulation layer is formed at the back surface. Furthermore, the effect of a high-κ gate insulator is studied and scaling implications discussed. View full abstract»

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  • Gate All Around MOSFET With Vacuum Gate Dielectric for Improved Hot Carrier Reliability and RF Performance

    Page(s): 1820 - 1827
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    In this paper, gate all around (GAA) MOSFET with vacuum gate dielectric is proposed for the first time for improved hot carrier reliability and RF performance. Analog and RF performance of the GAA MOSFET with vacuum gate dielectric (GAA VacuFET) is compared with conventional GAA MOSFET with SiO2 dielectric, and it is found that GAA VacuFET is superior to SiO2 dielectric for RF high-speed applications and more immune to the hot carrier damage because of low electric field at the drain side but it has a serious drawback of low on-current and transconductance as compared to SiO2 dielectric. In order to enhance the on current and transconductance of GAA VacuFET, Gate Electrode engineering and channel doping engineering are used. An analytical model is developed for dual material gate graded channel GAA MOSFET with vacuum gate dielectric (DMG GC VacuFET) and the model is verified with the simulated results. Incorporation of DMG and GC not only enhances digital and analog RF performance of GAA VacuFET but also hot carrier reliability is improved. View full abstract»

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  • Comparison of ZnO-Based JFET, MESFET, and MISFET

    Page(s): 1828 - 1833
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    We compare key properties of zinc oxide (ZnO)-based junction field-effect transistors (JFETs), metal-semiconductor field-effect transistors (MESFETs), and metal-insulator-semiconductor field-effect transistors (MISFETs) prepared from a common ZnO:Mg thin film. The JFETs are fabricated with a ZnCo2O4-gate, the MESFETs with reactively sputtered Pt-gate and the MISFETs with WO3 as gate insulator. The three FET types are compared with regarding dc characteristics, frequency dependence, and stability at temperatures up to 150°C. All devices can be switched within a similar gate voltage range of less than 3 V, making a direct comparison of the device characteristics possible. Measurements above room temperature show a common shift of the transfer curves to higher gate voltages, which seems to be a distinguishing property of ZnO compared with other semiconductors. All electric measurements show major differences between the devices, which can be attributed to the different gate structures. View full abstract»

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  • Compact Model for Carbon Nanotube Field-Effect Transistors Including Nonidealities and Calibrated With Experimental Data Down to 9-nm Gate Length

    Page(s): 1834 - 1843
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    A semianalytical carbon nanotube field-effect transistor (CNFET) model based on the virtual-source model is presented, which includes series resistance, parasitic capacitance, and direct source-to-drain tunneling leakage. The model is calibrated with recent experimental data down to 9-nm gate length. Device performance of 22- to 7-nm technology nodes is analyzed. The results suggest that contact resistance is the key performance limiter for CNFETs; direct source-to-drain tunneling results in significant leakage due to low effective mass in carbon nanotubes and prevents further downscaling of the gate length. The design space that minimizes the gate delay in CNFETs subject to OFF-state leakage current (IOFF) constraints is explored. Through the optimization of the length of the gate, contact, and extension regions to balance the parasitic effects, the gate delay can be improved by more than 10% at 11- and 7-nm technology nodes compared with the conventional 0.7 × scaling rule, while the OFF-state leakage current remains below 0.5 μA/μm . View full abstract»

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  • Time and Frequency Domain Characterization of Transistor Self-Heating

    Page(s): 1844 - 1851
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    Pulsed I-V and AC conductance or RF characterization techniques, within the time and the frequency domain, respectively, represent two approaches for evaluating self-heating in MOSFETs. In this paper, these methods are compared. Advantages and limitations of each technique are discussed and experimentally verified in silicon-on-insulator (SOI) MOSFETs. It is demonstrated that RF technique and the pulsed I-V hot chuck method agree well for the studied 130-nm-node partially depleted SOI devices. Applicability of the techniques for advanced technologies is discussed. View full abstract»

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  • Germanium Multiple-Gate Field-Effect Transistors Formed on Germanium-on-Insulator Substrate

    Page(s): 1852 - 1860
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    We demonstrate the integration of high performance p-channel Germanium Multiple-Gate Field-Effect Transistors (MuGFETs) on a Germanium-on-Insulator substrate. Detailed process conditions are documented in this paper. The effects of Ge fin doping concentration on the electrical performance of Ge MuGFETs are discussed, and this could be useful for further device optimization. It is found that a higher fin doping leads to better control of short-channel efforts of Ge MuGFETs but degrades the on-state current and transconductance. High on-state current for Ge MuGFETs is reported in this paper. View full abstract»

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  • Surface-Roughness-Limited Mean Free Path in Silicon Nanowire Field Effect Transistors

    Page(s): 1861 - 1866
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    The mean free path (MFP) in silicon nanowire field effect transistors limited by surface roughness scattering (SRS) is calculated with the nonperturbative approach utilizing the nonequilibrium Green's function method. The entrance scattering effect associated with finiteness of the channel length is identified and a method to eliminate it in the calculation of the MFP is developed. The behavior of the MFP with respect to channel length (L), channel width (W) , and the root mean square (rms) of the surface roughness is investigated extensively. Our major findings are that the single parameter, rms/W, can be used as a good measure for the strength of the SRS effects and that the overall characteristics of the MFP are determined by the parameter. In particular, the MFP exponentially decreases with the increase of rms/W and the MFP versus the gate electric field shows a distinctively different behavior depending on whether the strength of the SRS effects measured by rms/W is smaller or greater than 0.06. View full abstract»

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  • An Effective Capacitance Model for 28-nm and Beyond Copper Interconnect

    Page(s): 1867 - 1871
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    In 28-nm CMOS technology, copper interconnect becomes complicated as the dielectric copper diffusion barrier and low-κ damage compromise capacitance gain from low-κ implementation. As a consequence, accurate and effective estimation of the interconnect capacitance is a very challenging task during integration and unit process development. This paper attempts to integrate the impacts of the technological innovations and presents a new compact capacitance model by modifying one of the existing empirical models. The new model demonstrates good agreement with Raphael simulation and less than 2% delta to the real Si data at 28-nm node. Effects of the transition layer and the low-κ damage layer on capacitance and the impact of terminal capacitance on the coupling capacitance are discussed in detail. View full abstract»

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  • Novel Vertical SOI-Based 1T-DRAM With Trench Body Structure

    Page(s): 1872 - 1877
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    A vertical silicon-on-insulator (VSOI)-based capacitorless 1T-DRAM cell with a trench body structure is proposed. The trench body is added as an additional neutral region under the device channel region through a self-aligned fabrication process in a 300 nm wide VSOI MOSFET that enables the device to separate the hole storage region and sense electron current region without extra area penalty. With the holes stored in the trench body, the floating-body effect occurs and affects the threshold voltage significantly. A Synopsys TCAD software tool is also used to evaluate the device performance for DC and transient analysis. The electrical and transient characteristics confirm how the proposed device with trench body can be used perfectly as a 1T-DRAM application to achieve desirable performance in terms of a larger programming window and longer retention time. View full abstract»

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  • Epitaxial Germanium on SOI Substrate and Its Application of Fabricating High {\rm I}_{\rm ON}/{\rm I}_{\rm OFF} Ratio Ge FinFETs

    Page(s): 1878 - 1883
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    Integrating germanium (Ge) thin film on silicon-on-insulator (SOI) substrate and fabricating Ge fin field-effect transistors (FinFETs) are demonstrated in this paper. Directly grown Ge film on a high-resistivity thin SOI substrate provides a good platform for fabricating advanced Ge devices. The SOI structure could effectively suppress junction leakage; therefore, high ION/IOFF ratio (~5×105, at VD=0.1 V) of the drain current is achieved. Tri-gate structure provides better short-channel control abilities for the Ge FinFETs, and the drain-induced barrier lowering and threshold voltage (VTH) shift can be maintained at the level of ~110 mV/V and ~ 0.1 V, respectively, for Ge n-channel FinFET with Lchannel=120 nm and WFin=40 nm. Multifin Ge FinFET with Lchannel=170 nm and WFin=50 nm is also illustrated. Both N- and P-FinFETs possess high ION/IOFF ratio over 104. Besides, the subthreshold swing could be reduced around 25% after forming gas annealing. View full abstract»

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  • Analysis of the Performance of n-Type FinFETs With Strained SiGe Channel

    Page(s): 1884 - 1891
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    This paper reports a simulation study investigating the drive current of a prototypical SiGe n-type FinFET built on a relaxed SiGe substrate for different values of the Ge content x in the Si(1-x)Gex active layer. To this purpose, we performed strain simulations, band-structure calculations, and multisubband Monte Carlo transport simulations accounting for the effects of the Ge content on both the band-structure and the scattering rates in the transistor channel. Our results suggest that the largest on-current may be obtained with a simple Si active layer, because of the beneficial strain induced by the SiGe substrate. A SiGe channel instead is less performing because of strain relaxation and alloy scattering. View full abstract»

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  • Half-MOS Single-Poly EEPROM Cell in Standard CMOS Process

    Page(s): 1892 - 1897
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    A novel multiple-time programmable (MTP) single-poly EEPROM cell based on a half-MOS device is presented. The proposed cell is fabricated in a standard complementary metal-oxide-semiconductor (CMOS) process without any additional mask or process step. It is based on a novel approach, which provides many advantages with respect to the state-of-the-art standard MTP cells, in terms of area, program/erase performance, and endurance. A test-chip is fabricated in a standard 0.13 μm CMOS process and extensive experimental results are provided. View full abstract»

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  • Thermometry of AlGaN/GaN HEMTs Using Multispectral Raman Features

    Page(s): 1898 - 1904
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    In this paper, we utilize micro-Raman spectroscopy to measure temperature and stress in state-of-the-art AlGaN/GaN HEMTs. A rigorous discussion on the physical accuracy, precision, and precautions for diverse Raman thermometry methods is developed. Thermometry techniques utilizing shifts in a single Raman Stokes peak position underpredict the channel temperature due to induction of operational thermoelastic stress in operating devices. Utilizing the change in phonon linewidth by employing a proper reference condition gives true temperature results. Making use of frequency shifts in both the E2(high) and A1(LO) phonon modes offers accurate and time-efficient means to determine the state of temperature and thermal stress in operating AlGaN/GaN HEMTs presuming that linear relations between phonon frequencies and temperature/stress are well determined. Useful applications of this method such as monitoring stress in GaN wafers between fabrication steps and Raman thermography on AlGaN/GaN HEMTs are demonstrated. View full abstract»

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  • Field-Emission and Photoelectrical Characteristics of Ga–ZnO Nanorods Photodetector

    Page(s): 1905 - 1910
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    In this paper, vertically aligned Ga-doped ZnO nanorods are grown on glass substrate by a low-temperature process, hydrothermal method. The Ga-doped ZnO nanorods are needlelike in shape. The field-emission performance can be enhanced by Ga dopant and needlelike in shape. It is found that the turn-on electrical field is reduced from 3.63 to 3.15 V/μm and the field enhancement factor is enhanced from 9058 to 13529 by ultraviolet (UV) illumination. Under UV illumination, the Ga-ZnO nanorods photodetectors exhibit a high UV photocurrent fast rise time, and high UV-to-visible ratio. View full abstract»

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  • Influence of Dopants on the Thermal Conductance of GaN–Sapphire Interface

    Page(s): 1911 - 1915
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    Transient thermoreflectance (TTR) was used to characterize the interface thermal conductance (h) between GaN and sapphire at room temperature. Undoped, n-type, and p-type GaN films are grown by metal-organic chemical vapor deposition (MOCVD) on (0001) sapphire substrate. An In film pressed onto the GaN surface is used as a transducer and to measure the TTR signal. The TTR signal is also used to characterize the attenuation of acoustic waves and the surface roughness of the sapphire wafer. Results are modeled using 1-D heat conduction, and the value of h is determined. Results indicate that the value of h of the In-GaN interface remains between 18 and 28 MWm-2K-1. The value of h for the interface between undoped or n-type GaN and sapphire is low at 8 MWm-2K-1, and that between p-type GaN and sapphire is lower at 3 MWm-2K-1. The absence of good atomic level contact between pressed In and GaN is considered responsible for the low value of h. High concentration of Mg dopant atoms in the p-type GaN films at the interface, sapphire wafer with rough surface, and high dislocation density are also considered responsible for the lower value of h. The results indicate poor thermal energy dissipation, higher device temperature, reduced transconductance, and related device performance. View full abstract»

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  • Low-Interface-Trap-Density and High-Breakdown-Electric-Field SiN Films on GaN Formed by Plasma Pretreatment Using Microwave-Excited Plasma-Enhanced Chemical Vapor Deposition

    Page(s): 1916 - 1922
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    We investigated the SiN/GaN interface properties formed by the microwave-excited plasma-enhanced chemical vapor deposition (PECVD) with SiH4/N2/H2 gases. The interface and insulating properties of SiN films on GaN, formed by the microwave-excited PECVD, strongly depend on SiH4 flow rate. Although the interface trap density is lower than 1011 cm-2 eV-1 at the relatively high SiH4 flow rate of 1.0 standard cm3/min (sccm), the breakdown electric field is very low (approximately 1 MV/cm). Using the SiH4 plasma pretreatment before the stoichiometric SiN deposition, both low interface trap density and high breakdown voltage greater than 2 MV/cm were obtained. In this case, the clearly ordered Ga bonding near the SiN/GaN interface was estimated by electron energy loss spectroscopy. The formation of SiN film on GaN using the microwave-excited PECVD is a very useful technique for the high-quality interface properties. View full abstract»

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  • Characterization and Modeling of 4H-SiC Lateral MOSFETs for Integrated Circuit Design

    Page(s): 1923 - 1930
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    A new process in 4H-SiC is developed that features n-type buried and inversion channel lateral MOSFETs that are fabricated with several different channel lengths (2-8 μm) and widths (8-32 μm ) and characterized over a wide temperature range (25°C-225°C). It is shown that the on-resistance of enhancement-mode SiC MOSFETs reduces with temperature despite a reduction in inversion mobility because of the interaction of interface states with temperature. To enable integrated circuit development using the developed MOSFETs, their electrical characteristics are modeled over geometry and temperature using the industry standard PSP MOSFET model. A new mathematical formulation to describe the presence of the interface states is also developed and implemented in the PSP model, and excellent agreement is shown between measurement and simulation using the modified PSP model. View full abstract»

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  • Thermal Parameter Extraction Method for Light-Emitting Diode (LED) Systems

    Page(s): 1931 - 1937
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    This paper proposes a thermal parameter extraction method for light-emitting diode (LED) devices and LED systems (LEDs mounted on a heatsink). The proposed method provides a simple tool to find out the essential thermal parameters involved in the LED systems, including thermal resistance of LEDs, thermal capacitance of LEDs and thermal time constant of LEDs. All of these thermal parameters are essential for both reliability research and optimal design of LEDs. The concept and significance of the Tau (thermal time constant) of LEDs are emphasized in this paper. Heat transfer equations are initially used for LED devices and LED systems to predict the rising-up junction temperature and cooling-down junction temperature of the LED device and the LED system. Experiments on several LEDs and heatsinks at different time frames are conducted and the practical measurements confirmed the validity of this method and accuracy of the predicted thermal parameters of LEDs. View full abstract»

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  • Thermal Modeling of Resistive Switching Devices

    Page(s): 1938 - 1943
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    A Fourier series-based model is developed for the problem of heat conduction in a geometry composed of an insulator between two metallic electrodes, with multiple cuboidal heat sources within the insulator. This forms a useful thermal model of a resistive switching device with one or more conductive filaments serving as elements of state. Such a device in is the ON state if and only if a filament nearly or fully bridges the gap between the two electrodes, and is in the OFF state otherwise. The results of the model are compared with the finite element method simulations. By reducing the simulation time for the thermal part of the problem, coupled thermal-ionic-electronic simulations are made more computationally efficient, which helps accelerate device optimization by exploring the parameter space more rapidly. View full abstract»

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  • Ferroelectric-Assisted Dual-Switching Speed DRAM–Flash Hybrid Memory

    Page(s): 1944 - 1950
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    This paper presents a novel one-transistor low-voltage DRAM-Flash hybrid memory. The proposed device integrates ferroelectric thin film and nonvolatile charge injection, and demonstrates two modes of operations: 1) a fast (10-100 ns) DRAM mode with ~ 103 s of retention, associated with ferroelectric switching, and 2) a slower (0.1-1 ms) Flash mode with long retention time, from charge tunneling into the floating nodes. The time evolution of the electric field in the ferroelectric and the tunnel oxide is shown to naturally establish the two-step mechanism during the program operation. The complementary characteristics of ferroelectric switching and gate-charge injection enable low-voltage program/erase (±8 V), reasonable memory window (0.8 V), and long retention time. Devices were fabricated with the lead zirconatetitanate thin film as the ferroelectric layer and Au nanocrystals for gate-injected electron storage. Pulsed programming measurements were also performed to distinguish the memory window obtained from the two mechanisms in DRAM and Flash operations. View full abstract»

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  • Transparent Junctionless Electric-Double-Layer Transistors Gated by a Reinforced Chitosan-Based Biopolymer Electrolyte

    Page(s): 1951 - 1957
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    Transparent junctionless organic-inorganic hybrid electric-double-layer thin-film transistors are demonstrated using a reinforced solution-processed chitosan-based biopolymer electrolyte as a dielectric layer. The specific feature of such device is that the channel and source/drain electrodes are realized using a thin indium tin oxide (ITO) film without any source/drain junction. A SiO2 film (~5 nm)/chitosan organic-inorganic hybrid bilayer dielectric is found to be an efficient way to improve the stability and performance of the devices. Our results indicate that the transistor gated by organic-inorganic hybrid bilayer dielectric with a thin ITO channel (~10 nm) exhibited a better performance with a lower subthreshold swing (84 mV/dec), a larger ON/OFF ratio (5.5×107), and a smaller bias-stressing threshold voltage shift (ΔVth=0.13 V) . A physical model based on energy diagram with 1-D Poisson equation is proposed to interpret the operating mechanism. These results clearly show that the proposed architecture can provide a new opportunity for the next-generation low-voltage low-cost device design. View full abstract»

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Aims & Scope

IEEE Transactions on Electron Devices publishes original and significant contributions relating to the theory, modeling, design, performance and reliability of electron and ion integrated circuit devices and interconnects.

 

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Editor-in-Chief
John D. Cressler
School of Electrical and Computer Engineering
Georgia Institute of Technology