# IEEE Transactions on Circuits and Systems II: Express Briefs

## Filter Results

Displaying Results 1 - 16 of 16
• ### Table of contents

Publication Year: 2013, Page(s): C1
| |PDF (36 KB)
• ### IEEE Transactions on Circuits and Systems—II: Express Briefs publication information

Publication Year: 2013, Page(s): C2
| |PDF (135 KB)
• ### A 130-nm CMOS 0.007-$hbox{mm}^{2}$ Ring-Oscillator-Based Self-Calibrating IR-UWB Transmitter Using an Asynchronous Logic Duty-Cycled PLL

Publication Year: 2013, Page(s):237 - 241
Cited by:  Papers (7)
| |PDF (1536 KB) | HTML

We present a 0.007 mm2 impulse-radio ultrawideband transmitter (TX) based on a ring oscillator capable of synthesizing pulses with both controlled center frequency and bandwidth using a single duty-cycling/trigger reference input. The TX embeds a single-phase charge-pump phase-locked loop (PLL), implemented with asynchronous logic, with 55 logic elements overall. The system, including r... View full abstract»

• ### Wideband SAW-Less Receiver Front-End With Harmonic Rejection Mixer in 65-nm CMOS

Publication Year: 2013, Page(s):242 - 246
Cited by:  Papers (10)
| |PDF (274 KB) | HTML

A wideband direct-conversion receiver front-end featuring a new harmonic rejection technique is demonstrated in 65-nm CMOS. The circuit consists of a two-stage low-noise amplifier, the first stage with capacitive feedback, a harmonic rejection mixer using 25% and 50% duty cycle local oscillator signals, and a third-order channel-select filter with configurable bandwidth. The receiver front-end is ... View full abstract»

• ### Designing Harmonic-Controlled Drivers for Switching Power Amplifiers

Publication Year: 2013, Page(s):247 - 251
Cited by:  Papers (2)
| |PDF (694 KB) | HTML

A driver for a switching power amplifier is designed by an iterative least squares method. With only one stub and two lines in each input and output matching network, amplitude and phase responses up to ninth-order harmonic frequencies have been controlled. The designed amplifier is built, and the method is verified with measurements. View full abstract»

• ### 4-Gb/s Parallel Receivers With Adaptive Far-End Crosstalk Cancellation

Publication Year: 2013, Page(s):252 - 256
Cited by:  Papers (1)
| |PDF (829 KB) | HTML

Two 4-Gb/s parallel receivers with adaptive far-end crosstalk (FEXT) cancellation are presented. By using the highpass filter, the crosstalk cancellation (XTC) signal is generated to compensate the FEXT signal. A power detection loop is adopted to achieve automatic tuning of the XTC coefficient for different channel spacing. The receivers with adaptive XTC are fabricated in 40-nm CMOS technology, ... View full abstract»

• ### Capacitor-Coupled Built-Off Self-Test in Analog and Mixed-Signal Embedded Systems

Publication Year: 2013, Page(s):257 - 261
Cited by:  Papers (5)
| |PDF (747 KB) | HTML

Design-for-test (DfT) circuitry that employs differential terminals inherently suffers from an imbalance in the output of its differential pair. By providing the imbalanced differential test stimulus from the DfT circuitry, nonlinearity is eventually introduced in a differential mixed-signal circuit under test, resulting in low test accuracy and significant yield loss during production testing. Co... View full abstract»

• ### Unique Measurement and Modeling of Total Phase Noise in RF Receiver

Publication Year: 2013, Page(s):262 - 266
Cited by:  Papers (2)
| |PDF (534 KB) | HTML

Radio frequency (RF) receivers are common in many modern communications and radar systems, and they suffer from many performance degradation factors due to hardware limitations. Among all performance degradation contributors, phase noise and time jitter are particularly troublesome since they cause random errors which are difficult to compensate. The local oscillator in the receiver front end is a... View full abstract»

• ### Direct Synthesis Technique for Dual-Passband Filters: Superposition Approach

Publication Year: 2013, Page(s):267 - 271
Cited by:  Papers (8)
| |PDF (117 KB) | HTML

In this brief, a technique is proposed for the synthesis of dual-passband filters. Different from conventional techniques based on low-pass prototype, the technique in this brief can directly synthesize filters in bandpass form. Each passband of the filters can be accurately and separately designed, and then, their characteristic functions are superposed to obtain the final characteristic function... View full abstract»

• ### VLSI Implementation of a High-Throughput Iterative Fixed-Complexity Sphere Decoder

Publication Year: 2013, Page(s):272 - 276
Cited by:  Papers (16)
| |PDF (869 KB) | HTML

By exchanging soft information between the multiple-input multiple-output (MIMO) detector and the channel decoder, an iterative receiver can significantly improve the performance compared to the noniterative receiver. In this brief, a soft-input soft-output fixed-complexity-sphere-decoding algorithm and its very large scale integration architecture are proposed for the iterative MIMO receiver. The... View full abstract»

• ### Scaling, Offset, and Balancing Techniques in FFT-Based BP Nonbinary LDPC Decoders

Publication Year: 2013, Page(s):277 - 281
Cited by:  Papers (2)
| |PDF (1085 KB) | HTML

An analysis of finite precision effects in nonbinary mixed-domain low-density parity-check decoders is presented. It is shown how improved decoding performance can be achieved by using an offset-based method and proper scaling techniques. In addition, a novel fast Fourier transform (FFT)-based belief propagation (BP) decoder architecture is proposed which balances the computational load between pr... View full abstract»

• ### A Novel VLSI DHT Algorithm for a Highly Modular and Parallel Architecture

Publication Year: 2013, Page(s):282 - 286
Cited by:  Papers (5)
| |PDF (356 KB) | HTML

A new very large scale integration (VLSI) algorithm for a 2N-length discrete Hartley transform (DHT) that can be efficiently implemented on a highly modular and parallel VLSI architecture having a regular structure is presented. The DHT algorithm can be efficiently split on several parallel parts that can be executed concurrently. Moreover, the proposed algorithm is well suited for the sube... View full abstract»

• ### Low-Cost FIR Filter Designs Based on Faithfully Rounded Truncated Multiple Constant Multiplication/Accumulation

Publication Year: 2013, Page(s):287 - 291
Cited by:  Papers (14)
| |PDF (582 KB) | HTML

Low-cost finite impulse response (FIR) designs are presented using the concept of faithfully rounded truncated multipliers. We jointly consider the optimization of bit width and hardware resources without sacrificing the frequency response and output signal precision. Nonuniform coefficient quantization with proper filter order is proposed to minimize total area cost. Multiple constant multiplicat... View full abstract»

• ### Synchronization of Complex Networks With Impulsive Control and Disconnected Topology

Publication Year: 2013, Page(s):292 - 296
Cited by:  Papers (23)
| |PDF (224 KB) | HTML

Synchronization of complex networks is an important issue in the study of complex networks. Many existing works reveal that complex networks can reach synchronization under the condition of connected topology; however, by introducing the concept of joint connectivity and sequential connectivity, this brief shows us that complex networks can synchronize even if the topology is not connected at any ... View full abstract»

• ### IEEE Circuits and Systems Society Information

Publication Year: 2013, Page(s): C3
| |PDF (117 KB)
• ### IEEE Transactions on Circuits and Systems - II: Express Briefs information for authors

Publication Year: 2013, Page(s): C4
| |PDF (108 KB)

## Aims & Scope

Part I will now contain regular papers focusing on all matters related to fundamental theory, applications, analog and digital signal processing. Part II will report on the latest significant results across all of these topic areas.

Full Aims & Scope

## Meet Our Editors

Editor-in-Chief

Chi K. Michael Tse
Dept. of Electronic and Information Engineering
Hong Kong Polytechnic University
Hunghom, Hong Kong
cktse@ieee.org