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Solid-State Circuits, IEEE Journal of

Issue 5 • Date May 2013

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Displaying Results 1 - 24 of 24
  • Table of contents

    Page(s): C1 - C4
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  • IEEE Journal of Solid-State Circuits publication information

    Page(s): C2
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  • Table of contents

    Page(s): 1109 - 1110
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  • Overview for the Special Section on the 2012 Radio Frequency Integrated Circuits (RFIC) Symposium

    Page(s): 1111 - 1112
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  • A 70–100 GHz Direct-Conversion Transmitter and Receiver Phased Array Chipset Demonstrating 10 Gb/s Wireless Link

    Page(s): 1113 - 1125
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    A transmitter and receiver phased array chipset is demonstrated in the range between 70 and 100 GHz using a 0.18 µm SiGe BiCMOS process with $f_{T}/f_{MAX}$ of 240/270 GHz. Each chip comprises four phased array elements with distributed calibration memory and calibrated direct up- and down-conversion mixer chain. Each receive channel has a conversion gain of 33 dB and noise figure of < 7 dB from 75–95 GHz. Each transmit channel has a flat saturated output power of > 5 dBm between 70 and 100 GHz. Both transmitter and receiver arrays operate from 1.5 V and 2.5 V power supplies and consume 1 W each. Using a die-on-PCB prototype with integrated antennas, a wireless link operating at 10 Gb/s (using 16-QAM) or 8.75 Gb/s (using 32-QAM) is demonstrated at a distance of 1-meter with a carrier frequency of 88 GHz. View full abstract»

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  • A 2-Bit, 24 dBm, Millimeter-Wave SOI CMOS Power-DAC Cell for Watt-Level High-Efficiency, Fully Digital m-ary QAM Transmitters

    Page(s): 1126 - 1137
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    A high-efficiency, large output-power, mm-wave digital transmitter architecture is proposed for high data rate m-ary QAM transmission. Because it operates entirely in digital mode, without any matching networks, it is scalable in frequency up to at least 50 GHz and portable to future generations of CMOS technologies. It consists of n broadband mm-wave IQ power-DAC pairs directly modulated in amplitude and phase by 4 x n independent digital data streams. The output signals combine in free space to form a programmable ASK, BPSK, QPSK, and m-ary QAM mm-wave transmitter. Several proof-of-concept circuits with one DAC cell, and with one and two IQ pairs of DAC cells were fabricated in 45-nm SOI CMOS. Using a series-stacked differential output stage with four cascoded n-MOSFETs driven in saturation by a CMOS-inverter chain, each power-DAC cell demonstrates a 24.3 dBm output power with 21.3% drain efficiency and 14.6% PAE, at 45 GHz directly into 50-Ω loads. The peak drain efficiency is 30% at 22.5 dBm output power and 19.4% PAE. Experiments show 5-Gb/s BPSK, and simultaneous 2-Gb/s BPSK and 2-Gb/s ASK modulation per DAC cell in the 44-48 GHz range. Eye diagrams at 28 Gb/s further demonstrate the broadband operation of the DAC cell and its suitability as a large-swing NRZ modulator driver in fiberoptic links. View full abstract»

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  • A linearized, low-phase-noise VCO-based 25-GHz PLL with autonomic biasing

    Page(s): 1138 - 1150
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    This paper describes a new approach to low-phasenoise LC VCO design based on transconductance linearization of the active devices. A prototype 25 GHz VCO based on this linearization approach is integrated in a dual-path PLL and achieves superior performance compared to the state of the art. The design is implemented in 32 nm SOI CMOS technology and achieves a phase noise of - 130 dBc/Hz at a 10 MHz offset from a 22 GHz carrier. Additionally, the paper introduces a new layout approach for switched capacitor arrays that enables a wide tuning range of 23%. More than 1500 measurements of the PLL across PVT variations were taken, further validating the proposed design. Phase noise variation across 55 dies for four different frequencies is σ < 0.6 dB. Also, phase noise variation across supply voltages of 0.7-1.5 V is 2 dB and across 60 °C temperature variation is 3 dB. At the 25 GHz center frequency, the VCO FOMT is 188 dBc/Hz. Additionally, a digitally assisted autonomic biasing technique is implemented in the PLL to provide a phase noise and power optimized VCO bias across frequency and process. Measurement results indicate the efficacy of the autonomic biasing scheme. View full abstract»

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  • A 90-nm CMOS 5-GHz Ring-Oscillator PLL With Delay-Discriminator-Based Active Phase-Noise Cancellation

    Page(s): 1151 - 1160
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    Ring oscillators (ROs) provide a low-cost digital VCO solution in fully integrated PLLs. However, due to their supply noise sensitivity and high noise floor, their applications have been limited to low-performance applications. The proposed architecture introduces an analog feed-forward adaptive phase-noise cancellation architecture that extracts and suppresses phase noise of ROs outside the PLL bandwidth. The proposed technique can improve the phase noise at an arbitrary offset frequency and bandwidth, and, after initial calibration for gain, it is insensitive to process, voltage, and temperature variations. An experimental fractional PLL, with a loop bandwidth of 200 kHz, is utilized to demonstrate the active phase-noise cancellation approach. The cancellation loop is designed to suppress the phase noise at 1-MHz offset by 12.5 dB and reference spur by 13 dB with less than 17% increase in the overall power consumption at 5.1-GHz frequency. The measured phase noise at 1-MHz offset after cancellation is -105 dBc/Hz. The proposed RO-PLL is fabricated in 90-nm CMOS process. With noise cancellation loop enabled, the PLL consumes 24.7 mA at 1.2-V supply. View full abstract»

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  • A 65-nm GSM/GPRS/EDGE SoC With Integrated BT/FM

    Page(s): 1161 - 1173
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    A quad-band GSM/GPRS/EDGE cellular system, implemented in 65-nm CMOS, is integrated in a multimedia SoC with BT and FM. A low-IF receiver with digital IRR tracking is selected for its smaller area and better noise figure. The receiver achieves a sensitivity of $-$ 110 dBm, an IIP3 of $-$ 9.5 dBm, and a calibrated image rejection ratio of 65 dBc, while consuming 61 mA. The polar transmitter architecture is chosen for its SAW-less TX capability, smaller area, and low current consumption. It achieves an ORFS (output radio frequency spectrum) of $-$68 dB and $-$64 dB at 400 kHz in GMSK and EDGE mode, respectively, while consuming 61 mA. The loop gain normalization, dc offset and AM/PM delay of the polar system are compensated to be better than 1% error, 1 mV, and 1.9 ns within 170 $mu$s, respectively. Several techniques are employed to minimize interference coupling within the SoC; these include frequency planning, circuit implementation, transceiver architecture optimization, and digital clock selection. The measured sensitivity and the output spectrum of the three wireless systems under full-feature phone operation are virtually unchanged. View full abstract»

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  • A Multiband Mobile Analog TV Tuner SoC With 78-dB Harmonic Rejection and GSM Blocker Detection in 65-nm CMOS

    Page(s): 1174 - 1187
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    A 48–885–MHz ultralow-cost high-performance mobile analog TV (MATV) tuner with an improved harmonic rejection design algorithm achieves 5.5 dB/4.5 dB noise figure at VHF and UHF bands, respectively, and adjacent channel interference (ACI) ${rm N}+1/{rm N}+2$ performance of 24/29 dB. A harmonic rejection mixer (HRM) with a tracking filter (TF) scheme employing three external inductors, one for each TV band, achieves better than 78/83-dB harmonic-rejection for the VHFI/VHFIII bands. A single LC-tank VCO with a programmable divider that has a 50% duty cycle correction scheme covers the entire TV band with accurate LO phases. A digital automatic gain control (AGC) scheme detects the presence of ACI and/or GSM burst-mode blockers through an RF wideband peak detector (WBPD) and adjusts the receiver gain for optimum dynamic range. The RF tuner is fabricated in 65-nm CMOS technology with silicon area of only 1.25 $hbox{mm}^{2}$ and draws 37/19 mA for analog TV and FM radio receiver modes, respectively. View full abstract»

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  • A Wideband Receiver With Resonant Multi-Phase LO and Current Reuse Harmonic Rejection Baseband

    Page(s): 1188 - 1198
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    In this work we present an architecture for a low power SDR which draws on techniques from both narrowband low power radios and recent work in SDRs. The receiver consists of a wide tuning-range passive mixer, driven with resonant non-overlapping LO drive combined with a noise-power optimized multi-path baseband amplifier. LO generation circuitry drives the mixer with an 8-phase, 12.5% duty cycle LO, but does so directly from complementary LC-tank VCOs in order to resonate out the gate capacitance of the mixer. A capacitor sharing technique on the baseband side of the mixer doubles the RX frequency range of the 8-phase clock at no added cost in power or performance, while achieving a NF as low as 7 dB. The 1.8 mW low noise baseband amplifier reuses the bias current of its four input channels while rejecting the 3rd/5th harmonics by >34 dB. The receiver consumes 10–12 mW (including VCOs, pulse generation and baseband) over a frequency range of 0.7–3.2 GHz with a 1.3 V supply. View full abstract»

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  • Analysis and Design of a 5 GS/s Analog Charge-Domain FFT for an SDR Front-End in 65 nm CMOS

    Page(s): 1199 - 1211
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    This work describes the design of a 16 point analog domain FFT using a Charge Re-use Analog Fourier Transform (CRAFT) engine. The circuit relies on charge re-use to achieve 47 dB average output SNDR on an instantaneous input bandwidth of 5 GHz, and consumes only 3.8 mW (12.2 pJ/conv.). The CRAFT engine is used as a wide-band, low power RF front-end channelizer for software defined radio (SDR) applications. The paper also discusses the handling of circuit non-idealities for the CRAFT design: their significance, modeling, and circuit techniques for their mitigation. These techniques enable this implementation to achieve a large dynamic range even at high speeds. View full abstract»

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  • A Class-G Switched-Capacitor RF Power Amplifier

    Page(s): 1212 - 1224
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    A switched-capacitor power amplifier (SCPA) that realizes an envelope elimination and restoration/polar class-G topology is introduced. A novel voltage-tolerant switch enables the use of two power supply voltages which increases efficiency and output power simultaneously. Envelope digital-to-analog conversion in the polar transmitter is achieved using an SC RF DAC that exhibits high efficiency at typical output power backoff levels. In addition, high linearity is achieved and no digital predistortion is required. Implemented in 65 nm CMOS, the measured peak output power and power-added efficiency (PAE) are 24.3 dBm and 43.5%, respectively, whereas when amplifying 802.11g 64-QAM OFDM signals, the average output power and PAE are 16.8 dBm and 33%, respectively. The measured EVM is 2.9%. View full abstract»

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  • A Fully Integrated, Regulatorless CMOS Power Amplifier for Long-Range Wireless Sensor Communication

    Page(s): 1225 - 1236
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    This paper presents a CMOS power amplifier (PA) system designed with the explicit goal of customizing a high-output power transmitter for sensor applications, where the supply voltage from an energy storage element is often time varying. The PA is intended for use in a long-range sensor transceiver and can operate directly off a super-capacitor source. A constant output-power, regulatorless, series power-combined PA with a fully integrated tunable matching network is implemented in an attempt to eliminate all energy losses associated with a high-current voltage regulator. The PA monitors the output voltage at the off-chip antenna and digitally modulates the PA load impedance to maintain a constant target output power as the super-capacitor discharges. The PA system, integrated in a 90-nm CMOS process, has a peak output power of 24 dBm with an efficiency of 12% at 1.8 GHz, making it suitable for sensor data communication over distances of several hundred meters. As the PA supply varies from 2.5 to 1.5 V, the power control loop maintains a constant output power with an accuracy of $pm$ 0.8 dB. View full abstract»

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  • Post-Si Programmable ESD Protection Circuit Design: Mechanisms and Analysis

    Page(s): 1237 - 1249
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    This paper reports new mechanisms, design, and analysis of novel electrostatic discharge (ESD) protection solutions, which enable post-Si field-programmable ESD protection circuit design for the first time. Two new ESD protection concepts, nano-crystal quantum-dot (NC-QD) and silicon–oxide–nitride–oxide–silicon (SONOS)-based ESD protection, are presented. Experiments validated the two new programmable ESD protection mechanisms. Prototype designs demonstrated a wide adjustable ESD triggering voltage $({V}_{{t}1})$ range of $Delta{V}_{{t}1}sim hbox{ 2 V}$, very fast response $({t}_{1})$ to ESD transients of rising time ${t}_{r}sim hbox{ 100 pS}$ and pulse duration ${t}_{d}sim hbox{ 1 nS}$, ESD protection capability $({I}_{{t}2})$ of at least 25 $hbox{mA}/muhbox{m}$ for human body model (HBM) and 400 $hbox{mA}/muhbox{m}$ for charged device model (CDM) equivalent stressing, and very low leakage current $({I}_{rm leak})$ as low as 1.2 pA. Field-programmable ESD protection circuit design examples are discussed. View full abstract»

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  • A 2.4 GHz Hybrid Polyphase Filter Based BFSK Receiver With High Frequency Offset Tolerance for Wireless Sensor Networks

    Page(s): 1250 - 1263
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    A low power 2.4 GHz hybrid polyphase filter (PPF) based BFSK receiver with high frequency offset tolerance (FOT) at small modulation indexes (MIs) is presented for medium data rate wireless sensor network applications. A high FOT at low MI is achieved by a frequency-to-energy conversion architecture using PPFs without any frequency correction circuits. Channel selection and interference rejection are performed simultaneously by the PPFs without any extra hardware and power consumption. Furthermore, the proposed hybrid topology of the PPFs provides an improved adjacent channel rejection (ACR) at reduced power. The prototype receiver fabricated in a 0.13-µm CMOS process, including the RF and analog front-ends, consumes 1.97 mW from a 1 V supply. With a data rate of 1 Mb/s, a sensitivity of –84 dBm, a FOT of ${pm} $450 kHz (${pm} $180 ppm), and an ACR of 40 dB are achieved for a MI of 2. View full abstract»

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  • A Low-Power 26-GHz Transformer-Based Regulated Cascode SiGe BiCMOS Transimpedance Amplifier

    Page(s): 1264 - 1275
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    Low-power high-speed optical receivers are required to meet the explosive growth in data communication systems. This paper presents a 26 GHz transimpedance amplifier (TIA) that employs a transformer-based regulated cascode (RGC) input stage which provides passive negative-feedback gain that enhances the effective transconductance of the TIA's input common-base transistor; reducing the input resistance and isolating the parasitic photodiode capacitance. This allows for considerable bandwidth extension without significant noise degradation or power consumption. Further bandwidth extension is achieved through series inductive peaking to isolate the photodetector capacitance from the TIA input. The optimum choice of series inductive peaking value and key transformer parameters for bandwidth extension and jitter minimization is analyzed. Fabricated in a 0.25-µm SiGe BiCMOS technology and tested with an on-chip 150 fF capacitor to emulate a photodiode, the TIA achieves a 53 dBΩ single-ended transimpedance gain with a 26 GHz bandwidth and 21.3 pA/$sqrt{rm Hz}$ average input-referred noise current spectral density. Total chip power including output buffering is 28.2 mW from a 2.5 V supply, with the core TIA consuming 8.2 mW, and the chip area including pads is 960 µm x 780 µm. View full abstract»

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  • A 0.47–0.66 pJ/bit, 4.8–8 Gb/s I/O Transceiver in 65 nm CMOS

    Page(s): 1276 - 1289
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    A low-power forwarded-clock I/O transceiver architecture is presented that employs a high degree of output/input multiplexing, supply-voltage scaling with data rate, and low-voltage circuit techniques to enable low-power operation. The transmitter utilizes a 4:1 output multiplexing voltage-mode driver along with 4-phase clocking that is efficiently generated from a passive poly-phase filter. The output driver voltage swing is accurately controlled from 100–200 ${rm mV}_{rm ppd}$ using a low-voltage pseudo-differential regulator that employs a partial negative-resistance load for improved low frequency gain. 1:8 input de-multiplexing is performed at the receiver equalizer output with 8 parallel input samplers clocked from an 8-phase injection-locked oscillator that provides more than 1UI de-skew range. In the transmitter clocking circuitry, per-phase duty-cycle and phase-spacing adjustment is implemented to allow adequate timing margins at low operating voltages. Fabricated in a general purpose 65 nm CMOS process, the transceiver achieves 4.8–8 Gb/s at 0.47–0.66 pJ/b energy efficiency for ${rm V}_{rm DD}=0.6$–0.8 V. View full abstract»

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  • A 256 Pixel Magnetoresistive Biosensor Microarray in 0.18 µm CMOS

    Page(s): 1290 - 1301
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    Magnetic nanotechnologies have shown significant potential in several areas of nanomedicine such as imaging, therapeutics, and early disease detection. Giant magnetoresistive spin-valve (GMR SV) sensors coupled with magnetic nanotags (MNTs) possess great promise as ultra-sensitive biosensors for diagnostics. We report an integrated sensor interface for an array of 256 GMR SV biosensors designed in 0.18 µm CMOS. Arranged like an imager, each of the 16 column level readout channels contains an analog front-end and a compact ΣΔ modulator (0.054 mm$^{2}$ ) with 84 dB of dynamic range and an input referred noise of 49 nT/$surd$Hz. Performance is demonstrated through detection of an ovarian cancer biomarker, secretory leukocyte peptidase inhibitor (SLPI), spiked at concentrations as low as 10 fM. This system is designed as a replacement for optical protein microarrays while also providing real-time kinetics monitoring. View full abstract»

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  • A Logic-Compatible Embedded Flash Memory for Zero-Standby Power System-on-Chips Featuring a Multi-Story High Voltage Switch and a Selective Refresh Scheme

    Page(s): 1302 - 1314
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    Embedded flash memory implemented using standard I/O devices can open doors to new applications and system capabilities, as it can serve as a secure on-chip non-volatile storage for VLSI chips built in standard logic processes. For example, it is indispensable for adaptive self-healing techniques targeted for mitigating process variation and circuit aging related issues where system information must be retained during power down periods. Embedded non-volatile memory can also enable zero-standby power systems by allowing them to completely power down without losing critical data. There has been numerous device and circuit level research on high-density non-volatile memories such as flash, STT-MRAM, PRAM, and RRAM. However, only few attempts have been made to develop a cost effective moderate-density non-volatile solution using standard I/O devices. In this paper, a logic-compatible embedded flash memory that uses no special devices other than standard core and I/O transistors is demonstrated in a generic logic process having a 5 nm tunnel oxide. An overstress-free high voltage switch and a selective WL refresh scheme are employed for improved cell threshold voltage window and higher endurance cycles. View full abstract»

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  • A 0.13 µm 8 Mb Logic-Based Cu _{\rm x} Si _{\rm y} O ReRAM With Self-Adaptive Operation for Yield Enhancement and Power Reduction

    Page(s): 1315 - 1322
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    A 0.13 µm 8 Mb ${rm Cu}_{rm x}{rm Si}_{rm y}{rm O}$ resistive random access memory (ReRAM) test macro with $20{rm F}^{2}$ cell size is developed based on logic process for embedded applications. Smart and adaptive write and read assist circuits are proposed to fix yield and power consumption issues arising from large variations in set/reset time and high-temperature cell resistance. Self-adaptive write mode (SAWM) helps increase the ${rm R}_{rm off}/{rm R}_{rm on}$ window from 8X to 24X at room temperature. The reset bit yield is improved from 61.5% to 100% and the high power consumption is eliminated after the cell switches to ${rm R}_{rm on}$ during set. Self-adaptive read mode (SARM) increases read bit yield from 98% to 100% at 125$^{circ}{rm C}$. The typical access time of the on-pitch voltage sense amplifier (SA) is 21 ns. High bandwidth throughput is supported. View full abstract»

    Open Access
  • Call for papers: IEEE Asian Solid-State Circuits Conference

    Page(s): 1323
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  • 2014 IEEE Radio Frequency Integrated Circuits Symposium

    Page(s): 1324
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    Freely Available from IEEE
  • IEEE Journal of Solid-State Circuits information for authors

    Page(s): C3
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Aims & Scope

The IEEE Journal of Solid-State Circuits publishes papers each month in the broad area of solid-state circuits with particular emphasis on transistor-level design of integrated circuits.

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Meet Our Editors

Editor-in-Chief
Michael Flynn
University of Michigan