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# IEEE Transactions on Very Large Scale Integration (VLSI) Systems

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Displaying Results 1 - 22 of 22

Publication Year: 2013, Page(s):C1 - C4
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• ### IEEE Transactions on Very Large Scale Integration (VLSI) Systems publication information

Publication Year: 2013, Page(s): C2
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• ### Design of Ternary Logic Combinational Circuits Based on Quantum Dot Gate FETs

Publication Year: 2013, Page(s):793 - 806
Cited by:  Papers (16)
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In this paper, we discuss logic circuit designs using the circuit model of three-state quantum dot gate field effect transistors (QDGFETs). QDGFETs produce one intermediate state between the two normal stable ON and OFF states due to a change in the threshold voltage over this range. We have developed a simplified circuit model that accounts for this intermediate state. Interesting logic can be im... View full abstract»

• ### Parametric DFM Solution for Analog Circuits: Electrical-Driven Hotspot Detection, Analysis, and Correction Flow

Publication Year: 2013, Page(s):807 - 820
Cited by:  Papers (4)
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As VLSI technology pushes into advanced nodes, designers and foundries have exposed a hitherto insignificant set of yield problems. To combat yield failures, the semiconductor industry has deployed new tools and methodologies commonly referred to as design for manufacturing (DFM). Most of the early DFM efforts concentrated on catastrophic failures, or physical DFM problems. Recently, there has bee... View full abstract»

• ### Unified Capture Scheme for Small Delay Defect Detection and Aging Prediction

Publication Year: 2013, Page(s):821 - 833
Cited by:  Papers (4)
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Small delay defect (SDD) and aging-induced circuit failure are both prominent reliability concerns for nanoscale integrated circuits. Faster-than-at-speed testing is effective on SDD detection in manufacturing testing, which is always implemented by designing a suite of test signal generation circuits on the chip. Meanwhile, the integration of online aging sensors is becoming attractive in monitor... View full abstract»

• ### Novel MIMO Detection Algorithm for High-Order Constellations in the Complex Domain

Publication Year: 2013, Page(s):834 - 847
Cited by:  Papers (29)
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A novel detection algorithm with an efficient VLSI architecture featuring efficient operation over infinite complex lattices is proposed. The proposed design results in the highest throughput, the lowest latency, and the lowest energy compared to the complex-domain VLSI implementations to date. The main innovations are a novel complex-domain means of expanding/visiting the intermediate nodes of th... View full abstract»

• ### High-Throughput 0.13-$mu{rm m}$ CMOS Lattice Reduction Core Supporting 880 Mb/s Detection

Publication Year: 2013, Page(s):848 - 861
Cited by:  Papers (12)
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This paper presents the first silicon-proven implementation of a lattice reduction (LR) algorithm, which achieves maximum likelihood diversity. The implementation is based on a novel hardware-optimized due to the Lenstra, Lenstra, and Lovász (LLL) algorithm, which significantly reduces its complexity by replacing all the computationally intensive LLL operations (multiplication, division, a... View full abstract»

• ### Study of Through-Silicon-Via Impact on the 3-D Stacked IC Layout

Publication Year: 2013, Page(s):862 - 874
Cited by:  Papers (19)
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The technology of through-silicon vias (TSVs) enables fine-grained integration of multiple dies into a single 3-D stack. TSVs occupy significant silicon area due to their sheer size, which has a great effect on the quality of 3-D integrated chips (ICs). Whereas well-managed TSVs alleviate routing congestion and reduce wirelength, excessive or ill-managed TSVs increase the die area and wirelength. ... View full abstract»

• ### Design of Hardware Function Evaluators Using Low-Overhead Nonuniform Segmentation With Address Remapping

Publication Year: 2013, Page(s):875 - 886
Cited by:  Papers (4)
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In the piecewise function evaluation with polynomial approximation, nonuniform segmentation can effectively reduce the size of lookup tables for some arithmetic functions compared to uniform segmentation approaches, at the cost of the extra segment address (index) encoder that results in area and delay overhead. Also, it is observed that the nonuniform segmentation reflects a design tradeoff betwe... View full abstract»

• ### Statistical Functional Yield Estimation and Enhancement of CNFET-Based VLSI Circuits

Publication Year: 2013, Page(s):887 - 900
Cited by:  Papers (2)
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Carbon nanotube field effect transistors (CNFETs) show great promise as extensions to silicon CMOS. However, imperfections, which are mainly related to carbon nanotubes (CNTs) growth process, result in metallic and nonuniform CNTs leading to significant functional yield reduction. This paper presents a comprehensive technique for statistical functional yield estimation and enhancement of CNFET-bas... View full abstract»

• ### Theoretical Modeling of Elliptic Curve Scalar Multiplier on LUT-Based FPGAs for Area and Speed

Publication Year: 2013, Page(s):901 - 909
Cited by:  Papers (9)
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This paper uses a theoretical model to approximate the delay of different characteristic two primitives used in an elliptic curve scalar multiplier architecture (ECSMA) implemented on k input lookup table (LUT)-based field-programmable gate arrays. Approximations are used to determine the delay of the critical paths in the ECSMA. This is then used to theoretically estimate the optimal numbe... View full abstract»

• ### Architecture for Real-Time Nonparametric Probability Density Function Estimation

Publication Year: 2013, Page(s):910 - 920
Cited by:  Papers (4)
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Adaptive systems are increasing in importance across a range of application domains. They rely on the ability to respond to environmental conditions, and hence real-time monitoring of statistics is a key enabler for such systems. Probability density function (PDF) estimation has been applied in numerous domains; computational limitations, however, have meant that proxies are often used. Parametric... View full abstract»

• ### 1.2-mW Online Learning Mixed-Mode Intelligent Inference Engine for Low-Power Real-Time Object Recognition Processor

Publication Year: 2013, Page(s):921 - 933
Cited by:  Papers (5)
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Object recognition is computationally intensive and it is challenging to meet 30-f/s real-time processing demands under sub-watt low-power constraints of mobile platforms even for heterogeneous many-core architecture. In this paper, an intelligent inference engine (IIE) is proposed as a hardware controller for a many-core processor to satisfy the requirements of low-power real-time object recognit... View full abstract»

• ### Current-Comparison-Based Domino: New Low-Leakage High-Speed Domino Circuit for Wide Fan-In Gates

Publication Year: 2013, Page(s):934 - 943
Cited by:  Papers (18)
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In this paper, a new domino circuit is proposed, which has a lower leakage and higher noise immunity without dramatic speed degradation for wide fan-in gates. The technique which is utilized in this paper is based on comparison of mirrored current of the pull-up network with its worst case leakage current. The proposed circuit technique decreases the parasitic capacitance on the dynamic node, yiel... View full abstract»

• ### Symbolic Moment Computation for Statistical Analysis of Large Interconnect Networks

Publication Year: 2013, Page(s):944 - 957
Cited by:  Papers (3)
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The shrinking technology feature size and dense large-scale integration make process variation a challenging issue directly confronting the latest design automation tools. Process variation causes severe variation in interconnect networks, including very large-scale integrated interconnect structures, such as clock trees, clock mesh, power-ground networks, and other wiring structures in 3-D integr... View full abstract»

• ### Uncorrelated Power Supply Noise and Ground Bounce Consideration for Test Pattern Generation

Publication Year: 2013, Page(s):958 - 970
Cited by:  Papers (7)
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Power supply noise and ground bounce can cause considerable path delay variations. Capturing the worst case power supply noise at a gate level is not a sufficient indicator for measuring the worst case path delay. Furthermore, path delay variations depend on multiple parameters such as input stimuli, cell placement, switching frequency, and available decoupling capacitors. All these variables obsc... View full abstract»

• ### C-Based Complex Event Processing on Reconfigurable Hardware

Publication Year: 2013, Page(s):971 - 974
Cited by:  Papers (1)
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This brief presents an efficient complex event-processing framework, designed to process a large number of sequential events on field-programmable gate arrays (FPGAs). Unlike conventional structured query language based approaches, our approach features logic automation constructed with a new C-based event language that supports regular expressions on the basis of C functions, so that a wide varie... View full abstract»

• ### Reduced-Complexity LCC Reed–Solomon Decoder Based on Unified Syndrome Computation

Publication Year: 2013, Page(s):974 - 978
Cited by:  Papers (4)
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Reed-Solomon (RS) codes are widely used in digital communication and storage systems. Algebraic soft-decision decoding (ASD) of RS codes can obtain significant coding gain over the hard-decision decoding (HDD). Compared with other ASD algorithms, the low-complexity Chase (LCC) decoding algorithm needs less computation complexity with similar or higher coding gain. Besides employing complicated int... View full abstract»

• ### Subthreshold Dual Mode Logic

Publication Year: 2013, Page(s):979 - 983
Cited by:  Papers (10)
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In this brief, we introduce a novel low-power dual mode logic (DML) family, designed to operate in the subthreshold region. The proposed logic family can be switched between static and dynamic modes of operation according to system requirements. In static mode, the DML gates feature very low-power dissipation with moderate performance, while in dynamic mode they achieve higher performance, albeit ... View full abstract»

• ### Power Network Optimization Based on Link Breaking Methodology

Publication Year: 2013, Page(s):983 - 987
Cited by:  Papers (1)
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A link breaking methodology is introduced to reduce voltage degradation within mesh structured power distribution networks. The resulting power distribution network combines a single power distribution network to lower the network impedance, and multiple networks to reduce noise coupling among the circuits. Since the sensitivity to supply voltage variations within a power distribution network can ... View full abstract»

• ### IEEE Transactions on Very Large Scale Integration (VLSI) Systems information for authors

Publication Year: 2013, Page(s): 988
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• ### IEEE Transactions on Very Large Scale Integration (VLSI) Systems society information

Publication Year: 2013, Page(s): C3
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## Aims & Scope

Design and realization of microelectronic systems using VLSI/ULSI technologies requires close collaboration among scientists and engineers in the fields of systems architecture, logic and circuit design, chips and wafer fabrication, packaging, testing, and systems applications. Generation of specifications, design, and verification must be performed at all abstraction levels, including the system, register-transfer, logic, circuit, transistor, and process levels. To address this critical area through a common forum, the IEEE Transactions on VLSI Systems was founded.

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## Meet Our Editors

Editor-in-Chief

Krishnendu Chakrabarty
Department of Electrical Engineering
Duke University
Durham, NC 27708 USA
Krish@duke.edu