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Selected Topics in Quantum Electronics, IEEE Journal of

Issue 2 • Date March-April 2013

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Displaying Results 1 - 25 of 31
  • Front Cover

    Article#: 0000501
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    Freely Available from IEEE
  • IEEE Journal of Selected Topics in Quantum Electronics publication information

    Article#: 0000601
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  • Table of Contents

    Article#: 0100202
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  • Introduction to the Issue on Optical Interconnects for Data Centers

    Article#: 0200302
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  • Scalable and Distributed Contention Resolution in AWGR-Based Data Center Switches Using RSOA-Based Optical Mutual Exclusion

    Article#: 3600111
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1164 KB) |  | HTML iconHTML  

    We describe a mutual exclusion element using a reflective semiconductor optical amplifier (RSOA) and a simple scheme for contention resolution in arrayed waveguide grating router (AWGR)-based optical switches in data centers. We describe a hardware demonstration and detailed performance analysis of an AWGR-based optical switch based on the proposed concept. We show that the proposed RSOA-based contention resolution significantly reduces latency compared to existing methods and that it does not require any global or centralized coordination, which makes it inherently scalable and suitable for emerging data center networks. View full abstract»

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  • Photonic Crystal Nanobeam Cavities for Tunable Filter and Router Applications

    Article#: 3600210
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    We investigate the suitability of photonic crystal nanobeam cavities for interconnect applications. Owing to their small footprint, exactly the same as that of an optical waveguide, as well as ultrahigh quality factor resonances that they support, nanobeam cavities are attractive candidates for realization of densely integrated on-chip optical networks. We discus tunability of these filters using thermo-optic, electromechanic, and optomechanic effects, and we compare different reconfiguration strategies in terms of tuning hold power, tuning efficiency, and maximum operating frequency. View full abstract»

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  • Fabrication of a Graded-Index Circular-Core Polymer Parallel Optical Waveguide Using a Microdispenser for a High-Density Optical Printed Circuit Board

    Article#: 3600310
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    A simple fabrication method for multimode polymer optical waveguides with graded-index (GI) circular cores is introduced for use in optical printed circuit boards (O-PCBs). The new method, named “Mosquito method,” utilizes a microdispenser to dispense a viscous monomer directly onto the substrates. By optimizing the dispensing conditions, 12-channel parallel waveguides with circular GI-cores (core diameter of 40 μm) are successfully fabricated using the Mosquito method. The advantages of GI-core waveguides for O-PCB applications are discussed by comparing the optical characteristics of the fabricated waveguides with those of conventional step-index (SI) square-core polymer waveguides, and even with those of silica-based GI multimode fibers (MMFs), as an ideal case. To the best of our knowledge, this is the first comparison of SI- and GI-core multimode polymer waveguides that are composed of the same polymer materials and that have similar core and pitch sizes. We experimentally demonstrate that the GI circular-core polymer waveguides fabricated by the Mosquito method have sufficiently low propagation loss (0.033 dB/cm at 850 nm), low connection loss with GI-MMFs, and low interchannel crosstalk. We observe approximately -50 dB of interchannel crosstalk in the 250-μm pitch GI-core waveguide fabricated, which is almost 10 dB lower than in the SI counterpart. Furthermore, sufficiently low crosstalk is maintained in a half-pitch GI-core waveguide fabricated by the Mosquito method. View full abstract»

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  • LIONS: An AWGR-Based Low-Latency Optical Switch for High-Performance Computing and Data Centers

    Article#: 3600409
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    This paper discusses the architecture of an arrayed waveguide grating router (AWGR)-based low-latency interconnect optical network switch called LIONS, and its different loopback buffering schemes. A proof of concept is demonstrated with a 4 × 4 experimental testbed. A simulator was developed to model the LIONS architecture and was validated by comparing experimentally obtained statistics such as average end-to-end latency with the results produced by the simulator. Considering the complexity and cost in implementing loopback buffers in LIONS, we propose an all-optical negative acknowledgement (AO-NACK) architecture in order to remove the need for loopback buffers. Simulation results for LIONS with AO-NACK architecture and distributed loopback buffer architecture are compared with the performance of the flattened butterfly electrical switching network. View full abstract»

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  • Photonic Architectures for High-Performance Data Centers

    Article#: 3700109
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    Over the next decade, significant progress must be made in research on computer architectures that enable unprecedented improvements in the efficiency of large-scale computing systems, particularly to support applications that require exascale algorithmic performance. Here, we review the performance requirements for both high-performance computing systems and data centers, and show that it will be critical to exploit photonic devices for interconnect applications to meet these expectations. In the long term, CMOS-compatible fabrication technologies promise a “Moore's Law for photonics” that could completely change the economics of integrated optics and high-performance computing for defense, security, scientific, and consumer applications. View full abstract»

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  • Designing Energy-Efficient Data Center Networks Using Space-Time Optical Interconnection Architectures

    Article#: 3700209
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    This paper considers a space-time interconnection architecture (STIA) based on optical devices and proposes its introduction in data center networks. The power consumption of the STIA is modeled, accounting for the energy proportionality of the optical devices in the STIA. Using such a model, a STIA-based network is designed using three different topologies, tree, folded Clos, and flattened butterfly, and optimized for power efficiency. Results show that, for a fixed topology, small-size STIAs are an energy-efficient solution for data center networks and allow a power reduction of more than an order of magnitude with respect to the Ethernet-based network. The comparison for the same bisection bandwidth shows that folded Clos and flattened butterfly outperform tree, whose power consumption is strongly dependent on the oversubscription ratio selected. View full abstract»

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  • Design and Evaluation of a Flexible-Bandwidth OFDM-Based Intra-Data Center Interconnect

    Article#: 3700310
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    Data center networks are facing growing challenges to deliver higher bandwidth efficiency, lower latency, better flexibility, and lower cost. Various optical interconnect schemes have been proposed to take advantage of the high bandwidth capacity and low power consumption offered by optical switching. However, these schemes cannot offer flexible bandwidth sharing due to the large granularity in optical circuit switching, and they require costly optical components. In this paper, we introduce a novel data center network architecture based on cyclic arrayed waveguide grating device and multiple-input multiple-output (MIMO) orthogonal frequency division multiplexing technology with parallel signal detection (PSD). This architecture offers flexible bandwidth resource sharing at fine granularity. Other features include high-speed switching, low and uniform latency, and the ability to change the data rates dynamically. By eliminating costly optical components and keeping the core optical router passive and static, the power consumption, hardware cost, and operation cost are reduced. The fine granularity bandwidth sharing and MIMO switching through PSD are verified experimentally. We also propose and evaluate efficient subcarrier allocation schemes to achieve high bandwidth utilization. Finally, we present the implementation of an efficient scheduler for the bandwidth allocation of the proposed scheme. View full abstract»

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  • An Energy-Efficient Optically Connected Memory Module for Hybrid Packet- and Circuit-Switched Optical Networks

    Article#: 3700407
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    Demands on future data centers and high-performance computing systems will require processor-memory interconnects with greater performance and flexibility than can be provided by existing electronic interconnects. The bandwidth density and bit-rate transparency offered by optical systems are uniquely suited to address these challenges facing memory interconnects. We, thus, investigate a hybrid packet- and circuit-switched optical interconnection network linking microprocessors with their associated main memory, which can simultaneously reduce memory access latency and improve energy efficiency performance. This novel hybrid approach allows low-bandwidth memory control data and small memory transactions to be efficiently transmitted as wavelength-striped optical packets, while long bursts of memory accesses are optically circuit switched. In this study, we experimentally demonstrate an optically connected memory system in which a microprocessor accesses multiple 80-Gb/s memory modules all-optically across a hybrid packet- and circuit- switched optical network. Error-free communication between the microprocessor and main memory is confirmed (bit-error rates less than 10-12) with the optical network providing low-memory access latencies. The overall memory system reduces energy consumption by 28%. View full abstract»

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  • Performance Analysis and Experimental Demonstration of a Novel Network Architecture Using Optical Burst Rings for Interpod Communications in Data Centers

    Article#: 3700508
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    In this paper, we propose to use a novel network architecture of multiple optical burst rings to improve the interpod communications of the internal networks of data centers. In the proposed network architecture, bursty and fast-changing interpod traffic is handled by the electrical core switches, while the relatively stationary traffic is handled via optical burst rings. Compared to previously proposed hybrid optical/electrical switching schemes of using optical circuit switches, the proposed scheme offers high interpod transmission bandwidth, supports large number of pods, requires smaller connection reconfiguration time, and has better bandwidth utilization. Moreover, the proposed scheme only employs relatively low-cost commercial optical components, making it more practical for near-term implementations. View full abstract»

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  • Advanced Modulation Techniques for High-Performance Computing Optical Interconnects

    Article#: 3700614
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    We experimentally assess the performance of a 64 × 64 optical switch fabric used for ns-speed optical cell switching in supercomputer optical interconnects. More specifically, we study four alternative modulation formats and detection schemes, namely, 10-Gb/s nonreturn-to-zero differential phase-shift keying with balanced direct detection, 10-Gb/s polarization division multiplexed (PDM) quadrature phase-shift keying, 40-Gb/s single-polarization 16-ary quadrature amplitude modulation (16QAM), and 80-Gb/s PDM-16QAM, with coherent intradyne detection, in conjunction with an optimized version of the optical shared memory supercomputer interconnect system switch fabric. In particular, we investigate the resilience of the aforementioned advanced modulation formats to the nonlinearities of semiconductor optical amplifiers, used as ON/OFF gates in the supercomputer optical switch fabric under study. In addition, we compare their performance using as a benchmark the performance of conventional 10-Gb/s intensity modulation direct detection (IM/DD). We show that the choice of the appropriate advanced modulation format can increase the capacity of the switch fabric, while, at the same time, it can mitigate the main nonlinear effect, i.e., cross-gain modulation that arises when using conventional IM/DD. Nonlinear phase distortion becomes the main limiting factor when advanced modulation formats are used. View full abstract»

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  • Runtime Management of Laser Power in Silicon-Photonic Multibus NoC Architecture

    Article#: 3700713
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    Silicon-photonic links have been proposed to replace electrical links for global on-chip communication in future many-core processors. Silicon-photonic links have the advantage of lower data-dependent power and higher bandwidth density, but the high laser power can more than offset these advantages. We propose a solution to manage laser power of silicon-photonic network-on-chip (NoC) in many-core system. We present a silicon-photonic multibus NoC architecture between private L1 caches and distributed L2 cache banks which uses weighted time-division multiplexing to distribute the laser power across multiple buses based on the runtime variations in the bandwidth requirements within and across applications to maximize energy efficiency. The multibus NoC architecture also harnesses the opportunities to switch OFF laser sources at runtime, during low-bandwidth requirements, to reduce laser power consumption. Using detailed system-level simulations, we evaluate the multibus NoC architecture and runtime laser power management technique on a 64-core system running NAS parallel benchmark suite. The silicon-photonic multibus NoC architecture provides more than two times better performance than silicon-photonic Clos and butterfly NoC architectures, while consuming the same laser power. Using runtime laser power management technique, the average laser power is reduced by more than 49% with minimal impact on the system performance. View full abstract»

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  • High-Speed Receiver Technology on the SOI Platform

    Article#: 3800108
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    Low power, low-cost, and high-speed photonic links are required in data centers. After significant research and development work over the last few years, silicon photonics has become a promising candidate to provide this technology. The receiver is one of the critical components for a photonic link. In this paper, we report recent progress in receiver technology on the silicon-on-insulator platform, particularly regarding its application to links that utilize wavelength division multiplexing (WDM). First, we discuss the key building blocks for WDM receivers: echelle grating demultiplexers and high-speed Ge photodetectors. We then report on the demonstration of a Terabit/s WDM receiver chip through monolithic integration of 40 high-speed Ge photodiodes with a 40-channel dense wavelength division multiplexing echelle grating. The device demonstrates that silicon photonics is a key technology to enable low-power and low-cost data center applications. View full abstract»

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  • Energy-per-Bit Limits in Plasmonic Integrated Photodetectors

    Article#: 3800210
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    The energy consumption per transmitted bit is becoming a crucial figure of merit for communication channels. In this paper, we study the design tradeoffs in photodetectors, utilizing the energy per bit as a benchmark. We propose a generic model for a photodetector that takes optical and electrical properties into account. Using our formalism, we show how the parasitic capacitance of photodetectors can drastically alter the parameter values that lead to the optimal design. Finally, we apply our theory to a practical case study for an integrated plasmonic photodetector, showing that energies per bit below 100 attojoules are feasible despite metallic losses and within noise limitations without the introduction of an optical cavity or voltage amplifying receiver circuits. View full abstract»

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  • Ultrashort SiGe Heterojunction Bipolar Transistor-Based High-Speed Optical Modulator

    Article#: 7900109
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    A graded base SiGe HBT optical modulator has high-speed, high optical modulation efficiency, small footprint. In this paper, we present our work in the design and modeling of an HBT optical modulator, its driver circuit and fabrication and integration. A high-efficient HBT electro-optical (EO) modulator with π phase-shift length of 22.6 μm is investigated. The speed of this modulator is calculated to be 30 Gb/s. To verify the functionality of HBT structure as an EO modulator, an 80 Gb/s serializer and driver with an HBT modulator is fabricated by the IBM 8HP BiCMOS process, which has much higher speed but lower modulation efficiency. View full abstract»

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  • Oxide-Relief and Zn-Diffusion 850-nm Vertical-Cavity Surface-Emitting Lasers With Extremely Low Energy-to-Data-Rate Ratios for 40 Gbit/s Operations

    Article#: 7900208
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    We demonstrate novel structures of a vertical-cavity surface-emitting laser (VCSEL) for high-speed (~40 Gbit/s) operation with ultralow power consumption performance. Downscaling the size of oxide aperture of VCSELs is one of the most effective ways to reduce the power consumption during high-speed operation. However, such miniaturized oxide apertures (~2 μm diameter) in VCSELs will result in a large differential resistance, optical single-mode output, and a small maximum output power (<; 1 mW). These characteristics seriously limit the maximum electrical-to-optical (E-O) bandwidth and device reliability. By the use of the oxide-relief and Zn-diffusion techniques in our demonstrated 850-nm VCSELs, we can not only release the burden imposed on downscaling the current-confined aperture for high speed with low-power consumption performance, but can also manipulate the number of optical modes inside the cavity to maximize the E-O bandwidth and product of bit-rate transmission distance in an OM4 fiber. State-of-the-art dynamic performances at both room temperature and 85 °C operations can be achieved by the use of our device. These include extremely high D-factors (~13.5 GHz/mA1/2), as well as record-low energy-to-data ratios (EDR: 140 fJ/bit) at 34 Gbit/s operation, and error-free transmission over a 0.8-km OM4 multimode fiber with a record-low energy-to-data distance ratio (EDDR: 175.5 fJ/bit.km) at 25 Gbit/s. View full abstract»

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  • Comparison of Silicon Ring Modulators With Interdigitated and Lateral p-n Junctions

    Article#: 7900308
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    We present a rigorous comparison between Si ring modulators based on interdigitated and lateral p-n junctions. A detailed Si ring modulator model is derived, which is used to fit and benchmark the measured modulation performance of both ring modulators. At 10 Gb/s and 1 Vpp drive swing, the interdigitated ring modulator is found to exhibit a superior extinction ratio at low insertion loss as compared to the lateral ring modulator, at the expense of a higher capacitive load. Design improvements are proposed to obtain 25-Gb/s operation with similar extinction ratio and low insertion loss in future devices. Such devices are attractive to enable power-efficient scaling of optical interconnects to 400 Gb/s and beyond. View full abstract»

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  • Energy-Efficient Oxide-Confined 850-nm VCSELs for Long-Distance Multimode Fiber Optical Interconnects

    Article#: 7900406
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    Highly energy-efficient oxide-confined 850-nm singlemode vertical-cavity surface-emitting lasers (VCSELs) for optical interconnects are presented. Error-free (defined as a bit error ratio <; 1 × 10-12) data transmission at 17 and 25 Gb/s across 100 m of multimode optical fiber is achieved with a low dissipated heat energy of only 69 and 99 fJ/bit, respectively. At 17 and 25 Gb/s, the transmission distance is increased to 1000 and 600 m, respectively. To date, our VCSELs are the most energy-efficient directly modulated lasers for data transmission across distances up to 1 km of multimode optical fiber. View full abstract»

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  • Device Scaling Considerations for Nanophotonic CMOS Global Interconnects

    Article#: 8200109
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    We introduce an analytical framework to understand the path for scaling nanophotonic interconnects to meet the energy and footprint requirements of CMOS global interconnects. We derive the device requirements for sub-100 fJ/cm/bit interconnects including tuning power, serialization-deserialization energy, and optical insertion losses. Using CMOS with integrated nanophotonics as an example platform, we derive the energy/bit, linear, and areal bandwidth density of optical interconnects. We also derive the targets for device performance which indicate the need for continued improvements in insertion losses (<;8 dB), laser efficiency, operational speeds (>40 Gb/s), tuning power (<;100 μW/nm), serialization-deserialization (<;10 fJ/bit/Operation), and necessity for spectrally selective devices with wavelength multiplexing (>6 channels). View full abstract»

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  • Back-End Deposited Silicon Photonics for Monolithic Integration on CMOS

    Article#: 8200207
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    We present the vision of back-end deposited silicon photonics (BDSP) and review works that have been done in this field. Individual aspects of BDSP platform including excimer-laser-annealed polycrystalline silicon, low-loss plasma-enhanced chemical vapor deposition silicon nitride waveguide, modulator, detector, electrical interface, back-end CMOS compatibility, and benefits of the platform are discussed in detail. View full abstract»

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  • Silicon Optical Interconnect Device Technologies for 40 Gb/s and Beyond

    Article#: 8200312
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    Important active technologies, modulators, photodetectors, and thermooptics for low-energy silicon optical interconnects are discussed. High-speed performance up to 40 Gb/s is reported for the silicon modulators and germanium photodetectors, and approaches for further improvement in speed and efficiency are presented. Low-voltage avalanche multiplication is demonstrated, giving a gain-bandwidth product of 75 GHz, while the combined effects of multiplication gain and the Franz-Keldysh effect enable a 5-μm-long germanium photodetector to achieve responsivity in the L-band that is comparable to that in the C-band. With trench-based thermal isolation, a low switching power of 0.4 mW is achieved for a thermooptic switch. View full abstract»

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  • Special issue on biophotonics

    Article#: 9800301
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Aims & Scope

Papers published in the IEEE Journal of Selected Topics in Quantum Electronics fall within the broad field of science and technology of quantum electronics of a device, subsystem, or system-oriented nature.

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Meet Our Editors

Editor-in-Chief
John Cartledge
Queen's University