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Components, Packaging and Manufacturing Technology, IEEE Transactions on

Issue 4 • Date April 2013

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Displaying Results 1 - 25 of 26
  • Front Cover

    Page(s): C1
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  • IEEE Transactions on Components, Packaging and Manufacturing Technology publication information

    Page(s): C2
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  • Table of contents

    Page(s): 531 - 532
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  • High-Temperature Die-Attach Technology for Power Devices Based on Thermocompression Bonding of Thin Ag Films

    Page(s): 533 - 542
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    Wide-bandgap materials such as silicon carbide enable power electronics to face increasing demands for greater power density and high-temperature capability at the chip level. However, new packaging solutions have yet to be found to replace Pb solders in high-temperature applications. In this paper, the applicability of electrodeposited Ag thin film as a novel high-temperature die-attach material to connect power chips to direct-bonded copper substrates is investigated. Ag films were obtained by electrochemical deposition on the backmetallization of Si chips. The joint was then produced by thermocompression bonding at 350°C with a 40-N force applied for 10 min in air. A die shear strength of 1.70 MPa (twice the MIL standard) was achieved. The assembly demonstrated satisfactory resistance to thermomechanical fatigue when subjected to thermal aging and thermal cycling tests in high-temperature environments. The proposed bonding technology is thus a suitable solution for the provision of strong and reliable joints for power devices which have to operate in extreme temperature conditions (>200°C). View full abstract»

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  • Experimental Evaluation of the Polarization Crosstalk When Soldering a Polarization-Maintaining Fiber Into a V-Grooved Substrate

    Page(s): 543 - 548
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    The influence of stress on the polarization extinction ratio (PER) when solderjet-bumping a bow-tie polarization-maintaining fiber (PMF) to a V-grooved ceramic substrate is experimentally evaluated. Throughout this paper, the linear polarization of the coupling laser beam is kept perpendicular to the V-grooved substrate plane while the fiber is rotated by a high-precision fiber gripper such that one of the fiber's main axes is aligned with the incoming polarization. On-axis alignment is conducted by positioning a small aspheric coupling lens with a high-precision multiaxis actuator. After alignment, the fiber is soldered to the substrate by a lead-free solder alloy. For each fiber sample, the PER is evaluated before and after soldering. Statistically relevant sample sets are evaluated in similar conditions and both fiber axes are considered for coupling. For the sake of comparison, this paper is also carried out while using UV-curing adhesive bonding as a fixing method. Under the experimental conditions, the decrease in PER when using solderjet bumping is evaluated to be about 7% of the initial value, showing that the technique could be suitable for mass-production PMF-based-devices microassembly. View full abstract»

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  • Thermal Stability Characterization of the Au–Sn Bonding for High-Temperature Applications

    Page(s): 549 - 557
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    There is a need for electromechanical devices capable of operating in high-temperature environments (>200°C) for a wide variety of applications. Today's wide-bandgap semiconductor-based power electronics have demonstrated a potential of operating above 400°C, however, they are still limited by packaging. Among the most promising alternatives is the Au-Sn eutectic solder, which has been widely used due to its excellent mechanical and thermal properties. However, the operating temperature of this metallurgical system is still limited to ~250°C owing to its melting temperature of 280°C. Therefore, a high-temperature-resistant system is much needed, but without affecting the current processing temperature of ~325°C, typically exhibited in most high-temperature Pb-free solders. In this paper, we present the development and characterization of a fluxless die-attach soldering process based on gold-enriched solid-liquid interdiffusion (SLID). A low-melting-point material (eutectic Au-Sn) is deposited in the face of a substrate, whereas a high-melting-point material, gold in this instance, is deposited in its mating substrate. Deposition of all materials was performed using a jet vapor deposition (JVD) equipment where thicknesses are controlled to achieve specific compositions in the mixture. Sandwiched coupons are isothermally processed in a vacuum reflow furnace for different reflow times. Post-processed samples confirm the interdiffusion mechanism as evidenced by the formation of sound joints that prove to be thermally stable up to ~490°C after the completion of the SLID process. Differential scanning calorimetry demonstrate the progression of the SLID process by quantifying the remaining low-melting-point constituent as a function of time and temperature, this serving as an indicator of the completion of the soldering process. Mechanical testing reveals a joint with shear strength varying from 39 to 45.5 MPa, demonstr- ting to be stable even after 500 h of isothermal aging. Moreover, these investigations successfully demonstrate the use of the Au-Sn SLID system and the JVD technology as potential manufacturing processes and as a lead-free die-attach technology. View full abstract»

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  • Study on Hybrid Au–Underfill Resin Bonding Method With Lock-and-Key Structure for 3-D Integration

    Page(s): 558 - 565
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    This paper describes a hybrid Au-underfill resin bonding method with lock-and-key structure for 3-D integration. In 3-D large scale integration (LSI), the gap between stacked chips becomes narrower because the bump dimension and pitch are smaller than those encountered in 2-D LSI. Therefore, the filling of gaps less than 10 μm using capillary forces often becomes insufficient because of the surface condition. To address this challenge, we study a hybrid bonding method in which the metal-metal and resin-resin bonding are carried out simultaneously with a chip resin applied previously only around the bump. To realize hybrid bonding on the entire chip, we fabricate indent and protrusion structures, which are called lock-and-key structures. The key structure is fabricated by a process that can remove the resin on the bumps by O2 plasma irradiation. The lock structure is fabricated by conventional photolithography and dry etching. By means of hybrid bonding with the lock-and-key structure, we have achieved the Au bump bonding and the filling of 4-μm gaps between the stacked chips, concurrently. The cross-sectional transmission electron microscopy image of the bonded sample demonstrated that no significant gap exists at both the Au-Au and resin-resin interfaces. In addition, the shear strength of the sample bonded with resin is 10 times higher than that without the resin. The electrical continuity of the Au bump connections after hybrid bonding has also been determined. View full abstract»

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  • Electroplating Characteristics of Sn–Bi Microbumps for Low-Temperature Soldering

    Page(s): 566 - 573
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    In this paper, the characteristics of eutectic Sn-Bi microsolder bumps fabricated by electroplating are investigated. The underbump metallization (UBM) layers on a Si chip consist of Al, Cu, Ni, and Au, sequentially from bottom to top. The desired Sn-Bi bump size has a diameter of 22 μm and pitch of 44 μm. In order to obtain the optimal conditions for the eutectic Sn-Bi solder bumps, the polarization curves of Sn, Bi, and Sn-Bi electrolytes are analyzed, and the variation of the Sn- Bi composition as a function of the current density is measured. Experimentally, from the polarization curve, Bi and Sn start to deposit below -0.12 and -0.54 V, respectively, and Sn-Bi codeposition occurs below an electropotential of -0.54 V. The Bi content of the electroplated bumps decreases from 92.4 to 38.2 wt% when the current density is increased from 20 to 50 mA/cm2, and near-eutectic composition of the Sn-61 wt% Bi bump is obtained by plating at 40 mA/cm2 for 5 min. The surface of the Sn-Bi microsolder bumps show plate-like structures with acicular shapes, and the grain size increases with increasing current density. An intermetallic compound layer, estimated as AuSn4 with a thickness of about 0.5 μm, was observed between the UBM layers and the as-plated Sn-Bi bumps. View full abstract»

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  • Non-PR Sn-3.5Ag Bumping on a Fast Filled Cu-Plug by PPR Current

    Page(s): 574 - 580
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    The electroplating of Sn-3.5 wt% Ag bumps without a photoresist (PR) mould on a Si chip was performed to reduce the production steps and cost for 3-D chip stacking. The electroplating characteristics of Sn-Ag and Sn-Ag bump growth were examined. The Sn-Ag bumps were electroplated on the Cu-plugged TSVs (through-silicon vias) of a Si chip. The Cu plug in the via was produced using a high-speed Cu filling process by a periodic pulse reverse current waveform. The electroplating current was supplied to the exposed Cu surface in the TSVs to produce the Sn-3.5Ag bumps. As the experimental results show, the Sn-3.5Ag bumps were fabricated successfully without a PR mould, with no serious defects by electroplating. The Ag contents in the Sn-Ag bump decreased with increasing current density. Besides, the bump height and width increased with increasing plating time. The bump width grew isotropically because of the absence of a PR mould. The Sn-3.55 wt% Ag bumps were obtained at a current density of -55 mA/cm2 for 20 min on the Cu plugs. View full abstract»

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  • Evaluation of Anisotropic Conductive Films Based on Vertical Fibers for Post-CMOS Wafer-Level Packaging

    Page(s): 581 - 591
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    In this paper, we investigate the mechanical and electrical properties of an anisotropic conductive film (ACF) on the basis of high-density vertical fibers for a wafer-level packaging (WLP) application. As part of the WaferBoard, a reconfigurable circuit platform for rapid system prototyping, ACF is used as an intermediate film providing compliant and vertical electrical connection between chip contacts and a top surface of an active wafer-size large-area IC. The chosen ACF is first tested by an indentation technique. The results show that the elastic-plastic deformation mode as well as the Young's modulus and the hardness depend on the indentation depth. Second, the efficiency of the electrical contact is tested using a uniaxial compression on a stack comprising a dummy ball grid array (BGA) board, an ACF, and a thin Al film. For three bump diameters, as the compression increases, the resistance values decrease before reaching low and stable values. Despite the BGA solder bumps exhibit plastic deformation after compression, no damage is found on the ACF film. These results show that vertical fiber ACFs can be used for nonpermanent bonding in a WLP application. View full abstract»

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  • Low-Cost PCB-Integrated 10-Gb/s Optical Transceiver Built With a Novel Integration Method

    Page(s): 592 - 600
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    A novel integration method for the production of cost-effective optoelectronic printed circuit boards (OE PCBs) is presented. The proposed integration method allows fabrication of OE PCBs with manufacturing processes common to the electronics industry while enabling direct attachment of electronic components onto the board with solder reflow processes as well as board assembly with automated pick-and-place tools. The OE PCB design is based on the use of polymer multimode waveguides, end-fired optical coupling schemes, and simple electro-optic connectors, eliminating the need for additional optical components in the optical layer, such as micro-mirrors and micro-lenses. A proof-of-concept low-cost optical transceiver produced with the proposed integration method is presented. This transceiver is fabricated on a low-cost FR4 substrate, comprises a polymer Y-splitter together with the electronic circuitry of the transmitter and receiver modules and achieves error-free 10-Gb/s bidirectional data transmission. Theoretical studies on the optical coupling efficiencies and alignment tolerances achieved with the employed end-fired coupling schemes are presented while experimental results on the optical transmission characteristics, frequency response, and data transmission performance of the integrated optical links are reported. The demonstrated optoelectronic unit can be used as a front-end optical network unit in short-reach datacommunication links. View full abstract»

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  • Hybrid Solid- and Liquid-Cooling Solution for Isothermalization of Insulated Gate Bipolar Transistor Power Electronic Devices

    Page(s): 601 - 611
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    Rapid increases in the power ratings and continuing miniaturization of power electronic devices have pushed chip heat fluxes well beyond the range of conventional thermal management techniques. The heat flux of power electronic devices for hybrid electric vehicles is currently at the level of 100-200 W/cm2 and is projected to increase to 500 W/cm2 in next generation vehicles. Such high heat fluxes lead to higher and less uniform insulated gate bipolar transistor (IGBT) chip temperature and significantly degrade the device performance and system reliability. Maintaining the maximum temperature below a specified limit, while isothermalizing the surface temperature of the chip, has become a critical issue for thermal management of power electronics. In this paper, a hybrid solid- and liquid-cooling system design, which combines cold plate liquid cooling and TE solid-state cooling, is proposed for thermal management of a 10 × 10 mm IGBT chip. The liquid-cooling cold plate is used for global cooling of the entire IGBT module while the embedded thin-film TE cooler (TEC) is employed for isothermalization of the individual IGBT chip. A detailed package-level 3-D thermal model is developed to explore the potential application of this cooling concept, with the primary attention focused on isothermalization and temperature reduction of IGBT chip associated with variations in TEC sizes, TE materials, applied current on TEC, cooling system designs, working fluid temperature, cold plate cooling capacity, and IGBT chip heat flux. The results demonstrate that the hybrid solid and liquid cooling is a very promising thermal management solution that can eliminate more than 90% of the temperature nonuniformity on the IGBT chip. View full abstract»

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  • Thermal Analysis of Light Emitting Diode Integrated Light Source Based on a Fourier Series Solution

    Page(s): 612 - 616
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    It is difficult to measure the junction temperature of every chip in the light emitting diode (LED) integrated light source by using common experimental methods. In this paper, a model to simulate the whole temperature field in sources face of LED integrated light is proposed. Fourier-based solution is used to solve the heat equation in three dimensions. The thermal model is programmed by Matlab and has been validated by finite element method simulations. The comparison shows that the relative error between these two models is within 3.6%. View full abstract»

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  • Design Optimization of Manifold Microchannel Heat Sink Through Evolutionary Algorithm Coupled With Surrogate Model

    Page(s): 617 - 624
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    A liquid flow manifold microchannel heat sink is optimized with the help of 3-D numerical analysis, a surrogate method, and a multiobjective evolutionary algorithm. The performance of the manifold microchannel heat sink is optimized for the overall thermal resistance and the pumping power required for driving the coolant. The design variables related to the width of the microchannel, depth of the microchannel, width of fins, length of the nozzles, and height of the nozzles, which contribute to objective functions, are identified and optimized for minimum thermal resistance and pumping power. A Latin hypercube sampling method is used to exploit the design space. The numerical solutions obtained at these design points are utilized to construct a surrogate model, i.e., response surface approximation. The Navier-Stokes and energy equations for laminar flow and conjugate heat transfer are solved using a finite-volume solver. A hybrid multi objective evolutionary algorithm coupled with a surrogate model is applied to find out global Pareto-optimal designs (PODs). Trade-off analysis is performed in view of the conflicting nature of the two objectives, which yields PODs with low thermal resistance at various pumping powers. The ratio of the microchannel width to the microchannel height and that of the nozzle height to the microchannel height are found to be more Pareto-optimal sensitive (sensitive along the Pareto-optimal front) than others. In contrast, the ratio of the fin width to the microchannel height and that of the nozzle length to the microchannel width are found to be less Pareto-optimal sensitive than other design variables. The PODs showed lower thermal resistance and pumping power than the reference designs at various mass flow rates. View full abstract»

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  • Electrical Properties of Nanocrystalline CuCr25 Contact Material

    Page(s): 625 - 632
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    Four pieces of nanocrystalline CuCr25 contacts with 45-mm diameter and 3-mm thickness were prepared, brazed onto cup-axial magnetic field electrodes, and assembled in two commercial vacuum interrupters to test their chopping current, ac dielectric breakdown voltage, and breaking capacity. For comparison, two microcrystalline CuCr25 contacts were also prepared as above. The test vacuum interrupters were operated by a 24-kV circuit breaker with a spring-operated mechanism. The opening velocity was 1.3 m/s and the arc current frequency was about 50 Hz. The experimental results showed that both the chopping current and the ac dielectric breakdown voltage of nanocrystalline CuCr25 contact material were lower than those of the microcrystalline CuCr25 material. The breaking capacity of nanocrystalline CuCr25 material was significantly lower than that of microcrystalline CuCr25. The cathode and the anode contact surfaces of nanocrystalline CuCr25 were seriously eroded by arc in the local areas, and obvious cracks occurred. View full abstract»

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  • Thermo-Mechanical Design Rules for the Fabrication of TSV Interposers

    Page(s): 633 - 640
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    The through-silicon-via (TSV) interposer is expected to be the driving vehicle for 2.5-D integrated circuit integration. Although a number of studies have been reported on the thermo-mechanical reliability of TSVs, it remains difficult to justify whether a TSV design or an interposer design is manufacturable or not because we still lack experimental reliability data. This investigation provides important experimental data as well as a series of correlation studies by finite element (FE) simulations. A 2-D analytical solution is also examined to help understand the physics of the problem. Regarding the experimental results, wafer cracking is observed for TSV arrays with large diameters and small pitch-to-diameter ratios after annealing at 300°C. The critical strength to wafer cracking is determined to be 388 MPa from some FE analyses. Through analytical considerations, the influence of TSV diameter on wafer cracking is found to rely on the contributions from the dielectric layer thickness and also the barrier layer thickness. An empirical model for the design of copper-filled TSV interposers is ultimately generated based on the modification of the 2-D solution. View full abstract»

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  • Electromagnetic-Simulation Program With Integrated Circuit Emphasis Modeling, Analysis, and Design of 3-D Power Delivery

    Page(s): 641 - 652
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    Accurate modeling and estimation of 3-D power network electrical performance are vitally important to aid 3-D integration and packaging design. This paper, for the first time, combines the electromagnetic (EM) simulation program with integrated circuit emphasis simulations to evaluate the electrical performance of a 3-D power network, which consists of Cu through-silicon-vias (TSVs), solders, micro-solders, and on-chip power grids. We intentionally partition a real stack-up structure of 3-D power network into separated components, electromagnetically extract all the passive elements resistance, inductance, conductance, and capacitance (RLGC) for each component at certain frequency points of interest. We then assemble all the components again into a corresponding equivalent circuit model and import EM-extracted RLGC values to analyze the overall 3-D system power performance. The number of stacked integrated circuits, floorplanning of TSVs/micro-solders, operating frequency of 3-D system, characteristics of decoupling capacitance, size of on-chip power grids, parasitics of power wires/vias/solders/TSVs/micro-solders, voltage supply, and waveform parameters of current loads are examined, unveiling several 3-D power delivery design implications. View full abstract»

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  • Ultra-Wideband Suppression of Power/Ground Noise in High-Speed Circuits Using a Novel Electromagnetic Bandgap Power Plane

    Page(s): 653 - 660
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    A power/ground plane pair is proposed using a novel planar electromagnetic bandgap (EBG) structure for isolating the power-to-ground noise (PGN) in high-speed circuits. Each unit cell of the novel EBG is designed by etching slots in a “C” shape on the power plane while maintaining the ground plane solid. Without cascading hybrid periodic structures, it shows an efficient mitigation of PGN within an ultra-wideband frequency range of 0.25-2.18 GHz. In this paper, the equivalent circuit model and cavity mode analysis for the novel EBG unit cell are given to quickly predict the lower and upper bound cutoff frequency, respectively. The dispersion diagram of the proposed EBG structure is validated by insertion loss measurements with ports at different locations of the unit cell for different modes. The result shows that there is a good consistency between the simulated and measured results. View full abstract»

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  • New Method for Fast Transient Simulation of Large Linear Circuits Using High-Order Stable Methods

    Page(s): 661 - 669
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    A new algorithm based on A -stable and L-stable high-order time-domain integration methods is presented for the simulation of large linear circuits such as those occurring in modeling chip interconnects and packaging structures. The proposed method takes advantage of the special structure of the mathematical formulation of circuits encountered in these applications to reduce the computational cost significantly. Several circuit examples are presented to demonstrate the speedup achieved by the proposed algorithm. View full abstract»

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  • Parallel-Distributed Block-LIM for Transient Simulation of Tightly Coupled Transmission Lines

    Page(s): 670 - 677
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    In this paper, the parallel-distributed block-latency insertion method (block-LIM) is proposed for the fast transient analysis of a large-scale circuit that includes lots of coupling elements, such as mutual inductance and mutual capacitance. A conventional SPICE-like simulator requires an enormous cost for transient analysis of large-scale equivalent network that includes tightly coupled transmission lines, which is derived by using well-established commercially based extractors. The proposed method is based on the leapfrog algorithm, and can efficiently analyze tightly coupled transmission lines. First, the original LIM and the block-LIM are reviewed briefly. Next, the parallel-distributed block-LIM is proposed for the fast transient simulation and is implemented on the personal-computer-cluster system. Finally, some numerical results are shown, and it is confirmed that the proposed technique is useful and efficient for the simulations of the tightly coupled transmission lines. View full abstract»

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  • 3-D Numerical and Experimental Investigations on Compression Molding in Multichip Embedded Wafer Level Packaging

    Page(s): 678 - 687
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    This paper focuses on the 3-D numerical methodology development of wafer level compression molding. With its successful application in a two-die-package embedded wafer level encapsulation, flow patterns, velocity, and pressure distributions are compared for different die size and die thickness. The computed flow-induced forces indicate which zone has a high risk of die sliding. The simulated molten molding compound flow fronts are compared with actual molding short shot samples. The key advantage of this numerical study is that it helps detect the molding defects quickly and improve moldability problems efficiently, in order to reduce manufacturing cost and design cycle time. View full abstract»

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  • All-Solution Thin-film Capacitors and Their Deposition in Trench and Through-Via Structures

    Page(s): 688 - 695
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    Thin integrated passive devices (IPDs) will play a critical role in the miniaturization of future high-performance electronic and bioelectronic systems. Silicon-based capacitors are currently manufactured with expensive processes such as sputtering and atomic layer deposition. Solution-deposited electrodes and dielectrics in trench and through-via structures provide alternative low-cost routes. Two solution-deposition techniques, spin-coating and vacuum infiltration, are investigated in this paper. A representative all-solution-derived thin-film capacitor consisting of sol-gel lanthanum nickel oxide (LNO) as the electrode, and sol-gel lead zirconate titanate as the dielectric thin-film is demonstrated in the first part of this paper. The role of barriers in reducing leakage currents is studied using three electrode systems: LNO/Si, LNO/ZrO2/Si, and LNO/Pt/Ta/Si. Capacitors with LNO electrodes directly deposited on naturally oxidized silicon resulted in higher leakages, more defects and a lower yield. The results show that the zirconia barrier suppresses the leakage current in the dielectric. The second part of this paper describes sol-gel films deposited in the through-via and trench surfaces to demonstrate the sol-gel conformal coating technique. Scanning electron microscopy cross-section analysis shows that the vacuum infiltration conformally coated through-vias. These solution deposition techniques may have the potential to fabricate IPD capacitors at low cost. View full abstract»

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  • LCP Characterization of Broadband RF Performance With Consideration of Fabrication Tolerances for CSLP Substrate Suitability

    Page(s): 696 - 707
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    This paper discusses the development of a chip scale level package substrate using liquid crystal polymer (LCP) laminates to support wideband millimeter-wave transmission lines and layer-to-layer transitions. To evaluate the reproducibility of RF performance on LCP in large-panel processing, an iterative design, simulation, fabrication, and test cycle is implemented. Inspection and verification methods are utilized to correlate variation in fabrication tolerances with simulation performance. With subsequent evaluations of fabricated substrates, a database is compiled to update design models and provide an estimate of RF performance yield based on fabrication tolerances. For the first time, a statistical analysis is presented for large-panel LCP fabrication tolerances using printed circuit board supplier techniques. View full abstract»

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  • Open Access

    Page(s): 708
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    Freely Available from IEEE
  • IEEE Components, Packaging, and Manufacturing Technology Society information for authors

    Page(s): C3
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IEEE Transactions on Components, Packaging, and Manufacturing Technology publishes research and application articles on modeling, design, building blocks, technical infrastructure, and analysis underpinning electronic, photonic and MEMS packaging.

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R. Wayne Johnson
Auburn University