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Solid-State Circuits, IEEE Journal of

Issue 4 • Date April 2013

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Displaying Results 1 - 24 of 24
  • Front Cover

    Publication Year: 2013 , Page(s): C1 - C4
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  • IEEE Journal of Solid-State Circuits publication information

    Publication Year: 2013 , Page(s): C2
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  • Table of contents

    Publication Year: 2013 , Page(s): 893 - 894
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  • Introduction to the Special Issue on the 2012 Symposium on VLSI Circuits

    Publication Year: 2013 , Page(s): 895 - 896
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  • A 0.25 V 460 nW Asynchronous Neural Signal Processor With Inherent Leakage Suppression

    Publication Year: 2013 , Page(s): 897 - 906
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1848 KB) |  | HTML iconHTML  

    Further power and energy reductions via technology and voltage scaling have become extremely difficult due to leakage and variability issues. In this paper, we present a robust and energy-efficient computation architecture exploiting an asynchronous timing strategy to dynamically minimize leakage and to self-adapt to process variations and different operating conditions. Based on a logic topology with built-in leakage suppression, the prototype asynchronous neural signal processor demonstrates robust sub-threshold operation down to 0.25 V, while consuming only 460 nW in 0.03 {\rm mm}^{2} in a 65 nm CMOS technology. These results represent a 4.4 \times reduction in power, a 3.7 \times reduction in energy and a 2.2 \times reduction in power density, when compared to the state-of-the-art processors. View full abstract»

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  • A 22 nm All-Digital Dynamically Adaptive Clock Distribution for Supply Voltage Droop Tolerance

    Publication Year: 2013 , Page(s): 907 - 916
    Cited by:  Papers (4)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2244 KB) |  | HTML iconHTML  

    An all-digital dynamically adaptive clock distribution mitigates the impact of high-frequency supply voltage ({\rm V}_{{\rm CC}}) droops on microprocessor performance and energy efficiency. The design integrates a tunable-length delay prior to the global clock distribution to prolong the clock-data delay compensation in critical paths during a {\rm V}_{{\rm CC}} droop. The tunable-length delay prevents critical-path timing-margin degradation for multiple cycles after the {\rm V}_{{\rm CC}} droop occurs, thus allowing a sufficient response time for dynamic adaptation. An on-die dynamic variation monitor detects the onset of the {\rm V}_{{\rm CC}} droop to proactively gate the clock at the end of the tunable-length delay to eliminate the clock edges that would otherwise degrade critical-path timing margin. In comparison to a conventional clock distribution, silicon measurements from a 22 nm test chip demonstrate simultaneous throughput gains and energy reductions of 14% and 3% at 1.0 V, 18% and 5% at 0.8 V, and 31% and 15% at 0.6 V, respectively, for a 10% {\rm V}_{{\rm CC}} droop. View full abstract»

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  • A 0.41 µA Standby Leakage 32 kb Embedded SRAM with Low-Voltage Resume-Standby Utilizing All Digital Current Comparator in 28 nm HKMG CMOS

    Publication Year: 2013 , Page(s): 917 - 923
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1741 KB) |  | HTML iconHTML  

    We propose low-leakage current embedded SRAMs with high-performance for mobile applications. The proposed SRAM has two standby modes depending on temperature; one is a low-voltage resume-standby mode to reduce the standby current ({\rm I}_{\rm STBY}) more effectively at room temperature, and the other is the conventional resume-standby to reduce {\rm I}_{\rm STBY} effectively at high temperature. These schemes are implemented in a single SRAM macro with an all-digital current comparator (ADCC) that chooses either mode by monitoring {\rm I}_{\rm STBY} automatically. ADCC has a time to digital converter (TDC) which is suitable for leakage measurement. Moreover, the proposed monitoring sequence can compensate the error of the measurement caused by the variation of the MOSFETs. A test chip was fabricated using 28 nm HKMG CMOS technology. The proposed 32 kb SRAM achieves 0.41 \mu{\rm A} standby leakage which is half of the conventional value. This SRAM also realizes a high-speed operation with an access time of 420 ps. View full abstract»

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  • Highly Energy-Efficient SRAM With Hierarchical Bit Line Charge-Sharing Method Using Non-Selected Bit Line Charges

    Publication Year: 2013 , Page(s): 924 - 931
    Cited by:  Papers (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2207 KB) |  | HTML iconHTML  

    Low voltage SRAM at a near-threshold voltage has two major sources of power waste: excess bit line swing due to the random variation of transistors and dynamic power consumption of the bit line swing of non-selected columns. In order to overcome these waste power consumption issues and achieve the highest energy-efficient operation of low voltage SRAM, the new CSHBL technique and CCC techniques, which is the improved version of the CSHBL, have been proposed. An SRAM fabricated using 65 nm technology adopting the CSHBL achieved an energy consumption of 26.4 pJ/Access/Mbit, and that of 13.8 pJ/Acess/Mbit is achieved by the SRAM macro that adopted CCC with 40 nm technology. This energy consumption is lower than values in previous works. View full abstract»

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  • A 32 nm 0.58-fJ/Bit/Search 1-GHz Ternary Content Addressable Memory Compiler Using Silicon-Aware Early-Predict Late-Correct Sensing With Embedded Deep-Trench Capacitor Noise Mitigation

    Publication Year: 2013 , Page(s): 932 - 939
    Cited by:  Papers (4)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2760 KB) |  | HTML iconHTML  

    A Ternary Content Addressable Memory (TCAM) uses a two-phase search operation where early prediction on its pre-search results prematurely activates the subsequent main-search operation, which is later interrupted only if the final pre-search results contradict the early prediction. This early main-search activation improves performance by 30%, while the low-probability of a late-correct has a negligible impact on power consumption. This Early-Predict Late-Correct (EPLC) sensing with silicon-aware tuning enables a high-performance TCAM compiler implemented in 32 nm High-K Metal Gate SOI process to achieve 1 Gsearch/sec throughput on a 2048x640 bit TCAM instance while consuming only 0.76 W, resulting in an energy efficiency of 0.58-fJ/bit/search. Embedded Deep-Trench (DT) capacitance reduces power supply collapse by 53% while adding only 5% area overhead for a total TCAM area of 1.56 mm ^{2} . View full abstract»

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  • Field Tolerant Dynamic Intrinsic Chip ID Using 32 nm High-K/Metal Gate SOI Embedded DRAM

    Publication Year: 2013 , Page(s): 940 - 947
    Cited by:  Papers (5)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1776 KB) |  | HTML iconHTML  

    A random intrinsic chip ID generation method using retention fails is implemented in 32 nm SOI embedded DRAM. A dynamic key algorithm employs a unique pair of 4 Kb binary strings for an ID record for secure authentication. These strings are generated by controlling a wordline low voltage to search for a number of fails matching the corresponding challenge numbers. The algorithm further includes field-tolerant authentication by detecting a number of common bits analytically guaranteed for successful recognition, while preventing ID spoofing during the read operation. This results in 100% successful unique ID generation and recognition in two temperature and three voltage conditions per chip for a total of \sim 420 k ID pair comparisons in 266 chips. The analytical model predicts a 99.999% successful recognition rate for 10 ^{6} parts. Finally, a method to enable a field-tolerant ID using multiple domains will be discussed. View full abstract»

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  • Adaptive Multi-Pulse Program Scheme Based on Tunneling Speed Classification for Next Generation Multi-Bit/Cell NAND FLASH

    Publication Year: 2013 , Page(s): 948 - 959
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2486 KB) |  | HTML iconHTML  

    As device technology is scaling down, {\rm V}_{\rm th} 's of NAND flash cell show a wide distribution due to process variations such as random dopant fluctuation, etc. Since the extension of {\rm V}_{\rm th} distribution is directly related to degradation of program performance of NAND flash, it is more challenging to meet the market requirements for applications such as solid-state drivers (SSD). This paper presents a novel program scheme, called Adaptive Multi-pulse Program (AMP), for the scaled multi-bit/cell NAND flash devices. In the proposed program scheme memory cells are classified into several groups based on their own program speeds. F-N tunneling characteristic of NAND cell array is considered in determining the level of program bias for each group. Adaptive program pulses are applied to the predefined groups so that cells reach their target verify level at the same time, regardless of the difference of their program speed. Our experimental results show that AMP achieves 20% improvement on program performance due to the reduction of the number of verify executions by 39% in 3-bit/cell architecture NAND flash memory of 21 nm CMOS technology. View full abstract»

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  • A Fully-Integrated, Miniaturized (0.125 mm²) 10.5 µW Wireless Neural Sensor

    Publication Year: 2013 , Page(s): 960 - 970
    Cited by:  Papers (4)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2485 KB) |  | HTML iconHTML  

    A wirelessly powered 0.125 mm² 65 nm CMOS IC for Brain-Machine Interface applications integrates four 1.5 µW amplifiers (6.5 µVrms input-referred noise with 10 kHz bandwidth) with power conditioning and communication circuitry. The multi-node backscatter frequency locks to a wireless interrogator using a frequency-domain multiple access communication scheme. The full system, verified with wirelessly powered in vivo recordings, consumes 10.5 µW and operates at 1 mm range in air with 50 mW transmit power. View full abstract»

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  • A 2.8 GS/s 44.6 mW Time-Interleaved ADC Achieving 50.9 dB SNDR and 3 dB Effective Resolution Bandwidth of 1.5 GHz in 65 nm CMOS

    Publication Year: 2013 , Page(s): 971 - 982
    Cited by:  Papers (8)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2620 KB) |  | HTML iconHTML  

    This paper presents a power- and area-efficient 24-way time-interleaved successive-approximation-register (SAR) analog-to-digital converter (ADC) that achieves 2.8 GS/s and 8.1 ENOB in 65 nm CMOS. To minimize the power and the area, the capacitors in the capacitive DAC are sized to meet the thermal noise requirements rather than the matching requirements, leading to the LSB capacitance of 50 aF. An on-chip digital background calibration is used to calibrate the capacitor mismatches in individual ADC channels, as well as the inter-channel offset, gain and timing mismatches. Measurement results at the 2.8 GS/s sampling rate show that the ADC chip prototype consumes 44.6 mW of power from a 1.2 V supply while achieving peak SNDR of 50.9 dB and retaining SNDR higher than 48.2 dB across the entire first Nyquist zone with a 1.8{\rm V} _{{\rm pp}mathchar input signal. The prototype chip occupies an area of 1.03 ,\times, 1.66 {\rm mm}^{2} , including the pads and the testing circuits. The figure of merit (FoM) of this ADC, calculated with the minimum SNDR in the first Nyquist zone, is 76 fJ/conversion-step. View full abstract»

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  • A Reconfigurable Mostly-Digital Delta-Sigma ADC With a Worst-Case FOM of 160 dB

    Publication Year: 2013 , Page(s): 983 - 995
    Cited by:  Papers (6)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (3065 KB) |  | HTML iconHTML  

    This paper presents a second-generation mostly-digital background-calibrated oversampling ADC based on voltage- controlled ring oscillators (VCROs). Its performance is in line with the best \Delta \Sigma modulator ADCs published to date, but it occupies much less circuit area, is reconfigurable, and consists mainly of digital circuitry. Enhancements relative to the first-generation version include digitally background-calibrated open-loop V / I conversion in the VCRO to increase ADC bandwidth and enable operation from a single low-voltage power supply, quadrature coupled ring oscillators to reduce quantization noise, digital over-range correction to improve dynamic range and enable graceful overload behavior, and various circuit-level improvements. The ADC occupies 0.075 mm ^{2} in a 65 nm CMOS process and operates from a single 0.9–1.2 V supply. Its sample-rate is tunable from 1.3 to 2.4 GHz over which the SNDR spans 70–75 dB, the bandwidth spans 5–37.5 MHz, and the minimum SNDR+ 10log(bandwidth/power dissipation) figure of merit (FOM) is 160 dB. View full abstract»

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  • An Integral Path Self-Calibration Scheme for a Dual-Loop PLL

    Publication Year: 2013 , Page(s): 996 - 1008
    Cited by:  Papers (5)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (3117 KB) |  | HTML iconHTML  

    An integral-path self-calibration scheme is introduced as part of a 20.1 GHz to 26.7 GHz low-noise PLL in 32 nm CMOS SOI. A dual-loop architecture in combination with an integral path measurement and correction scheme desensitizes the loop transfer function to the VCO's small signal gain variations. The spread of gain peaking is reduced by self-calibration from 2.4 dB to 1 dB, when measured at 70 sites on a 300 mm wafer. The PLL has a measured phase noise @10 MHz offset of {-} 126.5 dBc/Hz at 20.1 GHz and {-} 124.2 dBc/Hz at 24 GHz View full abstract»

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  • A 7 bit, 3.75 ps Resolution Two-Step Time-to-Digital Converter in 65 nm CMOS Using Pulse-Train Time Amplifier

    Publication Year: 2013 , Page(s): 1009 - 1017
    Cited by:  Papers (6)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2047 KB) |  | HTML iconHTML  

    In this paper, a novel pulse-train time amplifier is proposed that achieves linear, accurate, and programmable gain for a wide input range. Using the proposed pulse-train time amplifier, a 7-bit two-step TDC is implemented. The proposed TDC employs repetitive pulses with gated delay-lines for a calibration-free and programmable time amplification and quantization. The prototype chip fabricated in 65 nm CMOS process achieves 3.75 ps of time resolution at 200 MS/s while consuming 3.6 mW and occupying 0.02 mm ^2 area. Compared to previously reported TDCs, the proposed TDC achieves the fastest conversion rate and the best FoM without any calibration. View full abstract»

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  • A Low Quiescent Current Asynchronous Digital-LDO With PLL-Modulated Fast-DVS Power Management in 40 nm SoC for MIPS Performance Improvement

    Publication Year: 2013 , Page(s): 1018 - 1030
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (3070 KB) |  | HTML iconHTML  

    A low quiescent current asynchronous digital- LDO (D-LDO) regulator integrated with a phase-locked loop (PLL)-modulated switching regulator (SWR) that achieves the near-optimum power management supply for core processor in system-on-chip (SoC). The parallel connection of the asynchronous D-LDO regulator and the ripple-based control SWR can accomplish fast-DVS (F-DVS) operation as well as high power conversion efficiency. The asynchronous D-LDO regulator controlled by bidirectional asynchronous wave pipeline realizes the F-DVS operation, which guarantees high million instructions per second (MIPS) performance of the core processor under distinct tasks. The use of a ripple-based control SWR operating with a leading phase amplifier ensures fast response and stable operation without the need for large equivalent-series-resistance, thus reducing the output voltage ripple for the enhancement of supply quality. The fabricated chip occupies 1.04 {\rm mm}^{2} in 40 nm CMOS technology. Experimental results show that a 94% peak efficiency with a voltage tracking speed of 7.5 {\rm V}/\mu{\rm s} as well as the improved MIPS performance by 5.6 times was achieved. View full abstract»

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  • 50 mV-Input Batteryless Boost Converter for Thermal Energy Harvesting

    Publication Year: 2013 , Page(s): 1031 - 1041
    Cited by:  Papers (8)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2659 KB) |  | HTML iconHTML  

    A fully electrical startup boost converter for thermal energy harvesting is presented in this paper. The converter is implemented in a 65-nm bulk CMOS technology. With the proposed 3-stage stepping-up architecture, the minimum input voltage for startup is as low as 50 mV while the input voltage required for sustained power conversion is 30 mV. Due to the use of a zero-current-switching (ZCS) converter as the last stage and an automatic shutdown mechanism for the auxiliary converter, conversion efficiency up to 73% is achieved. By incorporating the boost converter and a thermoelectric generator (TEG), a miniaturized module is demonstrated for energy harvesting applications. View full abstract»

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  • A 2.4 GHz Multi-Channel FBAR-based Transmitter With an Integrated Pulse-Shaping Power Amplifier

    Publication Year: 2013 , Page(s): 1042 - 1054
    Cited by:  Papers (6)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2514 KB) |  | HTML iconHTML  

    A 2.4 GHz TX in 65 nm CMOS defines three channels using three high- {\rm Q} FBARs and supports OOK, BPSK and MSK. The oscillators have {-} 132 dBc/Hz phase noise at 1 MHz offset, and are multiplexed to an efficient resonant buffer. Optimized for low output power \approx {-} 10 dBm, a fully-integrated PA implements 7.5 dB dynamic output power range using a dynamic impedance transformation network, and is used for amplitude pulse-shaping. Peak PA efficiency is 44.4% and peak TX efficiency is 33%. The entire TX consumes 440 pJ/bit at 1 Mb/s. View full abstract»

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  • A 94 GHz mm-Wave-to-Baseband Pulsed-Radar Transceiver with Applications in Imaging and Gesture Recognition

    Publication Year: 2013 , Page(s): 1055 - 1071
    Cited by:  Papers (10)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (3352 KB) |  | HTML iconHTML  

    High-resolution mm-wave array beamformers have applications in medical imaging, gesture recognition, and navigation. A scalable array architecture for 3D imaging is proposed in which single-element phase coherent transceiver (TRX) chips, with programmable TX pulse delay capability, are mounted on a common board to realize the array. This paper presents the design of the enabling TRX chip: a highly integrated 94 GHz phase-coherent pulsed-radar with on-chip antennas. The TRX achieves 10 GHz of frequency tuning range and 300 ps of contiguous pulse position control, enabling its usage in the large-array imager with time-domain TX beamforming. The TRX is capable of transmitting and receiving pulses down to 36 ps, translating to 30 GHz of bandwidth. Interferometric measurements show the TRX can obtain single-target range resolution better than 375 \mu m (limited by equipment). Based on delay measurements, the time of arrival rms error would be less than 1.3 ps which, if used in a 3D imaging array, leads to less than 0.36 mm of RMS error in voxel size and position. View full abstract»

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  • A Harmonic-Rejecting CMOS LNA for Broadband Radios

    Publication Year: 2013 , Page(s): 1072 - 1084
    Cited by:  Papers (5)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2049 KB) |  | HTML iconHTML  

    The local oscillator harmonics corrupt the desired signal in broadband RF receivers by downconverting interferers. This paper proposes the notion of harmonic rejection in the front-end low-noise amplifier so as to relax the stringent matching required of harmonic-reject mixers. Described are frequency response shaping techniques by feedforward and unilateral Miller capacitance multiplication for a signal bandwidth of 100 MHz to 10 GHz. A calibration algorithm is also proposed for the tuning of the frequency response. An experimental prototype fabricated in 65-nm digital CMOS technology provides at least 20 dB of rejection while consuming 8.64 mW with a 1.2-V supply. View full abstract»

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  • A 100+ Meter 12 Gb/s/Lane Copper Cable Link Based on Clock-Forwarding

    Publication Year: 2013 , Page(s): 1085 - 1098
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (3827 KB) |  | HTML iconHTML  

    Active and passive copper cables for data rates exceeding 10 Gb/s are typically limited to less than 20 m. Optical fiber on the other hand offers superior performance for run length greater than 100 m, but is costly. Although 100 m copper link is demonstrated for 10GBASE-T, it utilizes complex symbols at a lower symbol rate across multiple signaling lanes and dissipates substantial power for DSP. In this paper, we propose a 12 Gbps/lane active cable link that extends copper cables {>} 100 meters using low power and area clocked repeaters powered through the cable that could potentially be embedded in the cable. The quality of the clock in such repeaters is the key component in maintaining a clean signal propagation through long distances. This paper introduces an FIR phase filtering technique in combination with an MDLL to deliver a low jitter forward clock. The total jitter at the end of the cable is 4.4 ps RMS. The link has repeating distances of 8 and 16 meters for data and clock, respectively. Each repeater occupies 1 mm ^2 of area in a 65-nm CMOS technology and dissipates 48 mW. View full abstract»

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  • Integrated Pop-Click Noise Suppression, EMI Reduction, and Short-Circuit Detection for Class-D Audio Amplifiers

    Publication Year: 2013 , Page(s): 1099 - 1108
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1990 KB) |  | HTML iconHTML  

    Circuit techniques that overcome practical noise, reliability, and EMI limitations are reported. An auxiliary loop with ramping circuits suppresses pop-and-click noise to 1 mV for an amplifier with 4 V-achievable output voltage. Switching edge rate control enables the system to meet the EN55022 Class-B standard with a 15 dB margin. An enhanced scheme detects short-circuit conditions without relying on overlimit current events. View full abstract»

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  • IEEE Journal of Solid-State Circuits information for authors

    Publication Year: 2013 , Page(s): C3
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Aims & Scope

The IEEE Journal of Solid-State Circuits publishes papers each month in the broad area of solid-state circuits with particular emphasis on transistor-level design of integrated circuits.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief
Michael Flynn
University of Michigan