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Electron Devices, IEEE Transactions on

Issue 4 • Date April 2013

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Displaying Results 1 - 25 of 37
  • Table of contents

    Page(s): C1 - C4
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  • IEEE Transactions on Electron Devices publication information

    Page(s): C2
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  • A Warm Welcome to a New T-ED Editor

    Page(s): 1297
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  • Theoretical Analysis of n-Type Si-Based Resonant Tunneling Diodes Deposited on Either Partially or Fully Relaxed SiGe Buffer Layers

    Page(s): 1298 - 1301
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (479 KB) |  | HTML iconHTML  

    We present a theoretical analysis on the electrical characteristics of n-type Si-based resonant tunneling diodes (RTDs) with double-barrier heterostructures (DBHs) on either partially or fully relaxed SiGe buffer layers. The analysis on these DBHs indicates that the large peak-to-valley ratios (PVRs) obtained at low temperatures decrease rather rapidly with the increase of temperature and become negligibly small at room temperatures because of the thermal broadening of the energy distribution of the electrons at higher temperatures. We propose to improve the temperature performance with the use of a narrow quantum well in the DBH. With this approach, a reasonable PVR from the structure deposited on a partially relaxed SiGe buffer is achieved. This paper provides an important alternative to the current approaches in developing Si-based RTDs for practical applications. View full abstract»

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  • Analytic Model of S/D Series Resistance in Trigate FinFETs With Polygonal Epitaxy

    Page(s): 1302 - 1309
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    In this paper, a simple but accurate model is presented to analyze source/drain (S/D) series resistance in trigate fin field-effect transistors, particularly on triangular or pentagonal rather than rectangular epitaxy. The model includes the contribution of spreading, sheet, and contact resistances. Although the spreading and sheet resistances are evaluated modifying standard models, the contact resistance is newly modeled using equivalent models of lossy transmission lines and transformations of 3-D to 2-D geometry. Compared with series resistance extracted from 3-D numerical simulations, the model shows excellent agreement, even when the S/D geometry, silicide contact resistivity, and S/D doping concentration are varied. We find that the series resistance is influenced more by contact surface area than by carrier path from the S/D extension to the silicide contact. To meet the series resistance targeted in the semiconductor roadmap, both materials and geometry will need to be optimized, i.e., lowering the silicide contact resistivity and keeping high doping concentration as well as maximizing the contact surface area, respectively. View full abstract»

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  • Contact Resistance Reduction for Strained N-MOSFETs With Silicon-Carbon Source/Drain Utilizing Aluminum Ion Implant and Aluminum Profile Engineering

    Page(s): 1310 - 1317
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1868 KB) |  | HTML iconHTML  

    We demonstrate a novel technique to reduce the nickel silicide (NiSi) contact resistance Rcon in strained n-channel MOSFETs (n-FETs) with silicon carbon (Si:C) stressors, where a presilicide aluminum (Al) implant is performed and the Al profile is found to be affected by carbon (C). Al diffusion during silicidation is retarded by the presence of C and a high Al concentration is retained within the NiSi:C film, which is considered to be the main reason for electron barrier height ΦBn reduction in NiSi:C contacts. Ge preamorphization implant prior to Al implant further reduces the ΦBn to 0.44 eV. Integration of this technique in n-FETs with Si:C stressors achieves a 50% reduction in source/drain series resistance and 12% enhancement in saturation drive current. Negligible impact on the device short-channel effects is observed. When Al segregates at the NiSi/Si interface, the hole barrier height ΦBp is lowered, and such an Al profile can be used for the p-FETs. Al profile engineering shows a promise as a single-metal-silicide solution for selective Rcon optimization in CMOS. View full abstract»

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  • A Comprehensive Crossbar Array Model With Solutions for Line Resistance and Nonlinear Device Characteristics

    Page(s): 1318 - 1326
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    This paper presents a comprehensive crossbar array model that incorporates line resistance and nonlinear device characteristics. The model can be solved using matrix algebra and is suitable for statistical analysis. The nonlinear device solution enables the assessment of crossbar arrays with diode or nonlinear select devices. The calculation based on this model shows that voltage and current degradation due to line resistance are not negligible even for small crossbar arrays, which constrains feasible array size. Diode and nonlinear select devices significantly improve the sensing margin of reading operation and the voltage window of writing operation. This model provides a quantitative tool for accurate analysis of crossbar arrays and the evaluation of memory select devices. View full abstract»

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  • Advanced DC-SF Cell Technology for 3-D NAND Flash

    Page(s): 1327 - 1333
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    Advanced dual control gate with surrounding floating gate (DC-SF) cell process and operation schemes are successfully developed for 3-D nand flash memories. To improve performance and reliability of DC-SF cell, new metal control gate last (MCGL) process is developed. The MCGL process can realize a low resistive tungsten (W) metal wordline, a low damage on tunnel oxide/inter-poly dielectric (IPD), and a preferable floating gate (FG) shape. Also, new read and program operation schemes are developed. In the new read operation, the higher and lower Vpass-read are alternately applied to unselected control gates to compensate lowering FG potential to be a pass transistor. In the new program scheme, the optimized Vpass are applied to neighbor WL of selected WL to prevent program disturb and charge loss through IPD. Thus, by using the MCGL process and new read/program schemes, the high performance and reliability of the DC-SF cell can be realized for 3-D nand flash memories. View full abstract»

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  • Germanium N and P Multifin Field-Effect Transistors With High-Performance Germanium (Ge) {\rm p}^{+}/{\rm n} and {\rm n}^{+}/{\rm p} Heterojunctions Formed on Si Substrate

    Page(s): 1334 - 1341
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    We demonstrate the characteristics of p+-Ge/n-Si and n+-Ge/p-Si heterojunction diodes formed by heteroepitaxial Ge grown on Si leading to high performance and very low leakage current. The ON/OFF current ratio of the p+-Ge/n-Si and n+-Ge/p-Si heterojunction was > 107 and > 106, respectively. The OFF current density was extremely low at <; 10 μA/cm2 for the p+-Ge/n-Si formed with different implantation energies of 10-40 KeV and ~ 20 μA/cm2 for the n+-Ge/p-Si with different implantation energies of 20-50 KeV at a reverse bias of |VR| = ±1 V, respectively. Both p and n-Ge channel multifin field-effect transistors (FinFETs) were formed by a mesa structure using these p+-Ge/n-Si and n+-Ge/p-Si heterojunctions. A high-κ/metal gate stack was employed. The body-tied Ge multifin FinFET with a fin width (WFin) of ~ 40 nm, and the channel length (LChannel) was 150 nm for p-FinFET and of 110 nm for n-FinFET, exhibiting a driving current of 174 μA/μm at VG=-2 V and 102 μA/μm at VG=2 V , respectively. This is the first experimental demonstration of a body-tied high mobility Ge channel multifin FinFET using a top-down approach. View full abstract»

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  • Semianalytical Model of the Subthreshold Current in Short-Channel Junctionless Symmetric Double-Gate Field-Effect Transistors

    Page(s): 1342 - 1348
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (515 KB) |  | HTML iconHTML  

    A 2-D semianalytical solution for the electrostatic potential valid for junctionless symmetric double-gate field-effect transistors in subthreshold regime is proposed, which is based on the parabolic approximation for the potential and removes previous limitations. Based on such a solution, a semi-analytical expression for the current is derived. The potential and current models are validated through comparisons with TCAD simulations and are used to evaluate relevant short-channel effect parameters, such as threshold roll-off, drain-induced barrier lowering, and inverse subthreshold slope. The implications of different possible definitions of threshold voltage, either based on the potential in the channel or on a fixed current level, are discussed. Finally, a fully analytical simplification for the current is suggested, which can be used in compact models for circuit simulations. View full abstract»

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  • Capacitance Hysteresis in the High-k/Metal Gate-Stack From Pulsed Measurement

    Page(s): 1349 - 1354
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    An unusual hysteresis is observed while measuring the capacitance-voltage (C-V) curve of the high-k/metal gate-stack using a pulsed-voltage technique. The hysteresis is found to vary only with the voltage ramp rate but not with the voltage pulse width. The C-V curve derived from the negative-to-positive (forward) voltage ramp has a consistently more positive flat ba5412279nd voltage than that obtained by the positive-to-negative (reverse) voltage ramp. The relative positions of the forward and reverse C-V curves are opposite to those measured using the quasi-static voltage-sweep method. Charge trapping/detrapping in the high-k oxide could not consistently account for these observations. An alternative explanation based on the lag in interface dipole response is proposed. View full abstract»

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  • Investigation of Silicon Nanowire Gate-All-Around Junctionless Transistors Built on a Bulk Substrate

    Page(s): 1355 - 1360
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    A silicon nanowire (Si-NW) with a gate-all-around (GAA) structure is implemented on a bulk wafer for a junctionless (JL) field-effect transistor (FET). A suspended Si-NW from the bulk-Si is realized using a deep reactive ion etching (RIE) process. The RIE process is iteratively applied to make multiply stacked Si-NWs, which can increase the on-state current when amplified with the number of iterations or enable integration of 3-D stacked Flash memory. The fabricated JL FETs exhibit excellent electrostatic control with the aid of the GAA and junction-free structure. The influence on device characteristics according to the channel dimensions and additional doping at the source and drain extension are studied for various geometric structures of the Si-NW. View full abstract»

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  • Lower Bound of Electrical Field for Maintaining a GaAs Photoconductive Semiconductor Switch in High-Gain Operating Mode

    Page(s): 1361 - 1364
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (558 KB) |  | HTML iconHTML  

    The high-gain operating mode of gallium arsenide (GaAs) photoconductive semiconductor switch (PCSS) brings the hope that a higher power PCSS will be triggered by a lower energy laser. However, the lock-on effect of high-gain PCSS restricts its lifetime and some other applications. In this paper, it is experimentally demonstrated that dynamically controlling the electrical field across a GaAs:EL2 PCSS can terminate the carrier avalanche and that there exists a lower bound of electrical field (about 3.64 kV/cm) for maintaining the high-gain operating mode of the PCSS under different conditions. This lower bound of electrical field is approximately equal to that of the transferred-electron effect; hence, it supports the hypothesis of a photon-activated charge domain to explain the physical phenomena of the high-gain PCSS. View full abstract»

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  • Effect of Strained k \cdot p Deformation Potentials on Hole Inversion-Layer Mobility

    Page(s): 1365 - 1371
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1146 KB) |  | HTML iconHTML  

    In the literature dedicated to strained p-type metal-oxide-semiconductor field-effect transistor inversion-layer mobility calculation via a k ·p valence-band structure, three key strain-related material parameters, namely, the Bir-Pikus deformation potentials aυ, b, and d, were widespread in magnitude. To improve such large discrepancies, in this paper, we conduct sophisticated calculations on 〈110〉/(001) and 〈110〉/(110) hole inversion-layer mobility for gigapascal-level uniaxial stresses along each of three crystallographic directions. The screening effect on surface roughness scattering is taken into account. We find that, to affect the calculated hole mobility enhancement, aυ is weak, b is moderate, and d is strong, particularly for the uniaxial compressive stress along the 〈110〉 direction. This provides experimental guidelines for an optimal determination of the primary factor, i.e., d, and the secondary factor, i.e., b, with the commonly used values for aυ. The result remains valid for varying surface roughness parameters and models and is supported by recent first-principles and tight-binding calculations. Thus, the strained k ·p valence-band structure with the optimized deformation potentials can ensure the accuracy of the calculated transport properties of 2-D hole gas under stress. View full abstract»

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  • Broadband Frequency Dispersion Small-Signal Modeling of the Output Conductance and Transconductance in AlInN/GaN HEMTs

    Page(s): 1372 - 1378
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    Frequency dispersion of transconductance and output conductance in AlInN/GaN high electron mobility transistors is investigated in this paper. Broadband dispersion effects in the microwave frequency range are reported for the first time. A small-signal model is developed. Trapping effects are taken into account with parasitic electrical networks including distributed time constants. The model is compared with experimental data for several bias conditions and different types of dispersion. View full abstract»

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  • A Novel Defect-Engineering-Based Implementation for High-Performance Multilevel Data Storage in Resistive Switching Memory

    Page(s): 1379 - 1383
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (616 KB) |  | HTML iconHTML  

    A novel strategy based on defect engineering is proposed for high-performance multibit data storage in oxide-based resistive random access memory (RRAM). Key innovations are: 1) material-oriented cell engineering for desired modification of physical locations of generated oxygen vacancies in resistive switching layer; and 2) operation scheme to control the amount of oxygen vacancy generated in the conducting filament regions during switching. Proper doping approach is applied to suppress the formation of oxygen vacancy clusters due to the avalanching effect in the forming and set processes. Gradual resistive switching process is observed in the devices with proper doping at the proper switching operation modes. Multilevels of resistance states are measured by the optimized dc or ac switching mode. Excellent memory performance with four-level data storage (good resistance uniformity under pulse switching, retention >104 s at 150°C, and endurance >106 cycles) is successfully demonstrated in hafnium oxide-based RRAM devices, indicating the viability of the proposed engineering design strategy. The proposed methodology helps to understand the mechanism of multilevel switching and provides guidelines for the design of high-performance multibit resistive switching memory devices. View full abstract»

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  • Conductive Filament Scaling of {\rm TaO}_{\rm x} Bipolar ReRAM for Improving Data Retention Under Low Operation Current

    Page(s): 1384 - 1389
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    The retention model of a bipolar ReRAM considering the percolative paths in a conductive filament is proposed. We demonstrate, for the first time, that the control of oxygen vacancy concentration in a conductive filament is the key for ensuring data retention including tail bits. To improve the retention property under low-current operation, the size of the conductive filament must be scaled down while keeping the density of oxygen vacancy high enough. Based on this concept, we demonstrate both low-current operation and sufficient retention results exceeding 500 h at 150°C, which correspond to more than 10 years at 85°C. View full abstract»

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  • Channel Width Splitting Effect on Driving Characteristics of Silicide Seed-Induced Laterally Crystallized Poly-Si Thin-Film Transistors

    Page(s): 1390 - 1396
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    The electrical performance of low-temperature polycrystalline silicon thin-film transistors (TFTs) is greatly affected by structures such as channel geometry, lightly doped drain, film thickness, etc. In this paper, the split channel polycrystalline silicon TFTs are fabricated through the silicide seed induced lateral crystallization method by dividing channel width with fixed numerical channel size. The number of channels splitting from 1 to 10 significantly improves driving characteristics such as driving current, field-effect mobility, subthreshold slope, and threshold voltage. It is found that the two main causes of improvements are the enlargement of effective channel width and a decrease in series resistance due to the crystal filtering effect on narrowly split channels, which lead to trap-state density reduction during lateral crystal growth. The causes of enlarged effective channel width and the decreased series resistance by the crystal filtering effect are demonstrated through capacitance-voltage and trap-state density extraction. View full abstract»

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  • Light Extraction Improvement for LED COB Devices by Introducing a Patterned Leadframe Substrate Configuration

    Page(s): 1397 - 1403
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (987 KB) |  | HTML iconHTML  

    We propose a patterned leadframe substrate (PLS) configuration for light-emitting diode chip-on-board devices (LED COBs) with regular triangular structures on it. The mechanism of this method is analyzed through ray dynamics, which indicate that the light-propagating regimes are considerably different as the structure inclination angle α changes. For typical encapsulant materials (refractive index=1.41), the optimal α is 22.5°~45°. Then the performance of LED COB devices with PLS configurations are verified through 3-D Monte Carlo ray-tracing simulations as well as experimental measurements. Results show that the light-extraction efficiency is significantly improved. A simulated enhancement of 42% and a measured enhancement of 41.07% are observed. These results are in good consistency with the ray dynamic analysis, confirming our predictions about PLS methods. Furthermore, we find that such an LED COB configuration also provides a way to change the angular distribution of intensity from half-peak side angle 101.84° to 141.80°. The findings of our work represent a new concept for LED COB packaging design of great practicality in building lighting systems. View full abstract»

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  • Modeling of the Steady State and Switching Characteristics of a Normally Off 4H-SiC Trench Bipolar-Mode FET

    Page(s): 1404 - 1411
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (760 KB) |  | HTML iconHTML  

    The electrical characteristics of a normally off 4H-silicon carbide (SiC) bipolar-mode FET are investigated by means of a careful design activity and an intensive simulation study useful for a first-time-ever realization of this device in SiC. Specific physical models and parameters strictly related to the presently available 4H-SiC technology are taken into account. The device basically consists of a trench vertical JFET operating in the bipolar mode that takes full advantage of the superior material properties. A drain-current density up to 500 A/cm2, a forced current gain on the order of 50, and a specific on-resistance as low as 1.3 mΩ·cm2 are calculated for a 1.3-kV blocking voltage device. The turn-off delay is on the order of a few nanoseconds. The presented analysis is supported by experimental results on the p-i-n diodes embedded in the device structure. View full abstract»

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  • 200 V Superjunction N-Type Lateral Insulated-Gate Bipolar Transistor With Improved Latch-Up Characteristics

    Page(s): 1412 - 1415
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    This paper evaluates the technique used to improve the latching characteristics of the 200 V n-type superjunction (SJ) lateral insulated-gate bipolar transistor (LIGBT) on a partial silicon-on-insulator. SJ IGBT devices are more prone to latch-up than standard IGBTs due to the presence of a strong pnp transistor with the p layer serving as an effective collector of holes. The initial SJ LIGBT design latches at about 23 V with a gate voltage of 5 V with a forward voltage drop (VON) of 2 V at 300 A/cm2. The latch-up current density is 1100 A/cm2. The latest SJ LIGBT design shows an increase in latch-up voltage close to 100 V without a significant penalty in VON. The latest design shows a latch-up current density of 1195 A/cm2. The enhanced robustness against static latch-up leads to a better forward bias safe operating area. View full abstract»

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  • Vertical Diamond Schottky Barrier Diode Fabricated on Insulating Diamond Substrate Using Deep Etching Technique

    Page(s): 1416 - 1420
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1077 KB) |  | HTML iconHTML  

    Diamond Schottky barrier diodes (SBDs) with vertical channel structures are fabricated on an insulating diamond substrate. The deep etching technique is used to make a vertical channel structure in the diamond stacking layers of the p+/p-/insulating substrate. Mo Schottky electrodes with the Al2O3 field plate structure are also fabricated to realize a high breakdown voltage. As a result, I-V characteristics with a high forward current density >103 A/cm2 and a high breakdown voltage >700 V are obtained at 25°C and 250 °C. Baliga's figure of merit is 332 MW/cm2, which is equivalent to the high value previously reported for diamond SBDs with lateral channel or pseudovertical channel structures, and is also ten times higher than the limit of Si SBDs. High-power diamond SBDs are expected to be realized on a large area insulating diamond substrate using this technique. View full abstract»

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  • Ultralow-Capacitance Through-Silicon Vias With Annular Air-Gap Insulation Layers

    Page(s): 1421 - 1426
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    Low capacitance is critical to the electric performance of through-silicon vias (TSVs). This paper reports the development and electrical characterization of ultralow-capacitance TSVs which use air gaps to replace the conventional silicon dioxide as the insulation layers. The air-gap TSVs are successfully fabricated by developing a sacrificial technology which uses void-free filling and selective etching of an annular benzocyclobutene polymer cladding that surrounds copper plugs. The capacitance and the leakage current are tested to characterize the electrical performance. The lowest effective dielectric constant of the air enables the capacitance of the air-gap TSVs to be as low as 24 fF, and the capacitance density is more than one order of magnitude lower than that of conventional SiO2 liner TSVs. The leakage current to the substrate is 3 ×10-13 A at 40 V, and no leakage current degradation occurs after a 40-cycle thermal shock test. The preliminary results demonstrate the new air-gap structure and the efficacy of air gaps in reducing TSV capacitance. View full abstract»

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  • Design and Analysis of Vertical Nanoparticles-Magnetic-Cored Inductors for RF ICs

    Page(s): 1427 - 1435
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    We report the design and analysis of the first vertical magnetic-cored inductors in CMOS backend for radio-frequency (RF) ICs, which includes theoretical and experimental studies of device architecture, equivalent circuit model with parameter extraction technique, process development, and device characterization. Vertical magnetic cores with multiple-layer stacked-spiral structures are designed to realize compact inductive devices in RF ICs. A CMOS-compatible post-CMOS backend process module (CMOS +) and optimized high-permeability nanoparticles are utilized to achieve a high inductance-to-coil-area ratio (L-density) in gigahertz range. The prototype six-layer inductors with NiZnCu ferrite nanoparticles-magnetic-core were fabricated in a commercial foundry 0.18-μm six-metal RF CMOS technology. A high L-density of over 700 nH/mm2 to multigigahertz was obtained, with an 80% chip size reduction from the reference planar magnetic inductors. An equivalent circuit model with parameter extraction technique is developed to analyze magnetic enhancement effects. This work demonstrates the potential of design and integration of compact high-performance vertical magnetic-cored inductive devices into CMOS backend for high-quality and low-cost RF systems-on-a-chip. View full abstract»

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  • Dielectric Permittivity of Porous Si for Use as Substrate Material in Si-Integrated RF Devices

    Page(s): 1436 - 1443
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (2086 KB) |  | HTML iconHTML  

    Dielectric permittivity of porous Si (PSi) layers formed on a low-resistivity p-type Si (0.001-0.005 Ω.cm) is thoroughly investigated using analytical expressions within the frame of broadband transmission line characterization method in the frequency range 1-40 GHz. It is demonstrated that the value of Si resistivity is critical for the resulting PSi layer permittivity even within the above limited resistivity range. The real part of PSi dielectric permittivity changes monotonically between 1.8 and 4 by changing the Si resistivity between 0.001 and 0.005 Ω.cm. The above study was made for porosities between 70% and 84%. The quality factor and attenuation loss of the investigated coplanar waveguide transmission lines were found to be Q=26 and a=0.19&nbsp;dB/mm, respectively, at 40 GHz. These values are competitive to those obtained on quartz, which is one of the off-chip RF substrates with the lowest losses. This confirms the superiority of the PSi material, mentioned above, for use as a local substrate for the on-chip RF device integration. View full abstract»

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IEEE Transactions on Electron Devices publishes original and significant contributions relating to the theory, modeling, design, performance and reliability of electron and ion integrated circuit devices and interconnects.

 

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Meet Our Editors

Acting Editor-in-Chief

Dr. Paul K.-L. Yu

Dept. ECE
University of California San Diego