# IEEE Transactions on Circuits and Systems II: Express Briefs

## Filter Results

Displaying Results 1 - 16 of 16

Publication Year: 2013, Page(s): C1
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• ### IEEE Transactions on Circuits and Systems-II: Express Briefs publication information

Publication Year: 2013, Page(s): C2
| |PDF (135 KB)
• ### Stability Analysis of Bang-Bang Phase-Locked Loops for Clock and Data Recovery Systems

Publication Year: 2013, Page(s):1 - 5
Cited by:  Papers (3)
| |PDF (306 KB) | HTML

Bang-bang phase detector-based phase-locked loops (PLLs) with first- and second-order analog loop filters (LFs) are considered. Discrete-time (DT) models are presented for the bang-bang PLLs (BPLLs) in the presence of loop delays. The DT models show that the delay introduces an additional pole at in the DT open-loop transfer function. The pole is of multiple order proportional to the delay, indica... View full abstract»

• ### A 10-Mbps 0.8-pJ/bit Referenceless Clock and Data Recovery Circuit for Optically Controlled Neural Interface System

Publication Year: 2013, Page(s):6 - 10
Cited by:  Papers (1)
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We propose a low-voltage low-power clock and data recovery (CDR) circuit which incorporates a relaxation-based voltage-controlled oscillator and clock-edge modulation, which eliminates the need for an external reference clock without allowing harmonic locking. This CDR supports input data rates between 200 kbps and 10 Mbps at 0.7 V and operates up to 24 MHz at 1.0 V. The proposed design consumes 8... View full abstract»

• ### A Fifth-Order 20-MHz Transistorized-$LC$ -Ladder LPF With 58.2-dB SFDR, 68-$muhbox{W/Pole/MHz}$ Efficiency, and 0.13-$hbox{mm}^{2}$ Die Size in 90-nm CMOS

Publication Year: 2013, Page(s):11 - 15
Cited by:  Papers (4)
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A novel transistorized-LC-ladder low-pass filter (LPF) is realized by combining source followers with Q-enhanced floating differential active inductors. It features a small number of active devices to minimize the sources of nonlinearity and noise and a robust frequency response against process variations and device mismatches. A fifth-order 20-MHz LPF prototype is fabricated in 90-nm CMOS. It mea... View full abstract»

• ### Low-Power High Parallel Load Resistance Current-Mode Grounded and Floating Capacitor Multiplier

Publication Year: 2013, Page(s):16 - 20
Cited by:  Papers (2)
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A current-mode capacitor multiplier using a high performance voltage follower is presented. The architecture has the ability to balance between very low equivalent series resistance of a few tens of ohms due to the voltage follower and very low power consumption achieved by means of reducing the biasing current in the output devices, forcing them to operate in subthreshold during static conditions... View full abstract»

• ### A LOG-Induced SSN-Tolerant Transceiver for On-Chip Interconnects in COG-Packaged Source Driver IC for TFT-LCD

Publication Year: 2013, Page(s):21 - 25
Cited by:  Papers (1)
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This brief presents a line-on-glass-induced simultaneous switching noise (SSN)-tolerant transceiver for on-chip interconnects in a chip-on-glass-packaged source driver IC for TFT-LCDs. An SSN compensator generates noise-sensitive bias voltages to maintain the bandwidth of a receiver. With each 10 noise of and , the proposed circuit shows an eye width of 0.542 UI with a bit error rate (BER) of for ... View full abstract»

• ### Memoryless Wide-Dynamic-Range CMOS Image Sensor Using Nonfully Depleted PPD-Storage Dual Capture

Publication Year: 2013, Page(s):26 - 30
Cited by:  Papers (4)
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A new low-cost high-performance dual-capture image sensor for wide-dynamic-range (WDR) applications is proposed. The proposed pixel uses a pinned photodiode (PPD) as a charge storage to achieve a WDR operation capability. By controlling the applied voltage at a transfer gate (TG) of the pixel to operate the PPD in a nonfull-depletion operation mode, the fixed pattern noise (FPN) that originated fr... View full abstract»

• ### VLSI Implementation of a Low-Cost High-Quality Image Scaling Processor

Publication Year: 2013, Page(s):31 - 35
Cited by:  Papers (10)
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In this brief, a low-complexity, low-memory-requirement, and high-quality algorithm is proposed for VLSI implementation of an image scaling processor. The proposed image scaling algorithm consists of a sharpening spatial filter, a clamp filter, and a bilinear interpolation. To reduce the blurring and aliasing artifacts produced by the bilinear interpolation, the sharpening spatial and clamp filter... View full abstract»

• ### FPGA-Based 40.9-Gbits/s Masked AES With Area Optimization for Storage Area Network

Publication Year: 2013, Page(s):36 - 40
Cited by:  Papers (24)
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In order to protect “data-at-rest” in storage area networks from the risk of differential power analysis attacks without degrading performance, a high-throughput masked advanced encryption standard (AES) engine is proposed. However, this engine usually adopts the unrolling technique which requires extremely large field programmable gate array (FPGA) resources. In this brief, we aim t... View full abstract»

• ### High-Performance Implementation of Point Multiplication on Koblitz Curves

Publication Year: 2013, Page(s):41 - 45
Cited by:  Papers (15)
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Fast and high-performance computation of finite-field arithmetic is crucial for elliptic curve cryptography (ECC) over binary extension fields. In this brief, we propose a highly parallel scheme to speed up the point multiplication for high-speed hardware implementation of ECC cryptoprocessor on Koblitz curves. We slightly modify the addition formulation in order to employ four parallel finite-fie... View full abstract»

• ### Joint DOA Estimation and Source Signal Tracking With Kalman Filtering and Regularized QRD RLS Algorithm

Publication Year: 2013, Page(s):46 - 50
Cited by:  Papers (7)
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In this brief, we present a nontraditional approach for estimating and tracking signal direction-of-arrival (DOA) using an array of sensors. The proposed method consists of two stages: in the first stage, the sources modeled by autoregressive (AR) processes are estimated by the celebrated Kalman filter, and in the second stage, the efficient QR-decomposition-based recursive least square (QRD-RLS) ... View full abstract»

• ### Initiation of Characteristic Ferroresonance States Based on Flux Reflection Model

Publication Year: 2013, Page(s):51 - 55
Cited by:  Papers (11)
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This brief focuses on the impact of basic circuit parameters to the initiation of characteristic ferroresonance states. Basic circuit parameters analyzed in this brief are the coil nominal voltage (which results to a range of inductance values and knee points for the coil characteristics), circuit capacitance, and the rms source voltage. It is shown that experimental results could be recreated by ... View full abstract»

• ### Comments on “A Note on Observers for Discrete-Time Lipschitz Nonlinear Systems”

Publication Year: 2013, Page(s):56 - 60
Cited by:  Papers (5)
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This brief deals with the problem of observers design for Lipschitz nonlinear systems in the discrete-time case. The main objective consists to clarify and to correct some recent results in this field. After a state of the art, some analytic comparisons are provided. Two numerical examples are given in order to show the nonsuperiority of the result of the work of Zhang for Lipschitz nonlinearities... View full abstract»

• ### IEEE Circuits and Systems Society Information

Publication Year: 2013, Page(s): C3
| |PDF (117 KB)
• ### IEEE Transactions on Circuits and Systems—II: Express Briefs information for authors

Publication Year: 2013, Page(s): C4
| |PDF (108 KB)

## Aims & Scope

Part I will now contain regular papers focusing on all matters related to fundamental theory, applications, analog and digital signal processing. Part II will report on the latest significant results across all of these topic areas.

Full Aims & Scope

## Meet Our Editors

Editor-in-Chief

Chi K. Michael Tse
Dept. of Electronic and Information Engineering
Hong Kong Polytechnic University
Hunghom, Hong Kong
cktse@ieee.org