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Components, Packaging and Manufacturing Technology, IEEE Transactions on

Issue 3 • Date March 2013

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  • [Front cover]

    Publication Year: 2013 , Page(s): C1
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  • IEEE Transactions on Components, Packaging and Manufacturing Technology publication information

    Publication Year: 2013 , Page(s): C2
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  • Table of contents

    Publication Year: 2013 , Page(s): 361 - 362
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  • Low-Temperature Pressure-Less Silver Direct Bonding

    Publication Year: 2013 , Page(s): 363 - 369
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1470 KB) |  | HTML iconHTML  

    A light-emitting diode (LED) die and a glass substrate, both of which were coated with a few-micrometers-thick silver layer, was successfully direct-bonded above 200°C in air without any pressure. In this silver direct bonding, the following three factors are essential: 1) keeping surfaces of silver layers clean; 2) bonding with a suitable solvent that can be reduced and has a boiling point near the sintering temperature; and 3) avoiding excessive heating. Oxygen concentration in a sintering atmosphere has a great impact on bonding. The surface of a silver layer shows roughening by abnormal grain growth as increasing oxygen resulting in increase of bonding strength. The abnormal grain growth on the surface of silver effectively contributes to the increase of junction area. Sintering at too high temperature, however, causes the formation of large voids, which migrated towards silver/glass interfaces resulting in the reduction of bonding strength. An LED die bonded at 240°C for 2 h can maintain high bonding strength through a heat run test at 350°C for 2 h. Furthermore, transient thermal resistance of an LED die bonded with the silver direct bonding is lower than that of an LED die bonded by traditional eutectic bonding with Au-Sn alloy. This bonding method can realize high thermal conductivity with low-temperature pressure-less process and can contribute to high-power semiconductor devices. View full abstract»

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  • Effect of the Thermomechanical Properties of No-Flow Underfill Materials on Interconnect Reliability

    Publication Year: 2013 , Page(s): 370 - 376
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1414 KB) |  | HTML iconHTML  

    The demands on flip chip packaging are increasing as the requirement for miniaturization and thinner silicon chips rises. In encapsulating flip chip packages it is important to not only maintain the mountability, but also to control the warpage of the package. In this paper, three types of underfill material with different thermomechanical properties are prepared. The requirements for achieving both longer interconnect life and the mountability with lower warpage are investigated. Underfill material with higher Young's modulus shows a longer interconnect life. From the results of failure analysis after thermal cycling, cracking at the edges of the bumps is observed. It is found from finite element analysis that underfill material with higher Young's modulus can effectively reduce the strain accumulating inside the bump. Underfill material with a low coefficient of thermal expansion reduces warpage after chip assembly. Therefore, optimization of both Young's modulus and the coefficient of thermal expansion of the underfill material are essential in order to achieve higher interconnect reliability while maintaining higher mountability. View full abstract»

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  • Contact Physics of Capacitive Interconnects

    Publication Year: 2013 , Page(s): 377 - 383
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    The resistance and capacitance of a typical multipoint contact interface have been used to assess the impact on high-frequency signal integrity. In the past, it has been shown how fully degraded interfaces could still provide acceptable performance for signal transfers at high data rates. In the case of fully degraded contacts, signals were shown to transfer by capacitive coupling and wave propagation. This paper focuses on the critical parameters of a capacitive-coupled interface. Moreover, the physics of the contact interface is related to contacts that rely on capacitive (as opposed to metallic) coupling and electronic tunneling. These results help define the physics and design requirements for capacitive coupling. In addition, critical performance parameters such as real contact area, film thickness, and the nature of dielectric films are defined for high-frequency signal propagation. This paper provides a contrast between the requirements for high-frequency signal transfer using capacitive coupling and electron tunneling versus traditional metallic contact. View full abstract»

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  • Material and Structure Designs for Reliable Quad-Flat-Package for Scaled-Down Ultralarge-Scale Integrations With Porous Low- k/{\rm Cu} Interconnects

    Publication Year: 2013 , Page(s): 384 - 390
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    Reliability of a quad-flat-package (QFP) with a circuit-under-pad (CUP) structure is investigated for Cu interconnects with porous low dielectric constant (low-k) films in scaled-down ultralarge-scale integrations. The following experimental factors are discussed: 1) low-k material properties and their stacking structures; 2) CUP structure; and 3) mold compound material properties. The QFP characteristics are analyzed after chip dicing and Ag wire bonding, as well as after molding. Higher adhesion strength of porous low-k film to SiCN cap dielectrics and rigid Cu-anchored CUP structure can achieve highly reliable QFP packaging. A lower coefficient of thermal expansion (CTE) of the molding compound is also found to be effective in eliminating low-k delamination during thermal cycle test because it can reduce the stress at the cracking position. The adhesion-promoting porous SiOCH film with the Cu-anchored CUP in a low-CTE mold is a promising system to realize a reliable QFP with no low-k delamination, passing electrical tests after the pressure-cooker test and high-temperature storage test. View full abstract»

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  • Compact Tunable Bandpass Filter With a Fixed Out-of-Band Rejection Based on Hilbert Fractals

    Publication Year: 2013 , Page(s): 391 - 400
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1512 KB) |  | HTML iconHTML  

    This paper proposes a new type of compact tunable bandpass filter with bandwidth tuning and out-of-band fixed rejection. Because we employ the modified Hilbert fractal structure loaded with varactors as resonators, the tunable filter has a very compact configuration and a constant shape over the entire tuning range. The frequency selectivity is improved by introducing a cross coupling between the source and the load. As a result of the utilization of a pair of properly designed feedlines, the frequency tuning and the out-of-band rejection of the filter are independent of each other, which simplifies its operation significantly. Two filter prototypes have been realized with the same size of 25.0 × 17.0 × 1.0 mm3. Their superior performances have been demonstrated experimentally, with good agreement obtained between their simulated and measured S-parameters. View full abstract»

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  • Acceleration of Spectral Domain Approach for Generalized Multilayered Shielded Microstrip Interconnects Using Two Fast Convergent Series

    Publication Year: 2013 , Page(s): 401 - 410
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1269 KB) |  | HTML iconHTML  

    A simple and versatile approach for the acceleration of the spectral domain approach for generalized shielded microstrip interconnects is presented. This approach uses asymptotic expansion for the Bessel's function and the Green's function followed by an approximation of infinite summation using two fast convergent sine cosine series. The asymptotic expansion coefficients of the Green's functions are found by a combination of analytical and numerical approaches. The infinite summation involved in the computation of the elements of the Galerkin matrix is accelerated using two fast convergent sine cosine series. The use of a few entire-domain basis functions gives very accurate results for the propagation constants for any mode in the general case of a multilayered shielded microstrip line. In addition to this, closed-form expressions are developed to choose the number of terms and some parameters to adaptively accelerate the convergence of the second type of fast convergent series for a given accuracy. This approach can be extended to handle multiple interconnects in the same layer and in different layers and also to include the effect of finite thickness and conductivity. View full abstract»

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  • High-Performance, Compact Quasi-Elliptic Band Pass Filters for V-Band High Data Rate Radios

    Publication Year: 2013 , Page(s): 411 - 416
    Cited by:  Papers (6)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (762 KB) |  | HTML iconHTML  

    This paper presents a comparison of the design and implementation of V-band quasi-elliptic band pass filters suitable for system-on-package integration at millimetre-wave frequencies. Filters were designed and manufactured at low-temperature co-fired ceramic (LTCC) and alumina substrates. Filter circuits include the input/output coplanar waveguide to microstrip transitions as well as the microwave pads, used to facilitate measurement. Three four-pole filters incorporating half-wavelength resonators were implemented, two planar (on LTCC and alumina substrates) and one vertically stacked (on LTCC). In addition a six-pole filter was also implemented in alumina. The four-pole LTCC based filters have a measured insertion loss (IL) as low as 3.4 dB, fractional bandwidth (FBW(%) = BW-3 dB/Center Frequency) of 4.8% and return loss better than 10 dB. Total filter size is less than 1.1 × 0.74 mm. The alumina-based four-pole/six-pole filters exhibit a measured IL of 2.8/3.1 dB, FBW of 8.3%/12.6%, respectively. Both alumina filters exhibit a return loss better than 10 dB and with a corresponding filter layout footprint of less than 1.01 × 1.34 mm. A new figure-of-merit (HPFOM) is proposed and results from the filters proposed here clearly show they offer the best trade-off between performance and area (higher HPFOM). View full abstract»

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  • Conformal Phosphor Distribution for White Lighting Emitting Diode Packaging by Conventional Dispensing Coating Method With Structure Control

    Publication Year: 2013 , Page(s): 417 - 421
    Cited by:  Papers (1)
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    Conformal phosphor distribution is a well known way to improve optical performance for white light emitting diode (LED) packaging. However, it is difficult to be realized by mature and cheap dispensing coating methods. In this paper, with consideration given to the effect of boundary constraint on liquid wetting morphology, a method to achieve phosphor conformal distribution is presented by conventional dispensing coating with controlling the slanting angle of reflector cups. The numerical simulations and experiments on phosphor dispensed into reflector cups with different slanting angles are conducted. The results show that uniform phosphor distribution can be obtained when the slanting angle is the same as the contact angle between the phosphor slurry and the reflector cup side wall. The rule can be used to guide the design of the reflector cup and a simple change of reflector cup can realize phosphor conformal coating for white LEDs by the low cost traditional dispensing coating process. View full abstract»

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  • Broadband Packaging of Photodetectors for 100 Gb/s Ethernet Applications

    Publication Year: 2013 , Page(s): 422 - 429
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    The packing structure of functional modules is a major limitation in achieving a desired performance for 100 Gb/s ethernet applications. This paper presents a methodology of developing advanced packaging of photodetectors (PDs) for highspeed data transmission applications by using 3-D electromagnetic (EM) simulations. A simplified model of the PD module is first used to analyze and optimize packaging structures and propose an optimal packaging design based on the simplified model. Although a PD module with improved performance proved the success of the optimal packaging design, the simplified model could not identify other important bandwidth limitation effects. Therefore, a full 3-D EM model of PD modules is developed to predict the optical-to-electrical response of the module, and with this model, it is possible to identify a critical mode mismatch effect as another important factor of limiting the bandwidth of PD modules. After eliminating the mode mismatch effect by improving the chip-conductor-backed coplanar waveguide transition, a final optimal packaging structure is implemented for the PD module with reduced attenuation up to 100 GHz and a broader 3-dB bandwidth of more than 90 GHz. Furthermore, the PD module exhibits excellent performance under the high-speed data-transmission experiment with 107 Gb/s data rate. View full abstract»

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  • On the Assessment of the Life of SnAgCu Solder Joints in Cycling With Varying Amplitudes

    Publication Year: 2013 , Page(s): 430 - 440
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2634 KB) |  | HTML iconHTML  

    The long-term reliability of SnAgCu solder joints under actual field service conditions is far from well understood. Most accelerated cycling tests are restricted to constant amplitudes, whereas realistic environments usually involve varying amplitudes and/or more than one type of loading. Thus assessments of life as well as relative comparisons of alternatives in terms of life in service invariably have to rely on the assumption of a damage accumulation rule. This paper focuses on the life of SnAgCu solder joints in isothermal mechanical cycling with varying amplitudes. Test samples use representative solder material and geometry in electronic packaging industry. Experimental results show that the load sequence affects life significantly, reflecting deviations from a linear damage accumulation rule. Hardness and microstructure of solder material are studied after cyclic loading. The effect of load sequence could be explained by the damage evolution path and solder property change, which varied with cycling. Moreover, different levels of initial loading lead to changes in acceleration factors in subsequent shear fatigue cycling. View full abstract»

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  • High-Speed Shear Test for Low Alpha Sn-1.0%Ag-0.5%Cu (SAC-105) Solder Ball of Sub-100- \mu{\rm m} Dimension for Wafer Level Packaging

    Publication Year: 2013 , Page(s): 441 - 451
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2219 KB) |  | HTML iconHTML  

    The issue of soft error in microelectronics packaging has necessitated the development of low alpha activity solders, as solders are found to be one of the major sources of radiation in electronic devices that causes soft error. Low alpha ray emitter Sn-1.0Ag-0.5Cu (SAC) solders were prepared and their alpha activity was measured using ultra-low background alpha particle counting systems. The solders are confirmed to be low alpha solders having activity less than 0.005 α h-1 cm-2. High-speed shear test is performed to assess the strength of low alpha SAC solder balls of sub-100-μm diameter for different pad finishes. Two types of fluxes, one rosin mildly activated (RMA) and the other water soluble (WS) types are used during soldering to investigate the effect of flux on solder joint strength. Fracture energy has proved to be better index than maximum shear force in interpreting the test results as the former correlates with the fracture mode better. The performance of WS flux is better than RMA flux across all pad finish and speed conditions and among the pad finish electroless nickel electroless palladium immersion gold (ENEPIG) is superior to electroless nickel immersion gold, which in turn is better than organic solder preservative. Clearly the best choice is ENEPIG pad finish with WS flux. Intermetallic compound composition and morphology has been found to have significant effect on strength of solder joint. The shear strength of low alpha SAC105 is found to be lower than the high-Ag containing SAC305 and SAC405 solders. However, the effect of removing radioactive impurities from SAC105 on its shear strength and fracture energy remains inconclusive and needs further investigations. View full abstract»

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  • Warpage Prediction and Experiments of Fan-Out Waferlevel Package During Encapsulation Process

    Publication Year: 2013 , Page(s): 452 - 458
    Cited by:  Papers (4)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1086 KB) |  | HTML iconHTML  

    A wafer level package (WLP) that has a flip chip form and uses thin-film redistribution with solder bumps to connect the package to the printed wiring board directly is discussed in this paper. A liquid molding compound is used for the encapsulation process. Since the thickness of the fan-out WLP is smaller than that in a traditional integrated circuit (IC) package, the fan-out WLP induces more serious warpage. Warpage plays an important role during the IC encapsulation process, and too large a warpage would not let the package proceed to the next manufacturing process. This paper uses an approach that considers both cure- and thermal-induced shrinkages during the encapsulation process to predict the amount of warpage. Cure-induced shrinkage is described by the pressure-volume-temperature-cure (PVTC) equation of the liquid compound. The thermally induced shrinkage is described by the coefficients of thermal expansion of the component materials. The liquid compound properties are obtained by various techniques, such as cure kinetics by differential scanning calorimetry- and cure-induced shrinkage by a PVTC testing machine. These experimental data are used to formulate the PVTC equation. A fan-out WLP is first simulated, and the simulation results are verified with experiments. It is shown that an approach that considers both thermal and cure/compressibility effects can better predict the amount of warpage for the fan-out WLP. The PVTC equation is successfully implemented, and it is verified that warpage is governed by both thermal and cure shrinkages. The amount of warpage after molding could be accurately predicted with this methodology. Simulation results show that cure shrinkage of the liquid compound is the dominant factor responsible for package warpage after encapsulation. View full abstract»

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  • Warpage Estimation of a Multilayer Package Including Cure Shrinkage Effects

    Publication Year: 2013 , Page(s): 459 - 466
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (637 KB) |  | HTML iconHTML  

    Warpage and residual stresses in plastic electronics packages are partly due to the shrinkage of the epoxy molding compound during the cure stage and partly due to the mismatch in thermal expansions during the cooling stage. Here, we present a simple but robust way of estimating the warpage part due to the curing effects. The main assumption of our analytical model is that the molding compound remains in the rubbery phase during cure. Using this model, we derive expressions for the effective cure shrinkage and the stress-free temperature. The effective cure shrinkage is a single parameter that can be used as an intrinsic strain value in numerical simulations, which then allows accounting for the curing effects. The solutions are benchmarked with both experimental warpage curves from the literature and with full numerical simulations on a four-layer package consisting of lead frame, die attach, die, and the molding compound. Both comparisons show that our analytical predictions are well capable of accurately predicting cure-induced warpage in multilayer systems. View full abstract»

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  • Design of Compact Dual-Band Power Dividers With Frequency-Dependent Division Ratios Based on Multisection Coupled Line

    Publication Year: 2013 , Page(s): 467 - 475
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1192 KB) |  | HTML iconHTML  

    In this paper, a design method of compact dual-band power dividers with frequency-dependant power division ratios in two separated bands is proposed. A multisection coupled-line scheme is presented that takes advantage of the different odd- and even-phase velocities of a microstrip implemented coupled line. The proposed method is applicable to an extended frequency ratio of 1.4-3 compared to the formerly investigated coupled-line dual-band transformer. The design procedures are demonstrated by two design examples, and measurements of the implemented circuits are made for verification. View full abstract»

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  • Vertical Noise Coupling From On-Chip Switching-Mode Power Supply in a Mixed-Signal Stacked 3-D-IC

    Publication Year: 2013 , Page(s): 476 - 488
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2870 KB) |  | HTML iconHTML  

    In this paper, we propose a fast and accurate model of the vertical noise coupling from an on-chip switching-mode power supply (SMPS) to a low noise amplifier (LNA) in a stacked 3-D-IC. To achieve both speed and accuracy, the model is based on the analytic formulas of static R, L, and C parasitic extraction, and includes consideration of the phase difference in the on-chip inductors using a new iterative calculation method. The proposed model and the prediction of vertically coupled noise at the LNA output using the model are experimentally validated on a fabricated stacked 3-D-IC consisting of an onchip SMPS and LNA. Good agreement with the measurements is confirmed in both the frequency domain and the time domain. The enhancements of the proposed model, including the broad model bandwidth (<; 4 GHz) as good as 3-D EM solver and 99% reduction of the simulation elapsed time (2 s) from 3-D EM solver, are confirmed. This paper also analyzes: 1) the impact of vertical noise coupling on the RF signal gain performance of the LNA and 2) the impact of variation in the stacking configuration, location, and thickness of the stacked LNA on the vertical noise coupling using the proposed model. Based on the results of our analysis, this paper proposes and verifies an effective method to reduce the vertical noise coupling using the proposed model. View full abstract»

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  • Complete Modeling of Large Via Constellations in Multilayer Printed Circuit Boards

    Publication Year: 2013 , Page(s): 489 - 499
    Cited by:  Papers (6)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (824 KB) |  | HTML iconHTML  

    This paper presents, for the first time, the comprehensive modeling of complete via constellations consisting of several thousands of vias in multilayer printed circuit boards using the physics-based approach. For each computational step of the physics-based approach, several alternatives are analyzed with regard to their computational efficiency, and calculation times are discussed as a function of the number of simulated vias. The results of this analysis are used in combination with previous studies to determine an efficient yet accurate algorithm for the simulation of large numbers of vias. The impact of the stackup configuration on the computational effort of the algorithm is analyzed, and the most computationally expensive parts of the calculation process are identified. A parallelization of the algorithms is carried out to accelerate the critical calculation tasks. As an evaluation example, simulation results for a via array consisting of 10 000 vias and eight cavities are shown. With the proposed simulation methods, the computation time for this via array is about 6.5 h per frequency point on a single CPU and about 40 min per frequency point with the parallel version running on 16 CPUs. View full abstract»

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  • Novel Extraction of a Table-Based I–Q Behavioral Model for High-Speed Digital Buffers/Drivers

    Publication Year: 2013 , Page(s): 500 - 507
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (925 KB) |  | HTML iconHTML  

    An efficient and accurate table-based behavioral model extraction for high-speed input/output (I/O) buffer behavior is presented in this paper. The nonlinear current-voltage (I-V) and charge-voltage (Q-V) functions describing the graybox model structure are extracted via least-squares methods using identification signals recorded from large signal transient simulation. The resulting continuous time-domain model is easily implemented as lookup table and leads to an increase in modeling accuracy, and a decrease in computation time, as is demonstrated in this paper. Finally, its application in a realistic signal integrity scenario is presented, demonstrating a superior performance compared to that of the I/O buffer information specification model. View full abstract»

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  • Predicting the Behavior of Screen Printing

    Publication Year: 2013 , Page(s): 508 - 515
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (797 KB) |  | HTML iconHTML  

    A novel mathematical model is presented of the liquid transfer process encountered during screen printing, enabling the prediction of the volume of liquid removed from a mesh and printed on a substrate with reasonable accuracy. It is based on the key assumption that free surface effects dominate and the printed liquid is pulled out of, rather than flows from, the mesh. The model is validated against an extensive range of benchmark data from both on- and off-screen printing trials. The agreement is found to be remarkably good. In addition, the model is able to offer considerable insight to practitioners and liquid manufacturers alike-a key result being that the screen printing process can be made essentially independent of many of the set-up parameters in the operating range adopted by most practitioners. View full abstract»

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  • Classification of Solder Joint Using Feature Selection Based on Bayes and Support Vector Machine

    Publication Year: 2013 , Page(s): 516 - 522
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (807 KB) |  | HTML iconHTML  

    In this paper, a feature selection and a two-stage classifier for solder joint inspection have been proposed. Using a three-color (red, green, and blue) hemispherical light-emitting diode array illumination and a charge-coupled device color digital camera, images of solder joints can be obtained. The color features, including the average gray level and the percentage of highlights and template-matching feature, are extracted. After feature selection, based on the algorithm of Bayes, each solder joint is classified by its qualification. If the solder joint fails in the qualification test, it is classified into one of the pre-defined types based on support vector machine. The choice of the second stage classifier is based on the performance evaluation of various classifiers. The proposed inspection system has been implemented and tested with various types of solder joints in surface-mounted devices. The experimental results showed that the proposed scheme is not only more efficient, but also increases the recognition rate, because it reduces the number of needed extracted features. View full abstract»

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  • Laser Trim Pattern Optimization for CuAlMo Thin-Film Resistors

    Publication Year: 2013 , Page(s): 523 - 529
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (630 KB) |  | HTML iconHTML  

    The influence of varying laser trim patterns on the electrical performance of a novel CuAlMo thin-film resistor material is investigated. The benefits and limitations of various trim geometries are considered before two patterns, the “L” cut and serpentine cut, are selected to laser-trim resistor samples to target values of 1-10 Ω, using previously optimized laser conditions. The effect of increasing trim gain and varying trim pattern on the stability and standard deviation of the films is then systematically investigated. A two-stage trimming process is used to reduce resistance drift to <;0.1% following storage for 168 h at 125°C in air, which also allows much tighter resistance tolerances of <;±0.1% to be achieved. View full abstract»

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    Publication Year: 2013 , Page(s): 530
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  • Open Access

    Publication Year: 2013 , Page(s): 531
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Aims & Scope

IEEE Transactions on Components, Packaging, and Manufacturing Technology publishes research and application articles on modeling, design, building blocks, technical infrastructure, and analysis underpinning electronic, photonic and MEMS packaging.

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Meet Our Editors

Managing Editor
R. Wayne Johnson
Auburn University