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Components, Packaging and Manufacturing Technology, IEEE Transactions on

Issue 2 • Date Feb. 2013

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  • [Front cover]

    Page(s): C1
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  • IEEE Transactions on Components, Packaging and Manufacturing Technology publication information

    Page(s): C2
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  • Table of contents

    Page(s): 185 - 186
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  • Microspring Characterization and Flip-Chip Assembly Reliability

    Page(s): 187 - 196
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2754 KB) |  | HTML iconHTML  

    Electronics packaging based on stress-engineered spring interconnects has the potential to enable integrated IC testing, fine pitch, and compliance not readily available with other technologies. We describe new spring contacts which simultaneously achieve low resistance ( <; 100 mΩ) and high compliance (>; 30 μm) in dense 2-D arrays (180 ~ 180-μm pitch). Mechanical characterization shows that individual springs operate at approximately 150-μN force. Electrical measurements and simulations imply that the interface contact resistance contribution to a single contact resistance is <; 40 mΩ . A daisy-chain test die consisting of 2844 contacts is assembled into flip-chip packages with 100% yield. Thermocycle and humidity testing suggest that packages with or without underfill can have stable resistance values and no glitches through over 1000 thermocycles or 6000 h of humidity. This paper suggests that integrated testing and packaging can be performed with the springs, enabling new capabilities for markets such as multichip modules. View full abstract»

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  • Multichip Embedding Technology Using Fine-Pitch Cu–Cu Interconnections

    Page(s): 197 - 204
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    Increasing performance and functional density while maintaining low cost is a catalyst for technological progress in the field of packaging. From flip-chip with solder to a hybrid approach of copper and solder, many methods have been created to reach this objective. The 3-D Packaging Research Center at Georgia Tech has been revolutionizing interconnection technology with the multichip embedding chip-last approach, which utilizes ultrathin adhesive-bonded copper bumps to enable ultrafine-pitch chip-to-package interconnections. This technology has been proven to be highly reliable using a low-cost low-temperature direct copper-to-copper bonding approach at 30-μm pitch and ~20-μm standoff height copper-to-copper interconnections. This interconnection method provides a platform for integration with flip-chip packages through its proven ability to work well with different die sizes and thicknesses bonded to the surface of ultrathin organic substrates. The next step in advancing the chip-last approach is to investigate chip embedding at the single-chip and multichip levels. Consequently, this paper focuses on: 1) the design and fabrication of the test vehicle to examine the reliability of the previously demonstrated copper-to-copper interconnections after embedding a thin die in an organic substrate, and 2) assembly process development and reliability data for the interconnections. Specifically, advances in the assembly process include: 1) a novel method to perform chip-last assembly at the panel level leading to a 10-15 times reduction in assembly time per die, and 2) an improved two-step assembly process to achieve simultaneous die embedding and cavity planarization. This embedding technology and its advancements not only allow actives to be embedded in organic substrates but also enables higher functional integration at high-throughput, making chip-last adhesive bonding with low-profile copper-to-copper interconnections a robust chip embedding solution- for the next generation of highly integrated heterogeneous subsystems. View full abstract»

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  • Sliding Mechanism of Lateral Thermosonic Process With Anisotropic Conductive Film for High Productivity and High Reliability

    Page(s): 205 - 212
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    In this paper, a thermosonic flip-chip bonding process using lateral ultrasonic vibration is proposed. To enhance the reliability of the specimen after the lateral thermosonic process, a sliding mechanism is adopted with investigation of equivalent stiffness of the anisotropic conductive film (ACF) joint. By a tensile test, it is shown that the equivalent stiffness of the ACF joint gradually increases as curing proceeds. Based on these results, the sliding point where the vibration amplitude of the chip specimen begins to decrease can be adjusted by the applied pressure. Thanks to the sliding mechanism, forced excitation to the sufficiently cured chip specimen can be naturally avoided. In addition, the robustness of the degree of cure against the bonding time variation can be improved in spite of the short bonding time. To demonstrate the feasibility of the proposed sliding mechanism in practice, experiments are conducted with a commercialized driver chip assembly of a liquid crystal display with an ACF. View full abstract»

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  • Thermal Stability of Optical Coupling Solutions in Silicone-Based Optical Interconnects

    Page(s): 213 - 220
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    The thermal stability of different coupling solutions (butt coupling and mirror coupling) in polymer optical interconnects has been investigated by means of the finite volume method based software, FLOTHERM. According to this approach, thermal simulations are performed to study and compare the thermal behavior of vertical-cavity surface-emitting diodes (VCSELs), photo diodes (PDs), and polymer waveguide layers within polymer optical interconnects with different coupling solutions. In the case of butt coupling, the maximum temperatures on the VCSEL and PD chips, as well as the influence caused by changes of the optical interconnect length, are discussed. In the case of mirror coupling, temperature distributions and gradients in the key waveguide layer are analyzed and also compared with optical interconnects using butt coupling. With this simulated temperature distribution and the experimentally evaluated refractive indices and thermooptic coefficients of core and cladding silicones, the influence on the maximum data transmission capability in silicone-based waveguides is discussed, as well as the impact on waveguide insertion loss figures at 850 nm. View full abstract»

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  • 3-D Packaging With Through-Silicon Via (TSV) for Electrical and Fluidic Interconnections

    Page(s): 221 - 228
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    In this paper, a liquid cooling solution has been reported for 3-D package in package-on-package format. A high heat dissipating chip is mounted on a silicon carrier, which has copper through-silicon via (TSV) for electrical interconnection and hollow TSV for fluidic circulation. Heat transfer enhancement structures have been embedded in the chip carrier. Cooling liquid, de-ionized water is circulated through the chip carrier and heat from the chip is extracted. The fluidic channels are isolated from electrical traces using hermetic sealing. The research work has demonstrated liquid cooling solution for 100 W from one stack and total of 200 W from two stacks of the package. The fluidic interconnections and sealing techniques have been discussed. View full abstract»

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  • Stretchable Electronics Technology for Large Area Applications: Fabrication and Mechanical Characterization

    Page(s): 229 - 235
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    The development and mechanical characterization of a novel technology for stretchable electronics is presented, which can be used for the realization of wearable textile electronics and biomedical implants. The stretchable devices consist of rigid or flexible component islands interconnected with stretchable meander-shaped copper conductors embedded in a stretchable polymer, polydemethylsiloxane. The technology uses standard printed circuit board manufacturing steps and liquid injection molding techniques to achieve a robust and reliable product. The conductors in the device are designed to accommodate strains up to 10-15%. Spin-on photo-definable polyimide as mechanical support for the stretchable interconnects and the functional flexible islands are introduced. By use of polyimide, the reliability of the stretchable interconnects, the straight interconnects on the flexible islands and the transitions between the stretchable and nonstretchable parts are improved. Long-term endurance behavior of the stretchable interconnects is studied by cyclic elongation at strain ranges of up to 20% while monitoring the electrical connectivity. It's shown that the lifetime of the polyimide supported interconnects is at least two times better compared to the nonsupported. View full abstract»

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  • One-Port Resonance-Based Test Technique for RF Interconnect and Filters Embedded in RF Substrates

    Page(s): 236 - 246
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    In this paper, a one-port test approach is proposed for testing radio frequency (RF) interconnects as well as RF passive filters embedded in RF substrates. The proposed technique relies on the use of an RF oscillator that is coupled to the embedded interconnect/filter via a probe card. Shifts in the RF oscillation frequency (referred to as resonance-based test) are used for defect detection, and are different from prior oscillation-based test techniques that configure the device under test itself into an oscillator. A core innovation is that the technique can detect defects in embedded passives/filters using only one-port probe access and eliminates the need of an external RF input test stimulus. Such one-port probing causes a shift in the oscillation frequency of the external oscillator because of the loading from the embedded RF passive circuit. To facilitate test response measurement, the output of the external RF oscillator (GHz signal) is down-converted to lower frequencies (MHz). The proposed test method is demonstrated through both simulations and measurements. Additionally, panel-level testing of RF substrates is illustrated. View full abstract»

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  • Compact and Broadband CB-CPW-to-SIW Transition Using Stepped-Impedance Resonator With 90 ^{\circ} -Bent Slot

    Page(s): 247 - 252
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    In this paper, a compact and broadband conductor-backed coplanar waveguide (CB-CPW) to substrate integrated waveguide (SIW) transition using a stepped-impedance resonator (SIR) with a 90°-bent slot is proposed. The proposed transition can achieve a 36.8% 15-dB fractional bandwidth, which almost covers the S-band (2.6-3.95 GHz). Compared to the CB-CPW-to-SIW transition using the single-section quarter-wavelength transformer, transition using the SIR with the 90°-bent slot can increase the 15-dB fractional bandwidth from 23.44% to 36.8% and reduce the physical length from 14 to 7.2 mm. In order to verify the simulation results, back-to-back transitions are fabricated and measured, and the measurement results are in good agreement with those of simulation. View full abstract»

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  • Substrate-Integrated Waveguide Bandpass Filters With Planar Resonators for System-on-Package

    Page(s): 253 - 261
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    This paper proposes some novel substrate-integrated waveguide (SIW) bandpass filters combined with planar resonators. According to specific topologies, microstrip lines with different electrical lengths are introduced into their designs. Their corresponding phase-shift characteristics are used to obtain the desired couplings between SIW cavities and the microstrip resonator. Two third-order filter samples are realized. One has a single transmission zero below the passband and the other possesses a quasi-elliptic response. Further, a fourth-order filter is developed by effectively superpositing two individual third-order topologies. It shows better frequency selectivity and flat in-band group delay, with good agreement between the measured and the simulated S-parameters. Their compactness and high rejection in the stopbands make them very suitable for system-on-package. View full abstract»

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  • Analytical Approach to Design of Proportional-to-the-Absolute-Temperature Current Sources and Temperature Sensors Based on Heterojunction Bipolar Transistors

    Page(s): 262 - 274
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    Embedded temperature sensors based on proportional-to-the-absolute-temperature (PTAT) current sources have the potential to lay the foundation for low-cost temperature-aware integrated circuit architectures if they meet the requirements of miniaturization, fabrication process match, and precise estimation in a wide range of temperatures. This paper addresses an analytical approach to the minimum-element PTAT circuit design capitalizing on the physics-based modeling of the heterojunction bipolar transistor (HBT) structures. It is shown that a PTAT circuit can be implemented on only two core HBT elements with good accuracy. Derived parametric relations allow a straightforward specification of the thermal gain at the design stage, which affects sensor sensitivity. Further derived current-to-temperature mapping expresses a temperature estimate based on the measured PTAT output current. Numerical examples indicate attainable estimation accuracy of 0.43% in case of a measurement instance taken in the absence of measurement noise. View full abstract»

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  • Constitutive Modeling of Joint-Scale SAC305 Solder Shear Samples

    Page(s): 275 - 281
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    In this paper, the creep behavior of lead-free hypo-eutectic Sn96.5Ag3.0Cu0.5 (SAC305) solder alloy is evaluated. A series of creep tests at different stress/temperature and strain rate/temperature pairs are conducted on joint-scale solder samples under shear. Stress-strain data is reported for constant stress (15-30 MPa) and constant shear strain rate (1E-6-1E-2 s-1) tests at temperatures of 20°C, 50 °C, 75°C, and 100°C. The quantitative data gained from the tests is used to fit an Anand viscoplastic constitutive model. The quality of the model fit and the intrinsic variability of the test specimens are also assessed. View full abstract»

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  • Conductive Anodic Filament Reliability of Small and Fine-Pitch Through Vias in Halogen-Free Organic Packaging Substrate

    Page(s): 282 - 288
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    The trend toward miniaturization of electronic systems demands reliable small fine-pitch through vias in organic packages and high-density interconnect system boards. Fine-pitch through vias in glass fiber-reinforced organic packages suffer from electrical insulation failures due to the formation of conductive anodic filaments (CAFs) in the presence of temperature, humidity, and voltage. In addition to the requirement for fine-pitch through vias, restriction in use of halogens as well as the move toward green electronic systems has driven the development of halogen-free thermally stable novel resin formulations for next-generation glass fiber-reinforced substrates. The introduction of new resin chemistries can also affect the reliability, as CAF failures are known to depend on the substrate material properties. In this paper, CAF reliability of small and fine-pitch through vias in a halogen-free glass fiber-reinforced organic substrate is investigated. Test structures with through via diameter of 100 μm with two different pitches, i.e., 250 and 500 μm , were fabricated and tested using 100 V direct current (dc) bias at 85 °C and 85% relative humidity for 1000 h. Insulation failures were observed in test structures with a pitch of 250 μm, while the test structures with a pitch of 500 μm exhibited stable insulation resistance during the test. Failures were identified using optical microscopy and characterized using scanning electron microscopy. The results indicate that CAF failures are a concern with fine-pitch through vias in packages, and, therefore, careful selection of materials and processes is required for achieving reliable fine-pitch through vias in high-density packages. View full abstract»

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  • Fast {cal H} -Matrix-Based Direct Integral Equation Solver With Reduced Computational Cost for Large-Scale Interconnect Extraction

    Page(s): 289 - 298
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    In this paper, we propose a fast H-matrix-based direct solution with a significantly reduced computational cost for an integral-equation-based capacitance extraction of large-scale 3-D interconnects in multiple dielectrics. We reduce the computational cost of an H-matrix-based computation by simultaneously optimizing the H-matrix partition to minimize the number of matrix blocks and minimizing the rank of each matrix block based on a prescribed accuracy. With the proposed cost-reduction method, we develop a fast LU-based direct solver. This solver possesses a complexity of kCspO (NlogN) in storage, a complexity of k2Csp2O(Nlog2N) in LU factorization, and a complexity of kCspO(NlogN) in LU solution, where k is the maximal rank, Csp is a constant dependent on matrix partition, and the constant kCsp is minimized based on accuracy by the proposed cost-reduction method. The proposed solver successfully factorizes dense matrices that involve millions of unknowns in fast CPU time and modest memory consumption, and with the prescribed accuracy satisfied. As an algebraic method, the underlying fast technique is kernel independent. View full abstract»

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  • Accurate 3-D Capacitance of Parallel Plates From 2-D Analytical Superposition

    Page(s): 299 - 305
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    The two conductor strip line is a classic transmission line structure which has been extensively studied and used in endless applications for decades. Unfortunately, the exact determination of the 3-D capacitance of this basic case is analytically intractable. It will be shown that accurate values of the total 3-D capacitance of a parallel plate capacitor with thin plates of any length, width, and separation can be determined from the superposition of the exact 2-D capacitance obtained from an analytic solution using elliptic integrals in a very simple manner. The accuracy is determined for a range of cases through a comparison of the analytic values with those obtained from a 3-D numerical calculation, using a work station with very large memory and processing capability. For most cases, the accuracy of the capacitance obtained by this superposition method falls nearly within the bounds of the numerical accuracy of the 3-D model and the elliptical integral evaluations. This superposition method is far more accurate than expected. View full abstract»

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  • Multiconductor Transmission Line Models for Modal Transmission Schemes

    Page(s): 306 - 314
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    We investigate modal transmission schemes used to reduce echo and internal crosstalk in a multichannel link using an untransposed multiconductor interconnection. The core of such a modal transmission scheme is an appropriate multiconductor transmission line (MTL) model of the interconnection. The standard theory of modal signaling, which emphasizes modal voltages, modal currents, and associated eigenvectors is summarized. Then, we present new results of MTL theory: three theorems on generalized associated eigenvectors and two high-frequency approximations. These results are needed to explain an assumption used in some modal transmission schemes. View full abstract»

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  • Modeling of Vias Sharing the Same Antipad in Planar Waveguide With Boundary Integral Equation and Group T-Matrix Method

    Page(s): 315 - 327
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1301 KB) |  | HTML iconHTML  

    We consider multiple scattering among different groups of vias with each group of vias sharing one antipad in planar waveguide. A transformation is used that converts the 2-D discretization and 2-D surface integration of the product of Green's functions and magnetic surface currents into 1-D discretization and 1-D integration of surface charges on the vias and on the ground plane. This is used to calculate the incident fields onto the vias. Based on the incident fields, the Foldy-Lax equations can be solved to calculate the circuit parameters for the problem. We show that the results are superior to the previously used finite difference method. In addition, the group T-matrix method is used to represent a group of vias to account for the scattering among different groups of vias. Results are illustrated for various cases of multiple vias up to 20 GHz. Results show the accuracy of the method even to very closely spaced vias when they are separated by merely 1 mil. Numerical results are in excellent agreement with ANSOFT HFSS. View full abstract»

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  • In Situ Measurement and Stress Evaluation for Wire Bonding Using Embedded Piezoresistive Stress Sensors

    Page(s): 328 - 335
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    A ball bonding process in wire bonding generally involves impact followed by ultrasonic (US) bonding prior to wedge bonding. During the ball bonding process, the impact force flattening the free-air ball introduces significant localized out-of-plane compressive stress on the pad and the low-k structure beneath. The subsequent process of US bonding induces in-plane and shear stresses to the structure. High induced stress during bonding is not desirable, as it may lead to pad damage or cratering of the silicon structure. In this paper, we report on studies conducted on using four piezoresistive sensors embedded underneath the center of the bond pad for the evaluation of in-plane and out-of-plane stresses, which covers both the impact and US stages during the ball bonding process. Different levels of impact force, bond force, bonding duration, and US power are investigated using gold wire bonding for feasibility and sensitivity studies of the stress sensors. Fast Fourier transform (FFT) and inverse FFT are used for noise filtering and to isolate the US signal yielding a continuous output signal from the in situ measurement of contact and US stages during the ball bonding process. It is found that the stress sensors are sensible to capture different impact force, bond force, bonding duration, and US power. View full abstract»

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  • Ultrasonic Effects in the Thermosonic Flip Chip Bonding Process

    Page(s): 336 - 341
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    Thermosonic flip chip (TSFC) bonding is a developing area in array microelectronic interconnection technology, and ultrasonic vibration plays an important role in TSFC bonding. To understand the ultrasonic effects at the bonding interface, a lab bonder is constructed, TSFC bonding is realized, and some ultrasonic effects (plastic deformation of the bumps on the bond pads, atom diffusion, and increased dislocation density) are observed. A dynamic finite element model of TSFC bonding is developed to analyze the stress and strain distribution at the bonding interface. The results of our study show that ultrasonic vibration causes a large cycled stress of about 288 MPa at the bonding interface, which: 1) increases dislocation density, forms dislocation nets, and provides fast diffusion channels, and 2) increases the stress gradient, provides the driver force for atom diffusion, and increases the atom diffusion flux. The large cycled stress plays a key role in forming a 25-nm diffusion layer and a good bonding strength in 100 ms at the TSFC bonding interface. View full abstract»

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  • Sensorless Closed-Loop and Selective Heating for SiP MEMS Flip Chip

    Page(s): 342 - 349
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    System-in-package (SiP) devices are increasingly becoming popular. When they are packaged using controlled collapse chip connection or derived processes, precise substrate heating at the land location is necessary. Currently, this is commonly achieved by heating the chip-handling probe. This approach restrains free motion of the chip and inhibits self-alignment of the chip to the substrate. Alternatively, the system is heated in a furnace. We present a method that heats the substrate locally at the desired spot while precisely controlling the temperature. This is achieved by embedding a Joule heater into the substrate. Additional sensors are not required because the change of the resistance of the heating, which reflects the change in temperature, is closely monitored. Because the temperature is determined inside the substrate, it provides accurate feedback of the solder's temperature. The method has been implemented and tested in an SiP microelectromechanical systems assembly process. It has proven to be a viable alternative to current methods, and features fast, localized, and tightly controlled heating and does not restrict the chip's free motion, thereby allowing chip self-alignment. Since the heating is integrated into the substrate, it also does not interfere with other components and requires no housing to protect the operators against optical radiation. Our method can be implemented at virtually no variable cost and with very low equipment costs. View full abstract»

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  • Oven Sintering Process Optimization for Inkjet-Printed Ag Nanoparticle Ink

    Page(s): 350 - 356
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1252 KB) |  | HTML iconHTML  

    This paper focuses on optimizing the oven sintering time and temperature for inkjet-printed silver nanoparticle ink on a polyimide substrate. Two basic aspects in fabricating conductor structures in printable electronics are conductivity and adhesion between the ink and the substrate material. Conductivity evolution during oven sintering is monitored with real-time resistance measurements at five different temperatures. Based on conductivity results, adhesion is evaluated at several time points at three temperatures. The higher the sintering temperature, the faster the structures reach their maximum conductivity values. The lowest conductor resistivity values are below 4 μΩ· cm. However, at each sintering temperature, it takes longer to reach the best adhesion values. In this paper, we aim to better understand oven sintering of silver nanoparticles and determine the best oven sintering conditions (temperature, time) for our particular ink-substrate combination. The results can be used to further define optimum sintering conditions for printed nanoparticle inks on polymer substrates. View full abstract»

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  • Corrections to “Terahertz Characterization of Dielectric Substrates for Component Design and Nondestructive Evaluation of Packages” [Nov 11 1685-1694]

    Page(s): 357
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    In the above titled paper (ibid., vol. 1, no. 11, pp. 1685-1694, Nov. 2011), Figs. 3(a), (b), and 5(b) are incorrect. The correct versions are presented here. View full abstract»

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  • Open Access

    Page(s): 358
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    Freely Available from IEEE

Aims & Scope

IEEE Transactions on Components, Packaging, and Manufacturing Technology publishes research and application articles on modeling, design, building blocks, technical infrastructure, and analysis underpinning electronic, photonic and MEMS packaging.

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Meet Our Editors

Managing Editor
R. Wayne Johnson
Auburn University