By Topic

Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on

Issue 12 • Date Dec 1993

Filter Results

Displaying Results 1 - 16 of 16
  • An efficient algorithm for constrained encoding and its applications

    Publication Year: 1993 , Page(s): 1813 - 1826
    Cited by:  Papers (8)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1164 KB)  

    An efficient algorithm and its implementation, ENCORE, are presented for finding approximate solutions to dichotomy-based constrained encoding, a problem fundamental to the synthesis of combinational logic circuits, and synchronous and asynchronous sequential circuits. ENCORE adopts a greedy strategy to find an encoding bit by bit, and then uses an iterative method to improve the solution quality. The novelty of the algorithm lies mainly in a linear-time heuristic to select each individual bit; this problem was previously solved in quadratic time. ENCORE has been applied to a variety of practical problem instances. For a number of examples found in the literature on the synthesis of asynchronous sequential machines, ENCORE consistently obtains optimal or near-optimal results. For the optimum state assignment of the MCNC FSM benchmarks, ENCORE generates the same or even shorter encoding lengths than the programs KISS, NOVA and DIET, but takes much less CPU time. It is demonstrated for the first time that PLA implementations of synchronous FSMs using dichotomy constraints compare very favorably with respect to area with those based on traditional group constraints View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • An efficient algorithm for bipartite PLA folding

    Publication Year: 1993 , Page(s): 1839 - 1847
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (772 KB)  

    Programmable logic arrays (PLAs) provide a flexible and efficient way of synthesizing arbitrary combinational functions as well as sequential logic circuits. They are used in both LSI and VLSI technologies. The disadvantage of using PLAs is that most PLAs are very sparse. The high sparsity of the PLA results in a significant waste of silicon area. PLA folding is a technique which reclaims unused area in the original PLA. This paper proposes a column bipartite folding algorithm based on matrix representation. Heuristics are used to reduce the search space and to speed up the search processes. The algorithm has been implemented in C programming language on a SUN-4 workstation. The program was used to study several large PLAs of varying sizes. The experimental results show that in most cases the proposed algorithm finds optimal solution in a reasonable CPU time View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Integrated circuit quality optimization using surface integrals

    Publication Year: 1993 , Page(s): 1868 - 1879
    Cited by:  Papers (16)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1048 KB)  

    A novel formulation of the parametric yield as a surface integral on the boundary of the disturbance space acceptability region is introduced. This formulation allows the accurate and efficient estimation of yield via a Monte Carlo method which can also produce yield gradients with minimal overhead. The authors extend this formulation to a more general IC quality measure. A general IC quality optimization method, significantly more efficient than Taguchi's, is introduced. This method can handle multiple performances and perform yield maximization as a special case. The optimization method is demonstrated on several circuit examples View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Computation of floating mode delay in combinational circuits: practice and implementation

    Publication Year: 1993 , Page(s): 1924 - 1936
    Cited by:  Papers (22)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (988 KB)  

    Delay computation in combinational logic circuits is complicated by the existence of unsensitizable (false) paths and this problem is arising with increasing frequency in circuits produced by high-level synthesis procedures. Various sensitization conditions have been proposed in the past to eliminate false paths in logic circuits, but the authors use a recently developed single-vector condition, that is known to be necessary and sufficient for a path to be responsible for the delay of a circuit (i.e., true) in the floating delay model. They build on this theory and develop an efficient and correct delay computation algorithm, for the floating mode delay. The algorithm uses a technique called timed-test generation and can be incorporated into any stuck-at fault test generation framework. The authors describe in detail an implementation of the timed-test generation algorithm that uses both logical and timed forward/backward implication and backtrace procedures to simultaneously prove the truth or falsity of sets of paths in the circuit. Logical and temporal conflict detection during implication and backtrace are used to speed up the algorithm. Unlike previous techniques, the algorithm remains highly efficient: even when a large number of distinct gate and path delays exist in the given circuit View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Interpolation of MOSFET table data in width, length, and temperature

    Publication Year: 1993 , Page(s): 1880 - 1884
    Cited by:  Papers (6)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (360 KB)  

    Table-based transistor modeling techniques require a current table and a charge/capacitance table for each device geometry at each simulation temperature. Simple interpolation methods can be used to construct any current table from a small basis set of tables. A database of 32 current tables (two widths, four lengths, measured at four temperatures) is sufficient to span the space defined by these sample points. The technique provides an accurate rendering of the transistor current above threshold without the need for complex parameter optimization and without the need for an exhaustive database of current tables View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Computation of floating mode delay in combinational circuits: theory and algorithms

    Publication Year: 1993 , Page(s): 1913 - 1923
    Cited by:  Papers (44)  |  Patents (4)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1064 KB)  

    Addresses the problem of accurately computing the delay of a combinational logic circuit in the floating mode of operation. (In this mode the state of the circuit is considered to be unknown when a vector is applied at the inputs.) It is well known that using the length of the topologically longest path as an estimate of circuit delay may be pessimistic since this path may be false, i.e., it cannot propagate an event. Thus, the true delay corresponds to the length of the longest true path. This forces one to examine the conditions under which a path is true. The authors introduce the notion of static cosensitization of paths which leads to necessary and sufficient conditions for determining the truth or falsity of a single path, or a set of paths. The authors apply these results to develop a delay computation algorithm that has the unique feature that it is able to determine the truth or falsity of entire sets of paths simultaneously. This algorithm uses conventional stuck-at-fault testing techniques to arrive at a delay computation method that is both correct and computationally practical, even for particularly difficult circuits View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A multiple-strength multiple-delay compiled-code logic simulator

    Publication Year: 1993 , Page(s): 1937 - 1946
    Cited by:  Papers (2)  |  Patents (10)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (996 KB)  

    Describes a new logic state model for gate level simulation based upon a powerset representation of the possible drive states at the output of a logic gate. Efficient implementation techniques for this model in a compiled-code logic simulator are presented, with the results that most complicated operations can be optimized into simple table lookups. Algorithmic issues in a multiple-strength multiple-delay logic simulator are discussed. Implementation results show that for typical circuits, compiled-code implementations of multiple-strength unit-delay logic simulation and multiple-strength multiple-delay logic simulation are slightly lower than three-state unit-delay simulation, and achieve speedups of 5 to 14 times compared to interpretive versions of the same algorithms View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A delay-based model for circuit parallelism

    Publication Year: 1993 , Page(s): 1903 - 1912
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (952 KB)  

    A new formal model for variable-delay simulators is presented for comparing the effects of time base on circuit parallelism. This model more accurately reflects current simulation strategies than previous models. Using this new model the author shows that parallelism is not a nondecreasing function of time base. She bounds parallelism, however, by two functions that converge to the unit-delay parallelism as the time base increases, preserving the intuition that coarser timing models result in greater parallelism. In addition, the author corroborates the model predictions via an empirical study and discusses the impact of the results on synchronous and conservative asynchronous parallel simulations View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A stochastic model to predict the routability of field-programmable gate arrays

    Publication Year: 1993 , Page(s): 1827 - 1838
    Cited by:  Papers (17)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1044 KB)  

    One area of particular importance is the design of an FPGA routing architecture, which houses the user-programmable switches and wires that are used to interconnect the FPGAs logic resources. Because the routing switches consume significant chip area and introduce propagation delays, the design of the routing architecture greatly influences both the area utilization and speed performance of an FPGA. FPGA routing architectures have already been studied using experimental techniques. This paper describes a stochastic model that facilitates exploration of a wide range of FPGA routing architectures using a theoretical approach. In the stochastic model an FPGA is represented as an N×N array of logic blocks separated by both horizontal and vertical routing channels, similar to a Xilinx FPGA. A circuit to be routed is represented by additional parameters that specify the total number of connections, and each connection's length and trajectory. The stochastic model gives an analytic expression for the routability of the circuit in the FPGA. Practically speaking, routability can be viewed as the likelihood that a circuit can be successfully routed in a given FPGA. The routability predictions from the model are validated by comparing them with the results of a previously published experimental study on FPGA routability View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A unified approach to floorplan sizing and enumeration

    Publication Year: 1993 , Page(s): 1858 - 1867
    Cited by:  Papers (5)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (784 KB)  

    Given a sliceable floorplan and cell sizes, Otten and Stockmeyer [1983] presented an algorithm to find an optimal implementation for each cell. The authors consider a generalized optimal sizing problem on a set of slicing trees related to an adjacency graph. For computation efficiency, they combine the tree enumeration and sizing procedures in a unified algorithm where floorplan trees and sizes are computed simultaneously. The tree enumeration is based on adjacency graph of the input cells, which ensures that the adjacency requirements of the cells are preserved. Time complexity of the algorithm is analyzed and experimental results using MCNC benchmarks are reported View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Transition fault testing for sequential circuits

    Publication Year: 1993 , Page(s): 1971 - 1983
    Cited by:  Papers (47)  |  Patents (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1136 KB)  

    Addresses the problem of simulating and generating tests for transition faults in nonscan and partial scan synchronous sequential circuits. A transition fault model for sequential circuits is first proposed. In this fault model, a transition fault is characterized by the fault site, the fault type, and the fault size. The fault type is either slow-to-rise or slow-to-fall. The fault size is specified in units of clock cycles. Fault simulation and test generation algorithms for this fault model are presented. The fault simulation algorithm is a modification of PROOFS, a parallel, differential fault simulation algorithm for stuck faults. Experimental results show that neither a comprehensive functional verification sequence nor a test sequence generated by a sequential circuit test generator for stuck faults produces a high fault coverage for transition faults. Deterministic test generation for transition faults is required to raise the coverage to a reasonable level. With the use of a novel fault injection technique, tests for transition faults can be generated by using a stuck fault test generation algorithm with some modifications. Experimental results for ISCAS-89 benchmark circuits and some AT&T designs are presented. Modifications to test generation and fault simulation algorithms required for partial scan circuits are presented. Experimental results on large benchmark circuits show that a high transition fault coverage can be achieved for the partial scan circuits designed using the cycle breaking technique View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Capacitance of top leads metal - comparison between formula, simulation, and experiment

    Publication Year: 1993 , Page(s): 1897 - 1902
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (448 KB)  

    The parasitic interconnection capacitance can significantly degrade the performance of an IC. In this paper, the parasitic capacitance of the top leads with a protective overcoat (PO) dielectric is modeled. For a nitride only PO, the nitride increases the line-to-line capacitance component by the average of the nitride and underlying oxide dielectric constants with a maximum error of 11% according to two-dimensional numerical simulations. If the oxide thickness of the PO is greater than 0.2 μm, then the line-to-ground component of capacitance will be within 10% of the value of a lead surrounded by oxide. The line-to-line component of capacitance can have an error of over 30% and a modification is required to reduce the error. Two modifications for the nitride/oxide PO are given; both increase the line-to-line capacitance by the fraction of nitride between the leads. The results of the modifications and simulation are compared to experiment. The two-dimensional simulations and formulas have a good fit to the experimental data View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A novel behavioral testability measure

    Publication Year: 1993 , Page(s): 1960 - 1970
    Cited by:  Papers (10)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (904 KB)  

    In this paper a new approach, called BETA, for computing testability is presented. The approach is based on analyzing the circuit's behavioral description: the control flow graph (CFG). Based on path analysis, testability measures are derived. Unlike a traditional testability measure which computes testability, our approach also derives the exact sequence for justifying and propagating the contents of each variable when possible. Variable classification is used to diagnose every register's controllability and observability and to classify them into several groups. Based upon this classification, guidance is provided to the test generator for each group. Variable classification is also useful in pointing out hard-to-control and hard-to-observe areas of a circuit. For fully controllable and observable variables, the best path sequence to justify and propagate these registers is generated. This approach has been implemented in a computer program and applied to several examples. All these results are verified by a CFG-based test generator and proven to be successful View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Verification of relations between synchronous machines

    Publication Year: 1993 , Page(s): 1947 - 1959
    Cited by:  Papers (1)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (992 KB)  

    Uses string function theory to develop an efficient methodology for the verification of logic implementations against behavioral specifications. First, the authors define five primitive relations between string functions, other than strict automata equivalence, namely: don't care times, parallelism, encoding, input don't care and output don't care relations. These relations have attributes, For instance, the parallelism relation has an attribute corresponding to the degree of parallelism. For each of these primitive relations, the authors derive transformations on the specification and the implementation such that the relation holds between the specification and implementation if and only if the transformed circuits exhibit the same input/output behavior. This reduces the problem of verifying primitive relations to automata equivalence checking. They enlarge the set of relations between specifications and implementations by including arbitrary compositions of the five primitive relations. To reduce the cost of verifying such a composite relation, the authors show that, given an arbitrary composite relation, a fixed order composite relation can be constructed under certain assumptions), where the primitive relations occur at most once in a predetermined order, such that the original relation holds between two machines if and only if the fixed order relation holds. For the fixed order composite relation, they derive again transformations on the specification and the implementation which reduce verifying the composite relation to performing one equivalence check. The end result is a sound and complete proof method for proving arbitrary compositions of relations by transforming the specification and the implementation and performing an equivalence check on the transformed finite state machines View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Analytical and simulation studies of failure modes in SRAMs using high electron mobility transistors

    Publication Year: 1993 , Page(s): 1885 - 1896
    Cited by:  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1060 KB)  

    Gallium arsenide memories, which are now beginning to be used commercially, are subject to certain unusual parametric faults, not normally seen in silicon or other memory devices. This paper studies the behavior of gallium arsenide high electron mobility transistor (HEMT) memories in the presence of material defects, processing errors and design errors to formulate efficient testing schemes. All defects and errors are mapped into equivalent circuit modifications and the resulting circuits are analyzed and simulated to observe the fault effects. Certain complex pattern-sensitive faults described in the testing literature are not observed at all, while certain other faults which have not been previously studied, are observed. It is shown that by slightly modifying and reordering existing test procedures, all faults in these RAMs can be tested View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Efficient via shifting algorithms in channel compaction

    Publication Year: 1993 , Page(s): 1848 - 1857
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (688 KB)  

    Considers in this paper the problem of shifting vias to obtain more compactable channel routing solutions. Let S be a grid-based two-layer channel routing solution. Let vc, wc be the number of grid points on column c that are occupied by vias, horizontal wires in S, respectively. The authors define the expected height of columns c in S to be hc=Avc+Bwc +C, where A, B, C are some design rule dependent constants. A column in S is said to be a critical column if it has maximum expected height among all columns in S. Let HS=maxchc be the expected height of the critical column(s) of S. HS is an estimation of the height of S after compaction. The authors show that the problem of shifting vias to minimize HS can be solved optimally in polynomial time View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.

Aims & Scope

The purpose of this Transactions is to publish papers of interest to individuals in the areas of computer-aided design of integrated circuits and systems.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief

VIJAYKRISHNAN NARAYANAN
Pennsylvania State University
Dept. of Computer Science. and Engineering
354D IST Building
University Park, PA 16802, USA
vijay@cse.psu.edu