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Semiconductor Manufacturing, IEEE Transactions on

Issue 1 • Date Feb. 2013

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Displaying Results 1 - 23 of 23
  • Table of contents

    Publication Year: 2013 , Page(s): C1 - C4
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  • IEEE Transactions on Semiconductor Manufacturing publication information

    Publication Year: 2013 , Page(s): C2
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  • Special Section on the 2011 Advanced Semiconductor Manufacturing Conference

    Publication Year: 2013 , Page(s): 1 - 2
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  • A Quality Metric for Defect Inspection Recipes

    Publication Year: 2013 , Page(s): 3 - 10
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (6343 KB) |  | HTML iconHTML  

    This paper describes a metric that measures the quality of defect inspection recipes. It takes into account several factors including nonvisual rate, defect of interest rate, defect count per wafer, and inspection time. The calculation runs automatically, and only minimal user input is necessary. Different weighting models allow giving each factor more or less importance, thus making the metric flexible for different applications in development and manufacturing. The result is a final score for each recipe. A list of inspection recipes can be sorted by scores to show that recipe needs optimization. Several examples show the use of the quality metric in IBM's East Fishkill development facility. View full abstract»

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  • The Evolution of Pixel Structures for Consumer-Grade Image Sensors

    Publication Year: 2013 , Page(s): 11 - 16
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (9289 KB) |  | HTML iconHTML  

    Materials integration in semiconductors, wafer fabrication process development, and device packaging have seemingly evolved at an exponential pace over the last decade. While microprocessor and memory chip manufacturers are the leading drivers of innovation, several other technology sectors benefit from the technologies that enable Moore's law scaling. Image sensor manufacturers, in particular, have realized many advancements from the selective use of advanced wafer fabrication and packaging developments. The motivations for the imaging industry to pursue advanced technology generation scaling are comparable to that of the broader semiconductor industry. In addition, image sensor companies seek a reduction of the camera module form factor, an increase in camera resolution, and an increase in pixel array performance. The pixel size of recent camera phone sensors has shrunk to 1.12 μm. This is about half the pixel size of leading edge devices of six years prior, and yet mobile imaging sensors have dramatically increased in performance. Design innovation continues to have an increasing contribution to the performance of leading edge pixels; however, to date, it has been fabrication process development that has substantially enabled the continuous breakthroughs in digital imaging. Current image sensor fabrication process flows mark a significant departure from conventional CMOS logic processes. Beyond silicon foundry processes, digital imaging companies must also concern themselves with the optical systems, packaging solutions, and image processing chips required to integrate their silicon devices with the consumer electronics supply chain. Chipworks, as a supplier of competitive intelligence to the semiconductor and electronics industries, monitors the evolution of image sensor technologies as they come into production. Chipworks has obtained charge-coupled devices and CMOS image sensor chips from leading manufacturers and performed structural, compositional,- and design analyses to benchmark the successful technologies employed by the market leaders. View full abstract»

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  • Scaling of Copper Seed Layer Thickness Using Plasma-Enhanced ALD and Optimized Precursors

    Publication Year: 2013 , Page(s): 17 - 22
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (5826 KB) |  | HTML iconHTML  

    Two recently developed precursors, AbaCus and Super AbaCus, are evaluated for use in ultralow temperature copper deposition by plasma enhanced atomic layer deposition. Film adhesion, platability, and process window evaluation demonstrate the strong capability of these precursors to overcome current metallization challenges. View full abstract»

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  • Through-Silicon-Via Fabrication Technologies, Passives Extraction, and Electrical Modeling for 3-D Integration/Packaging

    Publication Year: 2013 , Page(s): 23 - 34
    Cited by:  Papers (6)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (5958 KB) |  | HTML iconHTML  

    Major advances have been made in the processing technologies of through-silicon-vias (TSVs) because TSV is an essential element for both wafer-level 3-D integration and packaging-based 3-D integration, due to its short interconnect length, high interconnect density, and small footprint. Based on a review of current TSV technologies, this paper reports a number of recently developed extraction techniques to investigate TSV parasitics using a 3-D fullwave electromagnetic (EM) simulator, a SPICE simulator, and empirical calculations. All the TSV RLGC values extracted from the fullwave simulation are in good agreement with those from different approaches over the entire frequency range of interest. The proposed empirical calculations indicate close results to fullwave extraction, thus TSV can be accurately modeled as lump elements. A wideband SPICE model for circuit design is generated from the TSV EM solution with good matching for both magnitudes and phases of return loss and insertion loss. Sensitivity analysis results further indicate that the insulating layer thickness weighs most in signal gain at 20 GHz. As an application of the modeling approaches is developed, a novel coaxial TSV with superior electrical performance is proposed, and its latency and power are examined. This paper provides some insight into TSV electrical characteristics and physical design to maximize the benefits of 3-D systems. View full abstract»

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  • Reducing Environmentally Induced Defects While Maintaining Productivity

    Publication Year: 2013 , Page(s): 35 - 41
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (8837 KB) |  | HTML iconHTML  

    In semiconductor manufacturing, we expect the cause of defects to be process or tool related. However, at the 90 nm technology node and beyond we find that defects can be caused by issues related to the wafers' environment, such as processing of other wafers in the same tool or in the same carrier, or by seemingly innocuous actions. We pay special attention to the role of the mini-environment, which is deemed essential to achieving low particle counts for advanced technology nodes. We show defects that are caused by the environment, and some which are specifically related to the use of the mini-environment. We discuss several ways to reduce the sensitivity to environmental factors. Process and tool changes are found that eliminate yield detractors. We also present a workaround that has helped reduce the impact of queue time restrictions on cycle time. View full abstract»

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  • Characterizing the Economic Value of Organizational Learning in Semiconductor Manufacturing

    Publication Year: 2013 , Page(s): 42 - 52
    Cited by:  Papers (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (6587 KB) |  | HTML iconHTML  

    This paper describes an empirical study that assesses the economic value of various forms of organizational learning that are common in semiconductor manufacturing. This study considers three business environments: very large-scale integrated circuits, commodity components, and specialty parts with high value added. This study finds that the economic value of organizational learning varies over time, the relative economic value of different learning practices varies over time, the external economic environment strongly influences the economic value of different learning practices, the economic value of learning can be positive or negative, and the synergy between different kinds of learning can be positive or negative. The primary contribution of this paper is an empirically grounded model of organizational learning in the semiconductor manufacturing industry, which potentially enhances the profitability of semiconductor manufacturing ventures. The model helps practicing managers make investment decisions through scenario planning and identifies learning strategies that are tailored to their particular economic environment. This paper also provides insight into the structure of technological knowledge in semiconductor manufacturing, which has historically been treated as a black box. View full abstract»

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  • Impact of Recipe Restrictions on Photolithography Toolsets in an ASIC Fabrication Environment

    Publication Year: 2013 , Page(s): 53 - 68
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (8107 KB) |  | HTML iconHTML  

    In this paper, a detailed discrete event simulation model is used to better understand the effects of recipe constraints resulting from process restrictions and tool capabilities on overall average cycle time performance of a photolithography area and on average cycle times of individual mask layers. The study is motivated by the industry, in which engineers have to frequently make decisions on tool qualifications and recipe coverage. An experimental procedure is developed and implemented to show the impact of different levels of tool paths on photolithography toolsets. The simulation results show that increasing the number of tool paths decreases the overall average photolithography cycle time for particular wafer loading levels. Also, as start volumes increase, toolset utilizations increase and the impact of single-path tools on average cycle times increases. Immature processes and low-use processes tend to have more single paths and thus suffer higher average cycle times accordingly. Furthermore, it is reported that average cycle time decreases significantly under multiple process environments due to the lower impact of single paths. View full abstract»

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  • Run-to-Run Control Utilizing Virtual Metrology With Reliance Index

    Publication Year: 2013 , Page(s): 69 - 81
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (13206 KB) |  | HTML iconHTML  

    The incorporation of virtual metrology (VM) into run-to-run (R2R) control was one of the key advanced process control focus areas of the International Technology Roadmap for Semiconductors in 2009. However, a key problem preventing effective utilization of VM in R2R control is the inability to take the reliance level in the VM feedback loop of R2R control into consideration. The reason is that the result of adopting an unreliable VM value may be worse than if no VM is utilized at all. The authors have proposed the so-called reliance index (RI) and global similarity index (GSI) of VM to gauge the reliability of the VM results. This paper proposes a novel scheme of R2R control that utilizes VM with RI and GSI in the feedback loop. Simulation results of five random-generated rounds are performed. These random-generated rounds simulate the situation as if five modifications are performed on the process or the equipment due to predictive maintenances. As such, the issue of the R2R controller-gain management in real-production environment may be addressed whenever a modification is performed on the process or the equipment. View full abstract»

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  • Tool Condition Diagnosis With a Recipe-Independent Hierarchical Monitoring Scheme

    Publication Year: 2013 , Page(s): 82 - 91
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (10802 KB) |  | HTML iconHTML  

    Tool condition evaluation and prognosis has been an arduous challenge in the modern semiconductor manufacturing environment. More and more embedded and external sensors are installed to capture the genuine tool status for fault identification. Therefore, tool condition analysis based on real-time equipment data becomes not only promising but also more complex with the rapidly increased number of sensors. In this paper, the idea of generalized moving variance (GMV) is employed to consolidate the pure variations within tool fault detection and classification data into one single indicator. A hierarchical monitoring scheme is developed to generate an overall tool indicator that can coherently be drilled down into the GMVs within functional sensor groups. Therefore, we will be able to classify excursions found in the overall tool condition into sensor groups and make tool fault detection and identification more efficient. View full abstract»

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  • Lot Size Management in the Semiconductor Industry: Queueing Analysis for Cycle Time Optimization

    Publication Year: 2013 , Page(s): 92 - 99
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (4153 KB) |  | HTML iconHTML  

    In semiconductor manufacturing, production units (wafers) are transferred and processed in lots. While the current convention is a lot size of 25 wafers in semiconductor manufacturing, there has been much discussion about changing this standard to a smaller value. The principal motivation behind moving to smaller lot sizes is to decrease the average cycle time of a wafer. In this paper, we develop a simple queueing model to gain an insight into the relationship among cycle time, lot size, and the fab technology level. This analysis shows that, depending on the system parameters, moving to smaller lot sizes does not always yield cycle time improvements. View full abstract»

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  • A Petri Net-Based Novel Scheduling Approach and Its Cycle Time Analysis for Dual-Arm Cluster Tools With Wafer Revisiting

    Publication Year: 2013 , Page(s): 100 - 110
    Cited by:  Papers (15)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1414 KB) |  | HTML iconHTML  

    For some wafer fabrication processes, such as an atomic layer deposition (ALD) process, the wafers need to visit some process modules for a number of times. Using the existing swap-based strategy scheduling method in such systems leads to a 3-wafer cyclic schedule. Unfortunately, it is not optimal in the sense of cycle time. Aiming at searching for a better schedule, this paper models the system by a timed Petri net. With this model, the properties of the 3-wafer schedule are analyzed. Then, based on the analysis, it is found that, to improve the performance, it is necessary to reduce the number of wafers completed in a cycle. Hence, a 1-wafer schedule is developed by using a new swap-based strategy. By using the Petri net model, its cycle time is analyzed and shown to be optimal. Also, an effective method is presented to implement it. Illustrative examples are given to verify the research results obtained in this paper. View full abstract»

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  • Design-Aware Defect-Avoidance Floorplanning of EUV Masks

    Publication Year: 2013 , Page(s): 111 - 124
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (7898 KB) |  | HTML iconHTML  

    Fabricating defect-free mask blanks remains a major obstacle for the adoption of EUV lithography. We propose a simulated annealing based gridded floorplanner for single-project multiple-die reticles that minimize the design impact of buried defects. Our results show a substantial improvement in mask yield with this approach. For a 60-defect mask, our approach can improve the mask yield from 0% to 26%. If additional design information is available, it can be exploited for more accurate yield computation and further improvement in mask yield to 99.6%. These improvements are achieved with a limited area overhead of less than 0.2% on the exposure field. Our simulation results also indicate that around 10%-30% mask yield improvement is possible as a result of floorplanning compared to shifting the entire mask pattern. Our floorplanner can tolerate a defect position error (due to mask blank inspection tools) of 0.25 μm with just a 2% reduction in yield. The impact of defect dimensions and multilayer EUV patterning on the viability of floorplanning is also analyzed in this paper. View full abstract»

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  • Segregating Preventive Maintenance Work for Cycle Time Optimization

    Publication Year: 2013 , Page(s): 125 - 131
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (5190 KB) |  | HTML iconHTML  

    Preventive maintenance (PM) plays an essential role in keeping the equipment in control and performing in the long term in semiconductor manufacturing. However, the impact of this activity on the cycle time of a specific toolset or even the entire fab can be detrimental. Hence, there is a strong incentive for determining the best way to carry out the required PM work content so as to optimize cycle time. In this paper, a model is proposed that optimizes the number and frequency of PMs for a predetermined PM work content, with the consideration of attached setups. View full abstract»

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  • VM-Based Baseline Predictive Maintenance Scheme

    Publication Year: 2013 , Page(s): 132 - 144
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (12025 KB) |  | HTML iconHTML  

    Most conventional FDC approaches are used to find the TDs required for monitoring and the TDs' related key parameters that need to be monitored, and then apply the SPC approach to detect the faults. However, in a practical situation, an abnormal key-parameter value may not be caused solely by its own TD; it may result from the other related parameters. Therefore, accurate fault classification or diagnosis may not be achieved. Moreover, most conventional PdM methods require a library of degradation patterns from previous run-to-failure data sets. Without those massive historical failure data, the PdM methods may not function properly. In this paper, we propose a virtual-metrology- (VM) based BPM scheme that possesses the capabilities of FDC and PdM. The BPM scheme contains the TD baseline model, FDC logic, and a RUL predictive module. The TD baseline model generated by the VM technique is applied to serve as the reference for detecting the fault. By applying the BPM scheme, fault diagnosis and prognosis can be accomplished, the problem of the conventional SPC method mentioned above can be resolved, and the requirement of massive historical failure data can also be released. View full abstract»

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  • Characterization of Mass Transfer Rates and Contamination Kinetics on Silicon Wafer Surface

    Publication Year: 2013 , Page(s): 145 - 155
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (7924 KB) |  | HTML iconHTML  

    Production yield in semiconductor wafer fabrication is directly affected by low levels of molecular contamination of the silicon wafer surface. Wafers are often carried in specialized plastic enclosures, called front opening unified pods, that are continuously purged with a nitrogen flow to minimize wafer surface contamination. To improve this purge process, it is necessary to better understand the effect of mass transfer transport and kinetic processes on the silicon wafer surfaces. The experimental surface kinetics data available in the literature for diethyl phthalate were utilized, along with a validated computational fluid dynamics model to predict the relative magnitude of the time scales associated with transport and kinetics. The transport time was found to be considerably shorter than the characteristic adsorption time, and the desorption characteristic time was longer than the adsorption time. In general, surface kinetics parameters are not always known. Among other techniques, optimization techniques can be employed to calibrate the kinetic rate parameters. A multi-hierarchical model optimization technique can then be used to infer surface kinetics rates using experimentally measured concentration data for amine contamination of a wafer surface. View full abstract»

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  • Analyzing UV/Vis/NIR and Photo-Acoustic Spectra: A Note to the Band Gap of {\rm Ti}_{\rm x}{\rm Si}_{1-{\rm x}}{\rm O}_{2}

    Publication Year: 2013 , Page(s): 156 - 161
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (5316 KB) |  | HTML iconHTML  

    Exact contact-free and non-destructive opto-electrical analysis of thin film and powder materials are necessary for efficient development and improvement of semiconductor devices. Besides the quality of the apparatus, the grade of the mathematical evaluation models is of importance for correct data acquisition. For UV/Vis/NIR spectroscopy, the single-layer model and the double-layer model, taking into account transmission and reflection spectra (with an integrating sphere), have shown excellent results, compared with other measurement techniques. A further comparatively unknown and contact-free optical analysis method is the photo-acoustic spectroscopy (PAS). In the following, it will be shown that both analyzing methods provide comparable band gap energies, using just the spectra or the well-known Tauc plot, respectively, an adequate novel plot for the PAS method. For verification, the band gap energy, Eg, of a silicon powder has been investigated. Then, direct and indirect Egs of special TixSi1-xO2 compounds, x=10%,..., 50% -prepared with a sophisticated sol-gel procedure-have been analyzed. The results point out that titanium is bound mainly in TiO2 (rutil), with increasing amounts of brookite and anatase in the case of rising x-values. For Ti contents below 10%, the powder tends, reasonably, to behave like a glass substrate. View full abstract»

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  • CMOS Junctionless Field-Effect Transistors Manufacturing Cost Evaluation

    Publication Year: 2013 , Page(s): 162 - 168
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2888 KB) |  | HTML iconHTML  

    Junctionless field-effect transistors (JL-FETs) contain no doping gradients, so they are thought to be simpler to process and less costly to manufacture than fin field-effect transistors (FinFETs). To check this assertion, process flows for CMOS JL-FETs on 300 mm SOI and bulk silicon substrates with 22 nm gate length are developed, and the manufacturing costs are calculated using a cost-of-ownership based approach. It has been determined that for a given substrate, the cost of the given JL-FET process flows is comparable with FinFET processing with less than 2% cost difference, while JL-FET processing on SOI costs are greater than 10% on bulk silicon. The largest component of process cost is due to photolithography. View full abstract»

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  • Modeling of Deep Cavity Looping Process on 3-D Stacked Die Package

    Publication Year: 2013 , Page(s): 169 - 175
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (10886 KB) |  | HTML iconHTML  

    Three-dimensional (3-D) stacked die packaging can reduce cost and improve performance. It utilizes the oldest process, wire bonding, to connect chips with a large bond height difference (BHD) via deep cavity looping. This paper develops 3-D and 2-D finite element models of the process and validate them against experiments. The effects of the height difference between two bond points, reverse motion parameter, kink height parameter, and elliptic capillary traces on the process are studied. The simulations demonstrate that deep cavity looping produces greater deformation on kink II, a lower loop height, and more violent pulling on the wire than traditional looping. Optimized capillary trace parameters for traditional looping are not suitable for deep cavity looping; however, the trends in the effects of the parameters are the same. Elliptic capillary traces can change wire profiles significantly. View full abstract»

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  • Open Access

    Publication Year: 2013 , Page(s): 176
    Cited by:  Papers (1)
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    Freely Available from IEEE
  • IEEE Transactions on Semiconductor Manufacturing information for authors

    Publication Year: 2013 , Page(s): C3
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    Freely Available from IEEE

Aims & Scope

The IEEE Transactions on Semiconductor Manufacturing addresses the challenging problems of manufacturing complex microelectronic components.

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Meet Our Editors

Editor-in-Chief

Anthony Muscat
Department of Chemical and Environmental Engineering
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1133 E. James Rogers Way
University of Arizona
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