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Circuits and Systems I: Regular Papers, IEEE Transactions on

Issue 2 • Date Feb. 2013

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  • Table of contents

    Page(s): C1 - C4
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  • IEEE Transactions on Circuits and Systems—I: Regular Papers publication information

    Page(s): C2
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  • Wide Tunning Range 60 GHz VCO and 40 GHz DCO Using Single Variable Inductor

    Page(s): 257 - 267
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    This paper presents a 60 GHz, 16% tuning range VCO, and a 40 GHz, 18 bits, 14% tuning range DCO incorporating variable inductor (VID) techniques. The variable inductor, consisting of a transformer and a variable resistor, is tunable by adjusting its resistor. By employing the proposed frequency tuning scheme, wide-tuning range as well as multi-band operation are achieved without sacrificing their operating frequencies. To verify the operation principles, the VCO and DCO are both fabricated in 90 nm CMOS technology. The tuning range of VCO is from 52.2 GHz to 61.3 GHz. The measured phase noise from a 61.3-GHz carrier is about - 118.75 dBc/Hz at 10-MHz offset, and the output power is -6.6 dBm. It dissipates 8.7 mW from a 0.7-V supply, and the chip size is 0.28×0.36mm2. On the other hand, the DCO is capable of covering frequency range from 37.6 GHz to 43.4 GHz. The measured phase noise from a 43 GHz carrier is about -109 dBc/Hz at 10-MHz offset, and the output power is -11 dBm. The DCO core dissipates 19 mW from a 1.2-V supply. Chip size is 0.5×0.15mm2. View full abstract»

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  • A 1.62 Gb/s–2.7 Gb/s Referenceless Transceiver for DisplayPort v1.1a With Weighted Phase and Frequency Detection

    Page(s): 268 - 278
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    This paper proposes a 2.7 Gb/s referenceless transceiver with weighted PFD for frequency detection of random signals. A single loop referenceless CDR is also proposed to overcome the disadvantages of a dual loop CDR. The ANSI 8b/10b encoder & decoder with the scrambler, the serializer & de-serializer, and the output driver with pre-emphasis are included in the proposed transceiver architecture for DisplayPort v1.1a. The jitter of the generated clock at the Tx PLL is 3.28 psrms at 2.7 Gb/s with 1.2 V supply. The eye opening of the transmitter output with 3 m cable is 0.54 UI. The measured jitter of the recovered clock at the CDR is 1.57 psrms, and BER is less than 10-12. The receiver consumes 23 mW at 2.7 Gb/s with 1.2 V supply. The CDR core and transceiver occupy 0.07 mm2 and 0.94 mm2, respectively, in a 0.13 μm 1P8M CMOS process. View full abstract»

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  • An Analog Sub-Miliwatt CMOS Image Sensor With Pixel-Level Convolution Processing

    Page(s): 279 - 289
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    A new approach to an analog ultra-low power medium-resolution vision chip design is presented. The prototype chip performs low-level image processing algorithms in real time. Only a photo-diode, MOS switches and two capacitors are used to create an analog processing element (APE) that is able to realize any convolution algorithm based on a full 3 × 3 kernel. The proof-of-concept circuit is implemented in 0.35 μm CMOS technology, and contains a 64 × 64 SIMD matrix with embedded APEs. The matrix dissipates less than 0.3 mW (less than 0.1 W per APE) of power under 3.3 V supply, and its image processing speed is up to 100 frames/s. View full abstract»

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  • NEMS-Based Functional Unit Power-Gating: Design, Analysis, and Optimization

    Page(s): 290 - 302
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    In order to combat the exponentially growing leakage power in modern microprocessors, researchers have proposed the use of alternative power-gating structures that can yield higher leakage savings with a much lower performance impact. A prime contender is an emerging CMOS-compatible power-gating device, the nanoelectromechanical systems (NEMS) switch. Compared to transistors, NEMS switches have zero off-state leakage, so for very long periods of sleep, their effectiveness is unparalleled. For systems with periods of faster on/off rates, however, their slower switching speed, high activation energy, and finite device lifetime become drawbacks. This motivates an exploration to determine whether NEMS switches are capable of fast, fine-grained power-gating. In this article, we provide an accurate energy model of functional-unit power-gating that allows us to effectively compare transistors and NEMS switches. It is also fast enough to support the optimization of a wide variety of circuit- and system-level parameters, including supply voltage, threshold voltage, and power-gating scheduler aggressiveness. Using this framework, we show that NEMS switch power-gates along with an ideal oracle power-gating policy can achieve an average 29.5% drop in total functional unit energy, compared to only 23.5% with transistor power-gates. A more realistic hardware-based policy for NEMS switches yields a 28.9% drop, compared to a 23.0% drop with transistors. View full abstract»

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  • A 20 Gb/s Clock and Data Recovery With a Ping-Pong Delay Line for Unlimited Phase Shifting in 65 nm CMOS Process

    Page(s): 303 - 313
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    This paper describes a 20 Gb/s receiver with a DLL-based CDR, which uses a proposed Ping-Pong delay line (PPDL) in order to ameliorate the limited operating range problem of the DLL. The unlimited phase shifting algorithm with the PPDL extends the tracking range of the DLL-based CDR. The PPDL correlates two variable delay lines and swaps each other whenever one of them reaches its operational limit. The chip occupies 0.24 mm2 in 65 nm CMOS process. The power efficiency of the data transfer is 8.46 mW/Gb/s. The measured jitter of the 5 GHz clock is 1.125 psrms and the data eye opening is 0.613UI. View full abstract»

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  • Scale-Free Hyperbolic CORDIC Processor and Its Application to Waveform Generation

    Page(s): 314 - 326
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    This paper presents a novel completely scaling-free CORDIC algorithm in rotation mode for hyperbolic trajectory. We use most-significant-1 bit detection technique for micro-rotation sequence generation to reduce the number of iterations. By storing the sinh/cosh hyperbolic values at octant boundaries in a ROM, we can extend the range of convergence to the entire coordinate space. Based on this, we propose a pipeline hyperbolic CORDIC processor to implement a direct digital synthesizer (DDS). The DDS is further used to derive an efficient arbitrary waveform generator (AWG), where a pseudo-random number generator modulates the linear increments of phase to produce random phase-modulated waveform. The proposed waveform generator requires only one DDS for generating variety of modulated waveforms, while existing designs require separate DDS units for different type of waveforms, and multiple DDS units are required to generate composite waveforms. Therefore, area complexity of existing designs gets multiplied with the number of different types waveforms they generate, while in case of proposed design that remains unchanged. The proposed AWG when mapped on Xilinx Spartan 2E device, consumes 1076 slices and 2016 4-input LUTs. The proposed AWG involves significantly less area and lower latency, with nearly the same throughput compared to the existing CORDIC-based designs. View full abstract»

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  • A Low-Latency Low-Power QR-Decomposition ASIC Implementation in 0.13 \mu{\rm m} CMOS

    Page(s): 327 - 340
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    This paper presents a hybrid QR decomposition (QRD) design that reduces the number of computations and increases their execution parallelism by using a unique combination of Multi-dimensional Givens rotations, Householder transformations and conventional 2-D Givens rotations. A semi-pipelined semi-iterative architecture is presented for the QRD core, that uses innovative design ideas to develop 2-D, Householder 3-D and 4-D/2-D configurable CORDIC processors, such that they can perform the maximum possible number of vectoring and rotation operations within the given number of cycles, while minimizing gate count and maximizing the resource utilization. Test results for the 0.3 mm2 QRD chip, fabricated in 0.13 μm 1P8M CMOS technology, demonstrate that the proposed design for 4×4 complex matrices attains the lowest reported processing latency of 40 clock cycles (144 ns) at 278 MHz and dissipates 48.2 mW at 1.3 V supply and 25°C. It outperforms all of the previously published QRD designs by offering the highest QR processing efficiency. View full abstract»

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  • Stability and Stabilization for Markovian Jump Time-Delay Systems With Partially Unknown Transition Rates

    Page(s): 341 - 351
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    This paper focuses on the stability analysis and controller synthesis of continuous-time Markovian jump time-delay systems with incomplete transition rate descriptions. A general stability criterion is formulated first for state- and input-delay Markovian jump time-delay systems with fully known transition rates. On the basis of the proposed condition, an equivalent condition is given under the assumption of partly known/unknown transition rates. A new design technique based on a projection inequality has been applied to design both state feedback and static output feedback controllers. All conditions can be readily verified by efficient algorithms. Finally, illustrative examples are provided to show the effectiveness of the proposed approach. View full abstract»

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  • Finite-Time Distributed Tracking Control for Multi-Agent Systems With a Virtual Leader

    Page(s): 352 - 362
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    This paper aims at further investigating the finite-time distributed tracking control problems for multi-agent systems with a virtual leader under the conditions of fixed and switching topologies, respectively. Two continuous distributed tracking protocols are designed for tracking the virtual leader in finite time. Compared with the traditional distributed tracking protocols, the proposed distributed tracking protocols can reach consensus in finite time. In particular, to eliminate the chattering phenomenon occurred in non-Lipschitz dynamical systems, this paper introduces a saturation function to replace the original sign function in the proposed distributed tracking protocols. The improved protocols can guide all agents to track the virtual leader without chattering phenomenon in finite time for the same position. Numerical simulations are also given to validate the proposed distributed tracking protocols. View full abstract»

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  • Synchronization of Randomly Coupled Neural Networks With Markovian Jumping and Time-Delay

    Page(s): 363 - 376
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    This paper studies synchronization in an array of coupled neural networks with Markovian jumping and random coupling strength. The array of neural networks are coupled in a random fashion which is governed by Bernoulli random variable and each node has an interval time-varying delay. By designing a novel Lyapunov functional, using some inequalities and the properties of random variables, several delay-dependent synchronization criteria are derived for the coupled networks of continuous-time version. Discrete-time analogues of the continuous-time networks are also formulated and studied. Some new lemmas are developed to obtain less conservative synchronization criteria of both continuous-time model and its discrete-time analogues. Numerical examples of both continuous-time system and its discrete-time analogues are finally given to demonstrate the effectiveness of the theoretical results. View full abstract»

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  • Stability of Coupled Local Minimizers Within the Lagrange Programming Network Framework

    Page(s): 377 - 388
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    Coupled local minimizers (CLMs) turn out to be a potential global optimization strategy to explore a search space, avoid overfitting and produce good generalization. In this paper, convergence properties of CLMs based on an augmented Lagrangian function in the context of equality constrained minimization, are studied. We first consider the augmented Lagrangian by taking the objective of minimizing the average cost of an ensemble of local minimizers subject to pairwise synchronization constraints. Then we study an array of CLMs within the Lagrange programming network framework and analyze the local stability of CLMs using a linearization strategy. We further show that, under some mild conditions, global asymptotical stability of the unique equilibrium point of the network can be guaranteed. Afterwards, some sufficient conditions are presented to ensure the stability of synchronization between any two minimizers via a directed graph method. The results show that the CLMs usually can be synchronized if the penalty factors in the array of CLMs are chosen large enough. It is worth pointing out that CLMs possess the capability of global exploration in the search space and the advantage of faster running time on convex problems in comparison with most of the neural network approaches, which is also illustrated through two test functions and their numerical simulations. View full abstract»

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  • Stabilization of Discrete-Time Systems With Multiple Actuator Delays and Saturations

    Page(s): 389 - 400
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    This paper studies the problems of global and semi-global stabilization of discrete-time linear systems with multiple input saturations and arbitrarily large bounded delays. By developing the methodology of truncated predictor feedback (TPF), state feedback control laws using only the current states of the systems are constructed to solve these problems. The feedback gains are dependent on the delay information of the open-loop system and thus are referred to as delay-dependent feedback. A method for determining the exact condition such that the resulting closed-loop system is asymptotically stable is also presented. Moreover, if the delays in the system are time-varying or even unknown, a modified delay-independent TPF is also established to solve the concerned problems. Numerical example has been worked out to illustrate the effectiveness of the proposed approaches. View full abstract»

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  • Robust Information Fusion Estimator for Multiple Delay-Tolerant Sensors With Different Failure Rates

    Page(s): 401 - 414
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    In this paper, the robust information fusion Kalman filtering problem is considered for multi-sensor systems with parameter uncertainties, randomly delayed measurements and sensor failures. The stochastic parameter perturbations are included in the state space models such that the proposed fusion estimator has robustness for the varying system parameters. For each observation subsystem, multiple binary random variables with known probabilities are introduced to model sensor failures and random delays in the measurements. Without resorting to the augmentation of system states and measurements, a robust optimal recursive filter for each subsystem is derived in the linear minimum variance sense by using the innovation analysis method, and the estimation error cross-covariance matrix between any two subsystems is given recursively. Based on the optimal fusion algorithm weighted by matrices, a robust distributed state fusion Kalman filter is derived for the considered system, and the dimension of the designed filter is the same as the original system, which can reduce computation costs as compared with the augmentation method. Moreover, the performance of the designed fusion filter is dependent on the sensor failure rates. Finally, two illustrative examples are given to show the effectiveness of the proposed method. View full abstract»

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  • Aliasing-Free Digital Pulse-Width Modulation for Burst-Mode RF Transmitters

    Page(s): 415 - 427
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    Burst-mode operation of power amplifiers (PAs) is a promising concept towards higher power efficiency in radio frequency (RF) transmitters. Such transmitters use pulse-width modulation (PWM) to create the driving signal for the PA, and a reconstruction filter after amplification to obtain the transmission signal. However, conventional digital pulse-width modulated signals contain a large amount of distortion that cannot be removed by the reconstruction filter in a satisfactory manner. View full abstract»

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  • A CMOS Switched Load Harmonic Rejection Mixer for DTV Tuner Applications

    Page(s): 428 - 436
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    In this paper, a switched load harmonic rejection mixer (HRM) structure with one single mixer core and a pair of switched load resistors is proposed. Different from the traditional three-phase HRM which is widely used in DTV tuners, this HRM performs the harmonic rejection function by vector multiplication rather than superposition. Sharing most of its parts with an ordinary Gilbert mixer, the proposed HRM shows greater simplicity in structure. The single mixer-core structure is also more power efficient than a traditional three-phase HRM. In order to verify the effectiveness of this approach, a proof-of-concept prototype is designed and fabricated in 0.18- μm RFCMOS technology. Measurements indicate that 38 dB for 3rd and 34.5 dB for 5th harmonic rejection ratio can be achieved. The HRM including a buffer stage consumes a low bias current of 3 mA under 1.8 V supply voltage and has equivalent performance such as CG, NF, and IIP3 to an ordinary Gilbert mixer. With the load switch inactivated, this HRM can be easily transformed into an ordinary Gilbert mixer, which increases its flexibility for different applications. View full abstract»

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  • A 2.4-GHz Low-Flicker-Noise CMOS Sub-Harmonic Receiver

    Page(s): 437 - 447
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    A 2.4-GHz low-noise sub-harmonic direct-conversion receiver (SH-DCR) is demonstrated using standard 0.18-μm CMOS technology. Deep-n-well vertical-NPN (V-NPN) bipolar junction transistors (BJTs) are employed to solve the flicker noise problem in CMOS process. Design optimization of a power-constrained noise-impedance-matched low-noise amplifier (LNA) with the effect of lossy on-chip inductors is fully discussed in this paper. A multi-stage octet-phase polyphase filter is analyzed in detail and implemented to generate well balanced octet-phase LO signals. As a result, the demonstrated receiver achieves 51-dB voltage gain and 3-dB noise figure with flicker noise corner less than 30 kHz when RF = 2.4 GHz. The I/Q amplitude/phase mismatch is below ±0.2 dB/±1°, respectively, covering from 2.35 to 2.6 GHz. The dc current consumption is 5 mA at a 1.8-V supply. View full abstract»

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  • Wideband Receiver for a Three-Dimensional Ranging LADAR System

    Page(s): 448 - 456
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    A low-noise, high-gain, wide-linear-dynamic-range, wide-band receiver for a pulsed, direct, three-dimensional ranging LADAR system has been designed and implemented in a 0.13 μm CMOS technology. Specific design techniques, including gain control scheme to widen linear dynamic range, gain allocating between blocks and noise minimization to improve SNR, frequency response compensation to extend bandwidth and ensure system stability, and output voltage swing boosting, have been proposed to achieve challenging design goals with linear dynamic range of 1:1600, equivalent input-referred current noise of less than 5.6 pA/√Hz, high gain of 78 dBΩ, maximum output swing of at least 500 mV, bandwidth of at least 500 MHz, and low sensitivity to temperature variation over the range from -10°C to 60°C, in the presence of 2 pF photodiode parasitic capacitance. View full abstract»

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  • A 0.18-/spl mu/m CMOS 10-Gb/s Dual-Mode 10-PAM Serial Link Transceiver

    Page(s): 457 - 468
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    A 0.18-μm CMOS 10-Gb/s serial link transceiver is presented. For the power-efficiency, the transceiver employs a dual-mode 10-level pulse amplitude modulation (10-PAM) technique enabling to transmit 4-bit per symbol. Since the operating frequency of the internal circuits is reduced by 4, the power dissipation of the transceiver is much reduced. In addition, compared with a standard 16-PAM technique, the dual-mode 10-PAM technique can reduce power dissipation by 62.5%. The transmitter including a pseudo random bit sequence (PRBS) generator, multiplexers, an encoder, and an output driver achieves 10-Gb/s data-rate with 235-mW power dissipation such that the figure of merit (FOM) of the transmitter part is 23.5 mW/(Gb/s). The receiver including a flash type analog-to-digital converter (ADC), a decoder, and output drivers achieves 10-Gb/s data-rate and 10-12 BER with 190-mW power dissipation such that FOM of the receiver part is 19 mW/(Gb/s). The proposed 10-PAM transceiver was implemented in a 0.18-μm standard CMOS technology with 0.3 × 0.8-mm2 active area. View full abstract»

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  • A 45-nm SOI CMOS Integrate-and-Dump Optical Sampling Receiver

    Page(s): 469 - 478
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    An integrate-and-dump receiver based on an active feedback integrator is demonstrated in a 45-nm SOI CMOS process. The integrate-and-dump receiver provides matched filtering for non-return-to-zero, return-to-zero, and pulse amplitude modulation digital modulation formats, resulting in high SINAD as well as inherent anti-aliasing/low-pass filtering for a 2 GS/s high linearity/high-dynamic-range optical sampling receiver. The measured SINAD is greater than 28 dBc with a sinusoidal input up to 1 GHz; the SNR is greater than 29 dBc. The 2-GS/s integrate-and-dump receiver consumes less than 100 mW. The chip area is 0.980×0.762 mm2 including the pads. View full abstract»

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  • Analysis of Switching Circuits Through Incorporation of a Generalized Diode Reverse Recovery Model Into State Plane Analysis

    Page(s): 479 - 490
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    A new switching circuit analysis technique is proposed in which the reverse recovery and junction capacitance non-idealities of diode-based switches are incorporated into a state plane analysis of the circuit. Accurate state plane modeling of the reverse recovery process is based on the development of new generalizations of the classic charge control model. Using as an example a zero-voltage switching dc transformer possessing high sensitivity to diode characteristics, these generalizations are shown to be necessary to achieve accurate results across all operating modes. The proposed circuit analysis technique produces excellent modeling agreement with results measured on a hardware prototype of the dc transformer circuit. View full abstract»

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  • Dimensionless Approach to Multi-Parametric Stability Analysis of Nonlinear Time-Periodic Systems: Theory and Its Applications to Switching Converters

    Page(s): 491 - 504
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    This paper proposes a dimensionless approach to analyze the multi-parametric stability behavior of switching converters, which can be characterized by a nonlinear time-periodic (NTP) system. The main objective is to analyze how multiple circuit parameters affect the stability patterns of the derived NTP system and to simplify the parametric complexity of such NTP system. In contrast to previous work, the proposed method focuses on the parametric resultant relationships of the NTP system in the sense of topological equivalence, and investigates its stability in terms of the homeomorphic NTP system. Firstly, an equivalent stability theory of NTP systems is proposed. Then, based on the equivalent theory, a normalized map is introduced and various interesting properties are derived so as to formulate the dimensionless approach. Moreover, the approximate solution of the NTP system in dimensionless parameter space is calculated by using the Galerkin method, and its stability pattern is identified with the help of eigenvalue analysis approach. Finally, a case study of one-cycle controlled Zeta PFC converter is discussed in detail to exemplify the application of the proposed method. These analytical results agree well with those ones obtained from experimental measurements. View full abstract»

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  • Design of PWM Ramp Signal in Voltage-Mode CCM Random Switching Frequency Buck Converter for Conductive EMI Reduction

    Page(s): 505 - 515
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    An output voltage ripple aware design of different voltage ramp signal of voltage-mode CCM random frequency buck converter for conductive EMI reduction is presented. A mathematical analysis has been carried out to model the output voltage ripple of random switching converter. Simulations of the converter have been undertaken and measured results from the converter fabricated with a standard 0.35 μm CMOS process verify the proposed design approach. From experimental results, a carefully designed ramp can reduce the output voltage ripple by more than 8 times without significant influence on the inductor current spectrum spread and any increment on the output filtering inductance and capacitance comparing to the conventional design. View full abstract»

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  • IEEE Transactions on Circuits and Systems—I: Regular Papers information for authors

    Page(s): 516
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Aims & Scope

The theory, analysis, design, and practical implementations of circuits, and the application of circuit techniques to systems and to signal processing.

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Editor-in-Chief
Shanthi Pavan
Indian Institute of Technology, Madras