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Electron Devices, IEEE Transactions on

Issue 2 • Date Feb. 2013

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Displaying Results 1 - 25 of 62
  • Front cover

    Page(s): C1
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  • IEEE Transactions on Electron Devices publication information

    Page(s): C2
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  • Table of contents

    Page(s): 521 - 523
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  • A Warm Welcome to a New T-ED Editor

    Page(s): 524
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  • Special Issue on Advanced Modeling of Power Devices and Their Applications

    Page(s): 525 - 527
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  • Role of Simulation Technology for the Progress in Power Devices and Their Applications

    Page(s): 528 - 534
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1328 KB) |  | HTML iconHTML  

    The modern power electronics era started with the commercialization of the silicon-controlled rectifier in 1957, since when power electronics systems have been installed in a wide range of applications from appliances to traction and utility systems as the technology has advanced. Meanwhile, simulation tools have played an important role in the research and development of power semiconductors and power electronics systems. As power devices and power electronics become increasingly important technologies in today's electric society, it is worth examining the overall integration of power electronics design. This paper reviews the history of simulation technology with reference to power device modeling and discusses the future of power electronics system design. View full abstract»

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  • Analytical Modeling of IGBTs: Challenges and Solutions

    Page(s): 535 - 543
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (808 KB) |  | HTML iconHTML  

    With the availability of advanced computing capability, it is fashionable to analyze and design insulated-gate bipolar transistors (IGBTs) using sophisticated 2-D and 3-D numerical simulation tools. However, analytical modeling of IGBTs allows a deeper understanding of the physics of operation, which can foster innovation. This paper reviews 1-D analytical models developed for the IGBT on-state characteristics, switching behavior, and safe operating area for symmetric (nonpunchthrough) and asymmetric (punchthrough) devices. View full abstract»

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  • Application of Electrical Circuit Simulations in Hybrid Vehicle Development

    Page(s): 544 - 550
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    This paper describes the application of electrical circuit simulations in intelligent power module development for hybrid vehicles, electric vehicles, and fuel cell vehicles. The limitations of the conventional design and simulation systems are discussed, and efforts for overcoming these limitations are described. The introduction of a physics-based insulated-gate-bipolar-transistor model with a surface-potential MOSFET core into the design flow is described. Finally, future expectations for necessary simulation technology development are given. View full abstract»

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  • Limiting Factors of the Safe Operating Area for Power Devices

    Page(s): 551 - 562
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    This paper gives an overview about different failure mechanisms which limit the safe operating area of power devices. It is demonstrated how the device internal processes can be investigated by means of device simulation. For instance, the electrothermal simulation of high-voltage diode turn-off reveals how a backside filament transforms into a continuous filament connecting the anode and cathode and how this can be accompanied with a transition from avalanche-induced into thermally driven carrier generation. A similar current destabilization may occur during insulated-gate bipolar transistor turn-off with a high turn-off rate, when the channel is closed quickly leading to strong dynamic avalanche. It is explained how the current filamentation depends on substrate resistivity, device thickness, channel width, and switching conditions (gate resistor and overcurrent). Filamentation processes during short-circuit events are discussed, and possible countermeasures are suggested. A mechanism of a periodically emerging and vanishing filament near the edge of the chip is presented. Examples on current destabilizing effects in gate turn-off thyristors, integrated gate-commutated thyristors, and metal-oxide-semiconductor field-effect transistors are given, and limitations of current device simulation are discussed. View full abstract»

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  • Experimental Detection and Numerical Validation of Different Failure Mechanisms in IGBTs During Unclamped Inductive Switching

    Page(s): 563 - 570
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1331 KB) |  | HTML iconHTML  

    The physics of the different failure modes that limit the maximum avalanche capability during unclamped inductive switching (UIS) in punchthrough (PT) and not PT (NPT) insulated-gate bipolar transistor (IGBT) structures is analyzed in this paper. Both 3-D electrothermal numerical simulations and experimental evaluations support the theoretical analysis. Experimental results for UIS test show that, at low time duration (or inductance value) of the test, the UIS limit moves from energy limitation to current limitation. While the energy limitation is well known, the current-limited failures are less studied. In this paper, the current limit for UIS test is analyzed in detail, and the cause is attributed to a filamentary current conduction due to the presence of a negative differential resistance (NDR) region in the IC- VCE curve in breakdown. The filamentary current conduction locally increases the current density causing early device latch-up and possible device failure at a current much lower than the one dictated by energy limitations. The physical parameters that affect both the onset of NDR region and the failure current are discussed for both an NPT trench IGBT structure with a local lifetime control and a PT trench IGBT structure with a field-stop layer. View full abstract»

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  • HiSIM-IGBT: A Compact Si-IGBT Model for Power Electronic Circuit Design

    Page(s): 571 - 579
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2015 KB) |  | HTML iconHTML  

    A physics-based compact model of insulated-gate bipolar transistors (IGBTs) for power electronic circuit simulation is presented. The compact model is constructed as a combination of a metal-oxide-semiconductor field-effect transistor (MOSFET) part and a bipolar junction transistor (BJT) part with a conductivity-modulated base resistance in between them and is named “HiSIM-IGBT.” The model considers the potential distribution from the MOSFET channel to the two BJT junctions explicitly by solving important internal node potentials self-consistently. The IGBT output current at the collector terminal is governed by the base resistance of the bipolar part and the MOSFET characteristics, which is confirmed to be described accurately. The model is verified to accurately reproduce measured transient behaviors of switching test circuits which are basic components of practically used power electronic circuits. View full abstract»

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  • A Sequential Model Parameter Extraction Technique for Physics-Based IGBT Compact Models

    Page(s): 580 - 586
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1054 KB) |  | HTML iconHTML  

    A sequential parameter extraction technique describing the fitting targets and related parameters for compact insulated-gate bipolar transistor (IGBT) models is presented. Using 2-D device simulation data for a trench-type IGBT as reference, the performance of HiSIM-IGBT as an example of a compact IGBT model is compared to an IGBT macromodel. Parameter extraction with the compact model is fast and straightforward, owing to its physics-based modeling. Even with minimal extraction effort, the compact model fits the dc current and capacitance and reproduces the transient turnoff characteristics accurately. View full abstract»

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  • Modeling of Soft-Switching Losses of IGBTs in High-Power High-Efficiency Dual-Active-Bridge DC/DC Converters

    Page(s): 587 - 597
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    Soft-switching techniques are very attractive and often mandatory requirements in medium-voltage and medium-frequency applications such as solid-state transformers. The effectiveness of these soft-switching techniques is tightly related to the dynamic behavior of the internal stored charge in the utilized semiconductor devices. For this reason, this paper analyzes the behavior of the internal charge dynamics in high-voltage (HV) semiconductors, giving a clear base to perform overall converter optimizations and to understand the previously proposed zero-current-switching techniques for insulated-gate bipolar-transistor (IGBT)-based resonant dual active bridges. From these previous approaches, the two main concepts that allow switching loss reduction in HV semiconductors are identified: 1) shaping of the conducted current in order to achieve a high recombination time in the previously conducting semiconductors; and 2) achieving zero-voltage-switching (ZVS) in the turning-on device. The means to implement these techniques in a triangular-current-mode dual-active-bridge converter, together with the benefits of the proposed approaches, are analyzed and experimentally verified with a 1.7-kV IGBT-based neutral-point-clamped (NPC) bridge. Additionally, the impact of the modified currents in the converter's performance is quantified in order to determine the benefits of the introduced concepts in the overall converter. View full abstract»

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  • Layout Role in Failure Physics of IGBTs Under Overloading Clamped Inductive Turnoff

    Page(s): 598 - 605
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1323 KB) |  | HTML iconHTML  

    The clamped inductive turnoff failure of nonpunchthrough insulated-gate bipolar transistors (IGBTs) is investigated under overcurrent and overtemperature events. First, their electrical and physical signatures are experimentally determined. Second, physical TCAD simulations are carried out considering the current mismatch among the cells from the chip core, gate runner, and edge termination areas. As a result, a secondary breakdown of the IGBT periphery cells at the edge of the gate runner has been identified to be responsible for the failure. View full abstract»

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  • Accurate Power Circuit Loss Estimation Method for Power Converters With Si-IGBT and SiC-Diode Hybrid Pair

    Page(s): 606 - 612
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    An accurate power circuit loss estimation method has been developed for designing power converters with hybrid pairs of silicon (Si) insulated-gate bipolar transistor (Si-IGBT) and silicon carbide (SiC) Schottky barrier diode/SiC p-i-n diode. An analytical model of the switching losses of the hybrid pairs is proposed to achieve high accuracy and short calculation time. The nonlinearity of the device parameters and the stray inductance in the circuit are considered in the model. For the accurate power loss calculation, an empirical parameter extraction method is introduced for extracting device parameters. The calculated circuit power losses are compared with measurement results, and good agreements are confirmed. By using the proposed method, the power loss of a power converter utilizing 4.5-kV Si-IGBT/SiC-p-i-n-diode hybrid pairs is estimated to investigate the upper limitation of the switching frequency. View full abstract»

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  • Physical Models for SiC and Their Application to Device Simulations of SiC Insulated-Gate Bipolar Transistors

    Page(s): 613 - 621
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    Important physical models for 4H silicon carbide (4H-SiC) are constructed based on the literature and experiments on the physical properties of 4H-SiC. The obtained physical models are implemented into a commercial device simulator, which is used for examining the potential performance of SiC insulated-gate bipolar transistors (IGBTs). Device simulation using these new physical models shows that the forward characteristics of the conventional type of planar SiC IGBTs are significantly poorer than those of SiC p-i-n diodes, even if the carrier lifetime is improved. It is shown that the degradation in the characteristics of the conventional SiC IGBT is caused by the limited conduction modulation at the cathode side of the n-base layer. We show that this problem can be resolved by applying device structures that induce a hole-barrier effect in the SiC IGBTs. View full abstract»

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  • Modeling of SiC IGBT Turn-Off Behavior Valid for Over 5-kV Circuit Simulation

    Page(s): 622 - 629
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1779 KB) |  | HTML iconHTML  

    This paper presents a compact model of SiC insulated-gate bipolar transistors (IGBTs) for power electronic circuit simulation. Here, we focus on the modeling of important specific features in the turn-off characteristics of the 4H-SiC IGBT, which are investigated with a 2-D device simulator, at supply voltages higher than 5 kV. These features are found to originate from the punch-through effect of the SiC IGBT. Thus, they are modeled based on the carrier distribution change caused by punch through and implemented into the silicon IGBT model named “HiSIM-IGBT” to obtain a practically useful SiC-IGBT model. The developed compact SiC-IGBT model for circuit simulation is verified with the 2-D device simulation data. View full abstract»

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  • Behavioral Approach to SiC MPS Diode Electrothermal Model Generation

    Page(s): 630 - 638
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (671 KB) |  | HTML iconHTML  

    A comprehensive approach to generation of electrothermal models of silicon carbide (SiC) power Schottky diodes is presented. Both the electrical and thermal parts of the model are behavioral. The electrical one was developed in order to accurately represent the nonlinear properties of SiC merged PiN Schottky (MPS) diodes. Its parameters are automatically obtained with a dedicated numerical procedure. The thermal model derivation differs from the earlier approaches because it is based on the analysis of thermal constant spectrum of the temperature response of a modeled device. Simple model generation and parameter extraction procedures are proposed in which no knowledge of technological data is necessary. View full abstract»

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  • A Compact Physical AlGaN/GaN HFET Model

    Page(s): 639 - 645
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    We introduce a physics-based compact model for AlGaN/GaN heterojunction field-effect transistors (HFETs) that is suitable for both RF microwave and switched-mode power supply (SMPS) applications, so that RF techniques can help determine HFET performance in SMPS applications. Such simulations can predict the on-resistance, slew rate, and breakdown voltage from the physical design of the transistor. Starting from an expression for the drain-source conduction current, charge distribution and displacement current are determined. The new model was implemented in Verilog-A and implemented in AWRDE, the design environment from Applied Wave Research. The HFET model was validated by comparison with Silvaco simulations and with data from an AlGaN/GaN HFET S-band amplifier. The new model accurately predicts device performance for dc, small-signal, and large-signal operations. View full abstract»

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  • GaN Power Transistor Modeling for High-Speed Converter Circuit Design

    Page(s): 646 - 652
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1143 KB) |  | HTML iconHTML  

    A circuit simulator has been developed to design power losses of high-frequency power converters using GaN-based heterojunction field-effect transistors (GaN-HFETs). The simulator is based on a high-accuracy equivalent model of GaN-HFETs with peculiar device physics and high-speed loss calculation methods. The simulated power losses were consistent with measured results in dc-dc converters constructed by a GaN-HFET and a SiC Schottky diode with more than 93% accuracy. By utilizing the developed simulator, key requirements in heat-dissipation technologies, circuit parasitic inductances, and gate-drive technologies for next-generation converters are discussed. View full abstract»

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  • The Second-Generation of HiSIM_HV Compact Models for High-Voltage MOSFETs

    Page(s): 653 - 661
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1928 KB) |  | HTML iconHTML  

    This paper reviews the industry-standard surface-potential-based compact model HiSIM_HV for high-voltage MOSFETs, as, e.g., the lateral double-diffused MOS transistor, and introduces important improvements implemented in the second-generation model versions (HiSIM_HV2), for which open source code has been released since October 2011. HiSIM_HV solves the Poisson equation consistently within the intrinsic MOSFET, i.e., the gate-drift overlap region and the drain-side part of the drift region. Excess carrier concentrations in the drift region are accurately considered together with the velocity saturation effect. These modeling concepts enable a scalable compact model formulation with only one internal node. Fulfillment of the current continuity between MOSFET and drift parts is required for determining the internal node potential. An important enhancement implemented in the HiSIM_HV2 models is a physically accurate compact drift region resistance model, which captures the effects of the structure-dependent 2-D current flows in overlap and drift regions with their complicated bias dependence. Furthermore, compact modeling of gate overlap capacitance, leakage currents due to, e.g., impact ionization, self-heating, noise, and symmetry properties (smooth derivatives at zero drain-source voltage) have been substantially improved. View full abstract»

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  • An Accurate and Robust Compact Model for High-Voltage MOS IC Simulation

    Page(s): 662 - 669
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1332 KB) |  | HTML iconHTML  

    This paper presents an accurate and robust compact model for high-voltage MOS (HV-MOS) transistors for high-voltage IC simulation. This model describes the extended-drain MOS and lateral double-diffused HV-MOS effects such as quasi-saturation, gm reduction, self-heating, impact ionization, output conductance, and charge/capacitance effects accurately. In addition, the quasi-saturation effects are, for the first time, illustrated with a simple mathematic formulation. This model is developed with BSIM4 as the base and validated extensively with technology computer-aided design and measurement for wide ranges of power supplies and operating temperatures. View full abstract»

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  • Measurement and Compact Modeling of 1/f Noise in HV-MOSFETs

    Page(s): 670 - 676
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1100 KB) |  | HTML iconHTML  

    This paper investigates 1/f noise behavior under low and high drain biases of high-voltage metal-oxide-semiconductor field-effect transistors (MOSFETs) (HV-MOSFETs). A dedicated setup is presented which allows measuring low-frequency (LF) noise of lateral double-diffused MOSFETs (LDMOSFETs) up to 200 V at the drain. LF noise spectra of n- and p-channel LDMOSFETs were measured over a large range of gate and drain bias conditions and modeled using a recently established physics-based compact model of HV-MOSFETs. The investigated devices confirm that the overall noise is mostly dominated by the noise originating in the channel, while the drift-region-generated noise only is apparent in linear operation. View full abstract»

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  • A Physics-Based Analytical \hbox {1}/f Noise Model for RESURF LDMOS Transistors

    Page(s): 677 - 683
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1396 KB) |  | HTML iconHTML  

    A physics-based model has been implemented to describe the low-frequency noise behavior in differently processed reduced-surface-field lateral double-diffused MOS devices. The developed model is based upon the correlated carrier number and the mobility fluctuation theory known as the unified model but has been modified to account for the fluctuations in the extended drain and the channel. Unlike the unified 1/f noise model, nonuniform trap distribution has been taken into account with respect to position in the gate oxide and band-gap energy. The effect of stress on dc and noise characteristics has been investigated. Individual resistance and noise components in the channel and in the extended drain regions under the gate and field oxides are evaluated as a function of stress duration. The model is experimentally verified to identify the physical mechanisms for degradation due to stressing. View full abstract»

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  • Modeling of the Impurity-Gradient Effect in High-Voltage Laterally Diffused MOSFETs

    Page(s): 684 - 690
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1471 KB) |  | HTML iconHTML  

    MOSFET capacitance values in high-voltage laterally diffused MOSFETs, including the channel impurity concentration, which tails off along the channel from the source side to the drain side, are investigated. This pertinent doping inhomogeneity of the intrinsic MOSFET channel induces an additional electrostatic contribution to the amount of internal charges. With an emphasis on the deviations from homogeneous impurity-profile settings, the additional contribution was formulated within the framework of compact MOSFET models based on the surface-potential description. The developed capacitance-model enhancement requires a solution for the drain-side potentials at two uniform impurity concentrations, each of which corresponds to the source-side and the drain-side concentration of the impurity profile with gradient, respectively. The developed approach is found successful for all drain-source voltages, where the resulting high-voltage MOSFET-specific features are observed. View full abstract»

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Aims & Scope

IEEE Transactions on Electron Devices publishes original and significant contributions relating to the theory, modeling, design, performance and reliability of electron and ion integrated circuit devices and interconnects.

 

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Meet Our Editors

Editor-in-Chief
John D. Cressler
School of Electrical and Computer Engineering
Georgia Institute of Technology