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Very Large Scale Integration (VLSI) Systems, IEEE Transactions on

Issue 2 • Date Feb. 2013

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Table of Contents

IEEE Transactions on Very Large Scale Integration (VLSI) Systems publication information

Application Space Exploration of a Heterogeneous Run-Time Configurable Digital Signal Processor

A Unified Graphics and Vision Processor With a 0.89 $\mu$ W/fps Pose Estimation Engine for Augmented Reality

CORDIC Designs for Fixed Angle of Rotation

Application-Driven End-to-End Traffic Predictions for Low Power NoC Design

Thermal-Constrained Task Allocation for Interconnect Energy Reduction in 3-D Homogeneous MPSoCs

A Wide-Range PLL Using Self-Healing Prescaler/VCO in 65-nm CMOS

A Clock Control Strategy for Peak Power and RMS Current Reduction Using Path Clustering

A Fast-Locking All-Digital Deskew Buffer With Duty-Cycle Correction

A Built-In Repair Analyzer With Optimal Repair Rate for Word-Oriented Memories

System-Level Modeling and Analysis of Thermal Effects in Optical Networks-on-Chip

A Study of Tapered 3-D TSVs for Power and Thermal Integrity

Improved Trace Buffer Observation via Selective Data Capture Using 2-D Compaction for Post-Silicon Debug

AC-Plus Scan Methodology for Small Delay Testing and Characterization

A Variation Tolerant Current-Mode Signaling Scheme for On-Chip Interconnects

Modeling and Analysis of Power Distribution Networks in 3-D ICs

A Low-Cost, Systematic Methodology for Soft Error Robustness of Logic Circuits

Low Complexity Out-of-Order Issue Logic Using Static Circuits

Low Latency Systolic Montgomery Multiplier for Finite Field $GF(2^{m})$ Based on Pentanomials

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