By Topic

Components, Packaging and Manufacturing Technology, IEEE Transactions on

Issue 1 • Date Jan. 2013

Filter Results

Displaying Results 1 - 25 of 29
  • Front Cover

    Publication Year: 2013 , Page(s): C1
    Save to Project icon | Request Permissions | PDF file iconPDF (335 KB)  
    Freely Available from IEEE
  • IEEE Transactions on Components, Packaging and Manufacturing Technology publication information

    Publication Year: 2013 , Page(s): C2
    Save to Project icon | Request Permissions | PDF file iconPDF (122 KB)  
    Freely Available from IEEE
  • Table of contents

    Publication Year: 2013 , Page(s): 1 - 2
    Save to Project icon | Request Permissions | PDF file iconPDF (131 KB)  
    Freely Available from IEEE
  • Formation and Growth of Intermetallics in an Annealing-Twinned Ag-8Au-3Pd Wire Bonding Package During Reliability Tests

    Publication Year: 2013 , Page(s): 3 - 9
    Cited by:  Papers (4)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1453 KB) |  | HTML iconHTML  

    Wire bonding on Al pad packages with an innovative annealing twinned Ag-8Au-3Pd alloy wire results in a sufficient interfacial intermetallic layer at the initial as-bonded stage, while its growth during the further temperature cycling test and pressure cooker test is very slow. Even after prolonged high-temperature storage at 150°C for 500 h, the thickness of its intermetallics is only around 1.7 μm. In contrast, a very thin CuAl2 intermetallic layer appears at the interface of the Pd-coated Cu wire bonded package, and a thick layer of Au8Al3 intermetallic compounds forms in the Au wire package, which grows to a thickness of around 4.0 μm after high-temperature storage at 150°C for 500 h. Energy dispersive X-ray spectrometry analyses indicate that AgAl2, Au8Al3, and CuAl2 are the main intermetallic phases formed in the packages bonded with Ag-8Au-3Pd, and Au and Pd-coated Cu wires, respectively. However, an additional Pd-containing Ag2Al layer found at the AgAl2/Al interface of Ag-8Au-3Pd wire bonded package can interrupt its intermetallic reaction, and the annealing twins can further slow the intermetallic growth. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Transceiver Design for High-Density Links With Discontinuities Using Modal Signaling

    Publication Year: 2013 , Page(s): 10 - 20
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1337 KB) |  | HTML iconHTML  

    In high-speed chip-to-chip single-ended signaling links, far-end crosstalk presents one of the dominant noise sources, limiting the performance of the link. Diagonalizing the channel using modal decomposition has been proposed to mitigate the crosstalk, but so far only the transceiver designed for uniform low-loss homogenous media channels has been investigated. Furthermore, a practical circuit implementation of such a transceiver system will unavoidably deviate from the ideal (crosstalk-free) eigenvalue decomposition. In this paper, the impact of modal encoder/decoder coefficient quantization, random common noise, and uncorrelated noise on signal integrity is analyzed in terms of system-level performance metrics, signal-to-noise ratio at the receiver slicer, and bit error rate. Also discussed is the optimal selection of decoder coefficients with respect to the input-referred noise at the receiver. Based on these guidelines, a circuit design of a modal transceiver system over a typical memory bus with discontinuities is presented in detail. The proposed approach is verified using circuit-based link simulation, and the performance compared to several other proposed crosstalk-cancellation techniques. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Analytical Design of Via Lattice for Ground Planes Noise Suppression and Application on Embedded Planar EBG Structures

    Publication Year: 2013 , Page(s): 21 - 30
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1353 KB) |  | HTML iconHTML  

    Periodic ground via lattice is investigated to suppress the propagation of parallel-plate mode between two ground planes in a multiple layer package or printed circuit board. This parallel-plate mode (or ground/ground mode) plays a main role in the noise coupling or electromagnetic interference of the power planes or signal traces embedded between two ground planes. An analytical solution of the stopband cutoff frequency for designing the ground via pitch and diameter is derived, based on the eigenfunctions expansion method of the cavity model. Using the ground via lattice method and the analytical design solution, coupling noise mitigation and radiation emission reduction of power planes embedded between ground planes are demonstrated numerically and experimentally. Another example is the design of embedded planar electromagnetic bandgap (EBG) structure. The etched power plane of planar EBG structure embedded between the ground planes does not have a bandgap due to the coupling of the ground/ground mode. The minimum ground via number is designed to reproduce the bandgap of the embedded planar EBG structures by using the proposed analytical solution. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Novel Design Method for Electrically Symmetric High-Q Inductor Fabricated Using Wafer-Level CSP Technology

    Publication Year: 2013 , Page(s): 31 - 39
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2886 KB) |  | HTML iconHTML  

    High-Q spiral inductors are described that are embedded in the wafer-level chip-size package (WLP) and suffer from unfavorable two-port asymmetric characteristics. To solve this problem, a novel clip-type inductor is proposed, where an electrode crossover point in multiturn inductor structures is modified from a conventional mirror symmetric point to a novel electrical symmetric point. These novel clip-type inductors are designed and fabricated using the WLP technology. By means of a developed 4 nH novel clip inductor, a Q factor value difference between the two ports can be significantly reduced to 1.4% from 14.8% at 1.4 GHz. The Q factors of developed inductors are evaluated under both a conventional short-circuited load condition and an impedance-matched condition. In addition, a novel evaluation method for inductance values for inductors is also described. By using newly derived formulas, inductance values for a fabricated WLP clip-type inductor and a fabricated meander-type inductor are evaluated. This method represents the inherent nature of inductor devices under test including circuit parasitic elements. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Study on Bump Arrangement to Accelerate the Underfill Flow in Flip-Chip Packaging

    Publication Year: 2013 , Page(s): 40 - 45
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (863 KB) |  | HTML iconHTML  

    Flip-chip packaging is an integrated circuit packaging technique that uses solder bumps to connect chip with substrate. The underfill process uses epoxy encapsulant to solve this problem and improves the reliability of flip-chip packaging. The encapsulant is filled into the gap between the chip and substrate by the capillary force so that the thermal stresses may disperse into the underfill materials to avoid crack generation. The filling time in the underfill process strongly depends on the arrangement of the solder bumps. The edge effect can enhance the filling speed during the underfill encapsulation if the void formation can be avoided. With distributed bump pitch design, the filling time of the underfill can be reduced. There exists an optimal selection of the pitch variation during the use of distributed bump pitch. Another method of using a center bump-free channel can also increase the filling efficiency. The optimization method is used to determine the size of the channel that is found to increase the filling speed dramatically in the case of underfill of the chip with a fine bump pitch. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Study on Effects of Solder Fluxes on Catastrophic Mirror Damages During Laser Diode Packaging

    Publication Year: 2013 , Page(s): 46 - 51
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1046 KB) |  | HTML iconHTML  

    Solder fluxes have been commonly used in die bonding of high-power semiconductor lasers via indium solder. In this paper, the effects of some fluxes, with respect to reflow duration and cleaning solvent residues on the catastrophic mirror damage (CMD), are investigated. Scanning electron microscopy with an energy dispersive X-ray indicates that an increment of the sites of CMDs, size, and quality, obtained by increasing the reflow duration, depends on the type of the used flux. Fourier transform infrared spectroscopy confirms that nearly no contamination of the flux exists after the cleaning process. X-ray photoelectron spectroscopy analysis revealed that the flux or flux cleaning solvent residues could not be the main source of carbon or carbon compounds on the surface and, hence, the CMDs attributed to them. Finally, indium packaging of a diode laser by means of these rosin fluxes shows that RA flux has the best die bonding quality among other fluxes. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Effects of Package Level Structure and Material Properties on Solder Joint Reliability Under Impact Loading

    Publication Year: 2013 , Page(s): 52 - 60
    Cited by:  Papers (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1470 KB) |  | HTML iconHTML  

    In this paper, the effects of package level structures and material properties on solder joint reliability subjected to impact loading are investigated by the integrated experimental testing, failure analysis, and finite element modeling. Three different package structures: ball on I/O wafer level package (WLP), copper post WLP, and chip-scale (CS) ball grid array (BGA) package, are studied. Experimental testing based on JESD22-B111 is conducted to obtain the components' failure mode, rate, location, and the corresponding board strains and accelerations. Finite element models are developed and validated against the experimental results. For a CS BGA package, the compliance of the plastic substrate/mold compound provides a “stress buffer mechanism” at corner joints in BGA to relieve stresses. For a copper post (or pillar) WLP, wafer level epoxy, which encapsulates copper pillars, serves as a compliant layer for solder joint stress reduction under dynamic loading. Comprehensive data from simulation and experimental results show that package structure and material properties play a significant role on the dynamic responses of solder joints. The actual solder joint reliability performance of a CS BGA or WLP package depends on the resultant effects of package structure, material properties, package body size, and the component locations. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Comprehensive Thermomechanical Analyses and Validations for Various Cu Column Bumps in fcFBGA

    Publication Year: 2013 , Page(s): 61 - 70
    Cited by:  Papers (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2260 KB) |  | HTML iconHTML  

    Since the employment of copper (Cu) column bump (with lead-free solder cap) interconnect offers flexibility in the aspect ratio, increases the I/O density, and provides the characteristic of fine-pitch bumps in flip-chip technology (less than 150 μm bump pitch), a significant amount of research on Cu column bumps in flip-chip packages has been carried out in recent years. For the implementations of Cu column bumps, the architectures of bump-on-capture (BOC) pad with solder bump on pre-solder and bump-on-lead (BOL) with solder bump on Cu trace are usually adopted in flip-chip packages. For the purpose of realizing the mechanical behaviors for fcFBGA (flip-chip fine-pitch ball grid array) with lead-free (LF) bump, Cu column bump, and Cu column bump without (w/o) LF solder cap (Cu column w/o solder cap), this paper presents 3-D finite element analysis (FEA) and compare their warpage and stress responses. The experimental coplanarity measurements for these three types of bumps in fcFBGA are carried out to validate the FEA results. Moreover, the reliability assessment for the underfill selection is further validated with an FEA study. Through validation and simulation, it is observed that the use of an LF bump was better at preventing extreme low-k (ELK) failure and aluminum (Al) pad/underbump metallurgy (UBM) delamination, while the use of Cu column bump with and without a solder cap can avoid pre-solder crack failure. In addition, because the packaging geometry and material always play important roles in determining mechanical behaviors, identifying the most significant factors that affect the stress and warpage responses is useful if stress and warpage reductions in fcFBGA are required. In order to gain the essential factors in fcFBGA, systematic simulation studies for LF bump, Cu column bump, and BOL are illustrated. The impact levels for the top significant factors that influence the ELK, UBM, and bump stresses as well as the warpage are obtained thr- ugh systematic simulation studies. Several suggestions for reducing warpage and the critical stresses in fcFBGA with Cu column bumps are recommended. The results show that the stresses in ELK, UBM, and bump in the BOL structure are smaller than those in a BOC structure, demonstrating that the BOL structure provides a reliable fcFBGA package without any ELK damage, UBM delamination, or bump crack issues. The perpendicular BOL orientation in the corner bump area also prevents damage that can be caused by a Cu trace or LF bump. It is believed that the proposed results will provide design guidelines to enhance package reliability and reduce the package cost during the development stage. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Effects of Board Design Variations on the Reliability of Lead-Free Solder Joints

    Publication Year: 2013 , Page(s): 71 - 78
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2153 KB) |  | HTML iconHTML  

    Sn-Ag-Cu (SAC) solder alloys, such as Sn-3.0Ag-0.5 Cu (SAC305) are the popular choices of lead-free solders replacing SnPb solders. However, SAC solders are more brittle in nature due to stiffness and excessive intermetallic compounds growth at the solder joint to pad interface. This leads to higher risk of solder joints failures. Memory module-type smaller lead-free ball grid array (BGA) packages are constantly under dynamic stresses during handling and thermal stresses during operations. It is important to understand the dynamic performance and long-term reliability of memory module lead-free BGAs. It is believed that the printed circuit board (PCB) design variations cause dynamic and long-term failure discrepancies in the fields. In this paper, different pad and trace designs are introduced to evaluate the effects of PCB design variations on the bend and accelerated thermal cycling (ATC) performance of lead-free solder joints. Pad designs with nonsolder mask defined, solder mask defined (SMD), and a unique web design are assembled and tested. Different solder alloys, including SAC305, Sn-1.0Ag-0.5Cu (SAC105) SAC105, and SnPb solders, have been evaluated in this paper. Different PCB materials have also been evaluated in the test. Four-point monotonic bend tests are performed to characterize the bending performance variations with different PCB designs and compared with conventional Sn-Pb solder. The SMD pad is shown to have the best bend performance among all other types of designs in this paper. In addition, this design also shows improvement in mitigation of PCB pad cratering with lead-free solders. Wide trace width seems to degrade the strength and is not preferred. Just as it shows superior shock resistance when compared with SAC305, the SAC105 solder alloy also shows better bend performance. There is no significant improvement in bend performance with web design. After aging treatment, bend performance of both SAC305 and SAC105 degraded by up to 34% and 29%,- respectively. However, the bend performance of eutectic SnPb is actually improved after aging. ATC tests are performed to investigate the effects of design variations on the long-term reliability of lead-free solder joints; SMD design shows less reliability life than others. The implications of these results for the reliability of lead-free solder joints are discussed in this paper. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Improved Thermal Interfaces of GaN–Diamond Composite Substrates for HEMT Applications

    Publication Year: 2013 , Page(s): 79 - 85
    Cited by:  Papers (4)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1073 KB) |  | HTML iconHTML  

    High-power operation of AlGaN/GaN high-electron-mobility transistors (HEMTs) requires efficient heat removal through the substrate. GaN composite substrates, including the high-thermal-conductivity diamond, are promising, but high thermal resistances at the interfaces between the GaN and diamond can offset the benefit of a diamond substrate. We report on measurements of thermal resistances at GaN-diamond interfaces for two generations (first and second) of GaN-on-diamond substrates, using a combination of picosecond time-domain thermoreflectance (TDTR) and nanosecond transient thermoreflectance techniques. Two flipped-epitaxial samples are presented to determine the thermal resistances of the AlGaN/AlN transition layer. For the second generation samples, electrical heating and thermometry in nanopatterned metal bridges confirms the TDTR results. This paper demonstrates that the latter generation samples, which reduce the AlGaN/AlN transition layer thickness, result in a strongly reduced thermal resistance between the GaN and diamond. Further optimization of the GaN-diamond interfaces should provide an opportunity for improved cooling of HEMT devices. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Performance of Online and Offset Micro Pin-Fin Heat Sinks With Variable Fin Density

    Publication Year: 2013 , Page(s): 86 - 93
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (824 KB) |  | HTML iconHTML  

    A comparison of the performances of online and offset micro pin-fin heat sinks with variable fin density is given in this paper. The cooling systems generate uniform junction temperatures, which improves the integrated circuit (IC) chip's performance. Water is used as a coolant in the single phase and laminar regime. 4748 micro flat fins with rounded sides, which are distributed in three different sections along the flow length, are used in these configurations. The bottom wall temperature profile along the flow length, overall thermal resistances, pressure drops, and pumping powers for both configurations are presented. The results indicate that the offset micro pin-fin heat sink is a good alternative for cooling the IC chips of 2016. The cooling system using this fin configuration is capable of achieving a thermal resistance as low as 0.1 K/W with a pumping power requirement of 0.45 W. Comparisons with other cooling devices reported in the technical literature are presented. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Power Multiplexing for Thermal Field Management in Many-Core Processors

    Publication Year: 2013 , Page(s): 94 - 104
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1760 KB) |  | HTML iconHTML  

    This paper presents the effect of proactive spatiotemporal power multiplexing on the thermal field in many-core processors. Power multiplexing migrates the locations of active cores within a chip after each fixed time interval, referred to as the migration interval, to redistribute the generated heat and thereby reduce the peak temperature and spatial and temporal nonuniformity in the thermal field. Clock and supply gating is used to minimize the power of the deactivated cores. The control of the migration interval is studied considering a 256-core processor at the predictive 16-nm node to evaluate the conflicting impact of the migration interval on thermal field and system performance. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Dual-Bandpass Filters With Individually Controllable Passbands

    Publication Year: 2013 , Page(s): 105 - 112
    Cited by:  Papers (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (991 KB) |  | HTML iconHTML  

    A novel dual-band filter based on split-ring resonators (SRRs) and double-slit complementary SRRs is presented. The size of the filter is small and the two passbands can be individually designed. The basic cell of the filter is presented and analyzed, and then the multistage dual-passband filter is achieved by cascading basic cells. The design graphs for external quality factors of the resonators at input and output stages and the coupling coefficient between the adjacent resonators are constructed. The design graphs are utilized to determine the proper geometric parameters of each filter stage for a given filter specification. As an example, a prototype three-stage Chebyshev filter with a fractional bandwidth (FBW) of 2% at 0.9 GHz and a FBW of 3% at 1.3 GHz is demonstrated. The prototyped filter has an equal ripple of 0.4 dB at both passbands. The measurements of the prototyped filter agree well with the simulation results. The center frequencies and the FBWs of the two passbands of the prototyped filter can be individually designed with more flexibility compared to dual-band filters that utilize resonances of higher order modes. The overall size reduction of the proposed filter can be as high as by a factor of 3 compared to that of edge-coupled microstrip filters. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Analytical Transfer Functions Relating Power and Ground Voltage Fluctuations to Jitter at a Single-Ended Full-Swing Buffer

    Publication Year: 2013 , Page(s): 113 - 125
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1201 KB) |  | HTML iconHTML  

    The transfer functions relating supply voltage fluctuations to jitter are analytically derived in closed form expressions for a single-ended buffer. The analytic transfer functions are derived from a linear differential equation obtained from asymptotic linear inverter I-V curves. The transfer functions are validated by comparison with HSPICE simulations. The estimated jitter is compared with the simulated jitter using eye diagrams with single-frequency and multitone supply voltage fluctuations. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • 40- \mu{\rm m} Cu/Au Flip-Chip Joints Made by 200 ^{\circ}{\rm C} Solid-State Bonding Process

    Publication Year: 2013 , Page(s): 126 - 132
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (5201 KB) |  | HTML iconHTML  

    Flip-chip interconnect joints of copper/gold (Cu/Au) with 40-μm diameter and 100-μm pitch were made between silicon (Si) chips and Cu substrates using solid-state bonding at 200°C with a static pressure of 250-400 psi (1.7-2.7 MPa). The array of 50 × 50 Cu/Au columns was first created. In fabrication, photoresist with 50 x 50 cavities of 40-μm diameter and 45-μm depth were produced on Si wafers, which were first coated with 30 nm chromium and 100 nm Au films. Cu of 25-μm thickness was electroplated in the cavities, followed by 10 μm of Au. After stripping the photoresist, the array of 50 x 50 Cu/Au columns was obtained on a chip region of the wafer. The 50 x 50 Cu/Au columns on the chip were bonded to a Cu substrate by solidstate bonding. No molten phase was involved and no flux was used. No underfill was applied. The corresponding load for each column was only 0.22-0.35 g. Cross-section scanning electron microscopy images show that Cu/Au columns were well bonded to the Cu substrate. Despite the large mismatch in the coefficient of thermal expansion between Si and Cu, no joint breakage was observed. The pull test was performed and the fracture modes were evaluated. The fracture force and fracture strength obtained were 11.2-14.2 kg and 35-44 MPa (5000-6400 psi), respectively. The measured fracture force is four times larger than the criterion of the pull-off test in MIL-STD-883E. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Constitutive Models for Intermediate- and High-Strain Rate Flow Behavior of Sn3.8Ag0.7Cu and Sn1.0Ag0.5Cu Solder Alloys

    Publication Year: 2013 , Page(s): 133 - 146
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2739 KB) |  | HTML iconHTML  

    In much of the existing research, SnAgCu solder alloys are characterized at low strain rates, typically in the 10-6 to 1 s-1 range. In this paper, we report experimental results and constitutive models for two popular SnAgCu solder alloys at intermediate and high strain rates, ranging from 10-2 to 103 s-1 at room temperature. These experiments were performed using two different experimental setups: a MTS 810 uniaxial compression tester, and a split-Hopkinson pressure bar. In conjunction with our previous work at lower strain rates (10-6 to 10-3 s-1), these results yield the plastic flow response of these solders over nine decades of strain rate, and demonstrate a remarkably consistent relationship between the yield stress and the strain rate over the entire nine decades. We also develop the Anand viscoplastic constitutive model, and demonstrate that fit parameters for the low-strain rate regime can be extrapolated to accurately predict the experimental response at high strain rates. Thus, the model presented here proffers the capability of modeling solder deformation under a wide range of loading conditions using most commercially available finite element (FE) programs. To illustrate the validity of the model parameters, we develop idealized FE models together with cohesive zone failure descriptions at the interface between the solder and the intermetallic compound. We demonstrate that when used in conjunction with appropriate failure models, the constitutive model developed here accurately captures the empirically observed shift in failure modes from bulk failure to interfacial failure under tensile loading at higher strain rates. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Design and Experiment of a Jetting Dispenser Driven by Piezostack Actuator

    Publication Year: 2013 , Page(s): 147 - 156
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1835 KB) |  | HTML iconHTML  

    To make up for the insufficiency and instability of contact dispensers that are used for fluid dispensing in microelectronic packaging, a noncontact jetting dispenser driven by a piezostack actuator is introduced in this paper. After describing the structural components and operating principle of the dispensing mechanism, a fluid model is presented to discuss the dynamic properties of the fluid and analyze the key parameters of the proposed dispenser. The ANSYS simulation software is used to design the displacement amplifier, which is an important component of the dispenser. The maximum displacement output of 323 μm is obtained by optimizing. Subsequently, the dynamic behavior of the displacement amplifier is measured by an optical displacement sensor. The displacement change with the driving voltage amplitude and frequency is also investigated; the maximum displacement is 320 μm, and the error between the simulation and the measurement result is just 0.75%. In order to verify the practicality of dispenser, experiments are conducted to examine the effects of the driving voltage, backpressure, working temperature, and distance between the nozzle and the collector on the jetting performance and droplet diameter. The dispenser can dispense droplets uniformly and steadily. Its maximum jetting frequency is 65 Hz, and droplets of 1.07-mm diameter are produced by a stainless steel nozzle of 0.25-mm diameter in the experimental study, with the variation of the droplet diameter being within ±2%. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Empirical Equation of Wire Sag Model for Semiconductor Packaging With Numerical and Experimental Verification

    Publication Year: 2013 , Page(s): 157 - 167
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1029 KB) |  | HTML iconHTML  

    For the semiconductor packaging industry, the issue of wire sag has not been touched upon because only one single layer of wire bond is constructed along the perimeter of the chip system. Over-sag deflections may not cause any problems. However, driven by the demands for smaller and faster advanced microelectronic devices, modern 3-D and multichip modules have become the solution of choice in delivering higher integration and more multifunctional products to meet consumer needs. For 3-D and multichip packaging, excessive wire sag can lead to wires touching against the lower layer, causing a short-circuit and failure of chip functionality. Therefore, gaining knowledge of wire bond sag theory becomes extremely important for advanced packaging. We propose an empirical model to predict the sag stiffness of a wire bond. The sag stiffness of a wire bond is defined to represent its resistance to the sag drag force occurring during the encapsulation process by the molding flow. A higher sag stiffness of a wire bond gives the premise of less sag deflection, thereby avoiding short-circuiting and/or double wire crosstalk due to the closeness of the top-layer to the bottom-layer wire bonds. The theory of sag regarding semiconductor wire bonding has not been documented, to our knowledge, in the literature. Therefore, to deal with this issue, this paper will primarily focus on the theoretical and numerical analysis of sag deflection of a wire bond. A set of sag experiments is conducted to verify the validity of the sag model hypothesis outlined in the earlier paper. Subsequently, an empirical sag model could be put forward to predict the sag stiffness of a wire bond if the corresponding bond spans, bond heights, and material properties are known. The engineered design of a wire bond can be improved through the use of this sag equation. By making use of the proposed sag model, one can attain not only a first-order estimation of the sag deflection but also omit the tedious procedu- es of numerical analysis. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Surface-Tension-Driven Self-Assembly of 3-D Microcomponents by Using Laser Reflow Soldering and Wire Limiting Mechanisms

    Publication Year: 2013 , Page(s): 168 - 176
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (3176 KB) |  | HTML iconHTML  

    This paper proposes a surface-tension-driven self-assembly method for manufacturing highly 3-D microstructures in microelectromechanical systems (MEMS). By using laser reflow soldering, various MEMS microstructures, even including the thermal-sensitive components, are able to be effectively assembled. Moreover, an energy-based numerical model is established for predicting the equilibrium geometry of a self-assembled structure. Based on the calculated results of energy and torque, an analysis is carried out on the factors affecting the self-assembled equilibrium position. In addition, the self-assembly process is also investigated experimentally by fabricating a popped-up microstructure with two light-emitting diodes die. Experimental studies, combined with the modeling results, have demonstrated that the self-assembly angle can be controlled within ±2.5°. Furthermore, in order to enhance the precision of self-assembly, a novel low-cost wire limiter structure fabricated by the wire bonding process is presented, which reduces the assembly angle variation down to ±0.5°. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Effects of ACF Bonding Parameters on ACF Joint Characteristics for High-Speed Bonding Using Ultrasonic Bonding Method

    Publication Year: 2013 , Page(s): 177 - 182
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1002 KB) |  | HTML iconHTML  

    As the use of anisotropic conductive films (ACFs) in flex-on-board bonding has increased recently, the need for high-speed bonding for higher productivity has developed. For high-speed bonding, a fast-curable acrylic resin has been used instead of an epoxy resin, and ultrasonic (US) bonding is introduced to allow for short bonding time at high bonding temperatures. However, it is possible for fast curable acrylic ACFs at 250°C to be fully cured before the resins flow out sufficiently between the electrodes. In such cases, the ACF joints could show poor electrical characteristics due to there being no conductive particle capture. Therefore, in this paper, in order to understand important factors for high-speed bonding, the effects of the bonding parameters, substrate geometry, and ACF material property on the ACF joint characteristics, such as resin flow and joint resistance, are investigated using acrylic-based ACFs and US bonding. The fast-curable acrylic resin is fully cured at a bonding temperature of 250°C within 1 s. However, the ACF joints bonded at 250°C show joint gaps larger than the diameter of conductive particles, i.e., 8 μm, due to insufficient resin flow and open failure due to no particle capture. As the bonding pressure increases from 2 to 4 MPa, the ACF joint gap at 250°C is smaller than the conductive particle size, and the joint resistance reaches about 20 mΩ within 7 s when using 3-mm-long electrodes and a high-viscosity resin. However, in order to use a shorter bonding time and the common bonding pressure of 3 MPa, the effects of substrate geometry and resin property on ACF joint characteristics are investigated. As the electrode length of the substrates are decreased from 3 to 1 mm, the ACF joints show stable ACF joint gaps and joint resistance at 3 MPa despite the bonding temperature of 250°C applied within 1 s. In terms of the ACF resin properties, when a resin with low minimum viscosit- is used, the ACF joint gaps are smaller than the diameter of the conductive particles. Furthermore, the joint resistance of low-minimum-viscosity ACF is more stable than that of the ACF joints bonded with the high-minimum-viscosity resin at 250°C within 1 s, even though a 3-mm-long electrode is used. These results indicate that the substrate geometry of the printed circuit board and the ACF resin viscosity are significant factors for high-speed bonding to obtain stable ACF joints at a high bonding temperature of 250°C within 1 s. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • [Blank page]

    Publication Year: 2013 , Page(s): 183 - 184
    Save to Project icon | Request Permissions | PDF file iconPDF (6 KB)  
    Freely Available from IEEE
  • Open Access

    Publication Year: 2013 , Page(s): 185
    Save to Project icon | Request Permissions | PDF file iconPDF (1156 KB)  
    Freely Available from IEEE

Aims & Scope

IEEE Transactions on Components, Packaging, and Manufacturing Technology publishes research and application articles on modeling, design, building blocks, technical infrastructure, and analysis underpinning electronic, photonic and MEMS packaging.

Full Aims & Scope

Meet Our Editors

Managing Editor
R. Wayne Johnson
Auburn University