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Design & Test, IEEE

Issue 1 • Date Feb. 2013

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Displaying Results 1 - 24 of 24
  • Front Cover

    Publication Year: 2013 , Page(s): C1
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  • While the world benefi ts from what's new, ieee can focus you on what's next [advertisement]

    Publication Year: 2013 , Page(s): C2
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  • IEEE Design & Test of Computers publication information

    Publication Year: 2013 , Page(s): C1
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  • Table of contents

    Publication Year: 2013 , Page(s): 2
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  • Departments

    Publication Year: 2013 , Page(s): 3
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  • Towards Making Parallel EDA Serve Practical Applications

    Publication Year: 2013 , Page(s): 4 - 5
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  • Guest Editors' Introduction to Practical Parallel EDA

    Publication Year: 2013 , Page(s): 6 - 7
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  • Using GPUs to Accelerate CAD Algorithms

    Publication Year: 2013 , Page(s): 8 - 16
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    The authors give an introduction to developing an EDA tool on a graphical processing unit. They present fault simulation as one of their EDA-specific examples. View full abstract»

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  • To Thread or Not to Thread

    Publication Year: 2013 , Page(s): 17 - 25
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    The authors present a real-life industrial EDA problem; in particular, layout versus schematic checking. They describe why they chose threads to speed up their EDA tool. View full abstract»

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  • Exploiting Parallelism by Data Dependency Elimination: A Case Study of Circuit Simulation Algorithms

    Publication Year: 2013 , Page(s): 26 - 35
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (735 KB)  

    The authors present a methodology geared towards EDA applications such as parasitic extraction, transient circuit simulation, and RF steady-state simulations. View full abstract»

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  • Multicore Algorithms for Transient-Noise Simulation

    Publication Year: 2013 , Page(s): 36 - 44
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    The authors utilize multicores towards random noise simulation using an adaptive Newton sub-matrix approach. View full abstract»

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  • Advances in Parallel Discrete Event Simulation for Electronic System-Level Design

    Publication Year: 2013 , Page(s): 45 - 54
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    Editors' notes: The authors target the speeding up of parallel discrete event simulations in transaction-level models. View full abstract»

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  • Time Is Money

    Publication Year: 2013 , Page(s): 55 - 57
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  • Dispelling the Myths of Parallel Computing

    Publication Year: 2013 , Page(s): 58 - 64
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    Professor Patrick Madden presents his (agnostic) take on parallel computing. We believe that having an agnostic view allows us to focus on the deficiencies of the systems we are building, so we can improve on them. View full abstract»

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  • Developing Parallel EDA Tools [The Last Byte]

    Publication Year: 2013 , Page(s): 65 - 66
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (80 KB)  

    In the past decades, EDA tools were able to keep up with the increasing design sizes, enabled by Moore's Law, through smarter algorithms running on faster processors. Now that most key algorithms are close to n:Log??n??, implementation inefficiencies have been cleaned up and single-threaded performance gains have leveled off, parallel CAD is the way forward. Every EDA application will need to scale to dozens of processors. While several EDA tools have shown good scalability to many threads, some are not scaling beyond 12-16 threads and other tools have not even been replaced with more scalable equivalents. To reach massive parallelism, it is important for every EDA developer to master the following key skills described by the author. View full abstract»

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  • Can semantic technologies make the web truly worldwide? [advertisement]

    Publication Year: 2013 , Page(s): 67
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  • On Deploying Scan Chains for Data Storage in Test Compression Environment

    Publication Year: 2013 , Page(s): 68 - 76
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (584 KB)  

    In this study the authors show how the interface between automatic test equipment (ATE) and on-chip decompression logic can be improved by a smart reuse of the scan chains. Storing the parent patterns of a modular decompression scheme in groups of scan chains avoids multiple loads from the ATE and thus reduces the test time. The presented algorithm for scan chain selection allows a flexible bandwidth management while preserving encoding efficiency and fault coverage. View full abstract»

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  • Discover more. IEEE Educational Activities

    Publication Year: 2013 , Page(s): 77
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  • Know your limits (review of "limits to parallel computation: p-completeness theory"; greenlaw, r., et al; 1995) [book review]

    Publication Year: 2013 , Page(s): 78 - 83
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  • IEEE Phaser Data

    Publication Year: 2013 , Page(s): 84
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  • CEDA Currents

    Publication Year: 2013 , Page(s): 85 - 86
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  • Test Technology TC Newsletter

    Publication Year: 2013 , Page(s): 87 - 88
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  • IEEE Xplore Digital Library

    Publication Year: 2013 , Page(s): C3
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  • Technology insight on demand on IEEE.tv [advertisement]

    Publication Year: 2013 , Page(s): C4
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Aims & Scope

IEEE Design & Test offers original works describing the models, methods, and tools used to design and test microelectronic systems from devices and circuits to complete systems-on-chip and embedded software. The magazine focuses on current and near-future practice, and includes tutorials, how-to articles, and real-world case studies. The magazine seeks to bring to its readers not only important technology advances but also technology leaders, their perspectives through its columns, interviews, and roundtable discussions. Topics include semiconductor IC design, semiconductor intellectual property blocks, design, verification and test technology, design for manufacturing and yield, embedded software and systems, low-power and energy-efficient design, electronic design automation tools, practical technology, and standards.

It was published as IEEE Design & Test of Computers between 1984 and 2012.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief
Andre Ivanov
Department of Electrical and Computer Engineering, UBC