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# IEEE Transactions on Circuits and Systems II: Express Briefs

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Displaying Results 1 - 25 of 35

Publication Year: 2012, Page(s):C1 - C4
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• ### IEEE Transactions on Circuits and Systems—II: Express Briefs publication information

Publication Year: 2012, Page(s): C2
| PDF (39 KB)
• ### An Ultra Low-Power Dual-Band IR-UWB Transmitter in 130-nm CMOS

Publication Year: 2012, Page(s):701 - 705
Cited by:  Papers (9)
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In this brief, a 0-960-MHz/3.1-5-GHz dual-band ultra low-power impulse-radio ultrawideband transmitter is presented. The pulse transmitter integrated circuit is fabricated using a 130-nm CMOS process with the core die area of 0.1 mm2. At 1-MHz pulse repetition frequency, the power consumption values are measured in the lower and the upper bands as 5.6 and 31 μW, respectively. The... View full abstract»

• ### Ultralow Power Injection-Locked GFSK Receiver for Short-Range Wireless Systems

Publication Year: 2012, Page(s):706 - 710
Cited by:  Papers (3)
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This brief presents a novel CMOS Gaussian frequency-shift keying (GFSK) receiver with an ultralow power consumption, which is based on the injection-locking technique for short-range wireless systems. Additionally, through reducing the oscillation current amplitude of the injection-locked oscillator, the GFSK receiver sensitivity is significantly improved. While comprising a submilliwatt low-noise... View full abstract»

• ### A Clock-Harvesting Receiver Using 3G CDMA Signals in the 1900-MHz Band

Publication Year: 2012, Page(s):711 - 715
Cited by:  Papers (1)
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A clock-harvesting receiver is presented, which extracts a 1.2-kHz clock embedded within the third-generation code-division multiple-access standard for the wake-up of a wireless sensor network. The energy-detection-based receiver was fabricated in 0.13-μm CMOS and designed for low-power heavily duty-cycled operation. In active mode, the receiver has a measured sensitivity of -73 dBm while ... View full abstract»

• ### Measurement of Intersymbol Interference Jitter by Fractional Oversampling for Adaptive Equalization

Publication Year: 2012, Page(s):716 - 720
Cited by:  Papers (1)
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The deterministic jitter due to the intersymbol interference (ISI) is measured on-chip by fractional oversampling, which can be used to adapt the equalization coefficients of a continuous-time linear equalizer. The effective resolution of the jitter measurement is improved to 0.1 unit interval (UI) by sampling the data input by multiphase sampling clocks spaced by 0.7 UI with the proposed fraction... View full abstract»

• ### A 1.9-GHz Fractional-N Digital PLL With Subexponent $DeltaSigma$ TDC and IIR-Based Noise Cancellation

Publication Year: 2012, Page(s):721 - 725
Cited by:  Papers (1)
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This brief presents a 1.9-GHz fractional-N digital phase-locked loop (DPLL) with a subexponent ΔΣ time-to-digital converter (TDC) and an infinite impulse response (IIR)-based noise cancellation scheme. The proposed subexponent ΔΣ TDC generates adaptively scaled exponent-only information to track the finest resolution that prevents overloading for a given input environme... View full abstract»

• ### Analysis of a 5.5-V Class-D Stage Used in $+$ 30-dBm Outphasing RF PAs in 130- and 65-nm CMOS

Publication Year: 2012, Page(s):726 - 730
Cited by:  Papers (2)
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This brief presents the design and analysis of a 5.5-V class-D stage used in two fully integrated watt-level, +32.0 and + 29.7 dBm, outphasing RF power amplifiers (PAs) in standard 130- and 65-nm CMOS technologies. The class-D stage utilizes a cascode configuration, driven by an ac-coupled low-voltage driver, to allow a 5.5-V supply in the 1.2-/2.5-V technologies without excessive device voltage s... View full abstract»

• ### Continuous Class-E Power Amplifier Modes

Publication Year: 2012, Page(s):731 - 735
Cited by:  Papers (14)
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In this brief, a continuum of novel closed-form solutions is derived for class-E power amplifiers (PAs). It is analytically proven that the class-E zero voltage/zero voltage derivative switching conditions can be satisfied for an arbitrarily selected reactive second harmonic switch impedance (Z2S). The higher order harmonic currents are terminated capacitively. The con... View full abstract»

• ### A CMOS Integrated W-band Passive Imager

Publication Year: 2012, Page(s):736 - 740
Cited by:  Papers (2)
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This brief presents an integrated W-band passive imager, including a low-noise amplifier, a Dicke switch, a detector, a low-pass filter, a programmable-gain amplifier, and a 10-bit 20-MHz pipeline analog-to-digital converter (ADC). With digital outputs, the imager is ready to be interfaced with a digital signal processor to complete its system implementation. The chip is realized in a 65-nm CMOS t... View full abstract»

• ### A Dual-Channel Pipelined ADC With Sub-ADC Based on Flash–SAR Architecture

Publication Year: 2012, Page(s):741 - 745
Cited by:  Papers (6)  |  Patents (1)
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This brief presents a 10-bit dual-channel pipelined flash-successive approximation register (SAR) analog-to-digital converter (ADC) for high-speed applications. The proposed ADC consists of two channels for high operating speed, and each channel adopts a pipelined flash-SAR architecture for low power and a small area. The proposed flash-SAR ADC in the second stage is composed of a 1-bit flash ADC ... View full abstract»

• ### A 6-bit Current-Steering DAC With Compound Current Cells for Both Communication and Rail-to-Rail Voltage-Source Applications

Publication Year: 2012, Page(s):746 - 750
Cited by:  Papers (7)
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A compound current cell, with n-type, p-type, and bipolar properties, is proposed in this brief and utilized in a current-steering digital-to-analog converter (DAC) to satisfy the application of rail-to-rail voltage sources. In addition, the DAC with cells also has a high-speed fashion. Therefore, this brief presents a 6-bit CMOS current-steering DAC with cells for both communication and rail-to-r... View full abstract»

• ### Ultralow-Power Processing Array for Image Enhancement and Edge Detection

Publication Year: 2012, Page(s):751 - 755
Cited by:  Papers (5)
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This paper presents a massively parallel processing array designed for the 0.13-μm 1.5-V standard CMOS base process of a commercial 3-D through-silicon via stack. The array, which will constitute one of the fundamental blocks of a smart CMOS imager currently under design, implements isotropic Gaussian filtering by means of a MOS-based RC network. Alternatively, this filtering can be ... View full abstract»

• ### A New Quadrature PWM Modulator With Tunable Center Frequency for Digital RF Transmitters

Publication Year: 2012, Page(s):756 - 760
Cited by:  Papers (20)
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State-of-the-art quadrature-type modulators for all-digital radio-frequency (RF) transmitters operate optimally at an RF center frequency (fc) that is a fraction of the modulator switching rate. This is a major limitation if the modulators of this type are to be used in multichannel transmitter systems. In this brief, a novel quadrature modulator based on pulsewidth modulation with controll... View full abstract»

• ### A Model for MOS Diodes With $V_{rm th}$ Cancellation in RFID Rectifiers

Publication Year: 2012, Page(s):761 - 765
Cited by:  Papers (5)
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A theoretical model for diode-connected MOS transistors with a threshold cancellation technique is developed. The model is based on a detailed analysis of the technique with internal threshold cancellation (ITC) and reveals design insight and performance limitations. Derived design equations illustrate the tradeoff between the voltage drop and the reverse leakage of the diode. Furthermore, a desig... View full abstract»

• ### Generalized Series–Parallel $RLC$ Synthesis Without Minimization for Biquadratic Impedances

Publication Year: 2012, Page(s):766 - 770
Cited by:  Papers (23)
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This brief is concerned with the realization problem of biquadratic impedances, motivated by the recent development in passive mechanical control. This brief generalizes a realization procedure of a special class of biquadratic impedances to a more general form, and the resulting series-parallel RLC networks whose elements are no more than those in Bott-Duffin's networks are obtained withou... View full abstract»

• ### A 60-V, $>hbox{225} ^{circ}hbox{C}$ Half-Bridge Driver for Piezoelectric Acoustic Transducer, on SOI CMOS

Publication Year: 2012, Page(s):771 - 775
Cited by:  Papers (1)
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This brief presents a high-voltage (HV) transducer driver to fulfill the requirement of the proposed high-data-rate down-hole acoustic telemetry system. The driver is targeted to drive a stack of piezoelectric disks modeled as a capacitive load of 0.3 μF and across a broadband from 600 Hz to 1.2 kHz. To ensure stability, the driver is designed as an open-loop system, comprising a dead-time ... View full abstract»

• ### A 10-MHz GaN HEMT DC/DC Boost Converter for Power Amplifier Applications

Publication Year: 2012, Page(s):776 - 779
Cited by:  Papers (8)
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AlGaN/GaN HEMTs show low on-state resistance and small gate capacitances, which makes them good candidates for switching applications. Up to now, their exploitations in dc/dc converters have been largely investigated in high power electronics but with switching frequencies under 1 MHz. In this brief, the potentialities of GaN HEMTs are investigated for high-speed dc/dc converters. To this aim, a 1... View full abstract»

• ### A Dual Charge Pump for Quiescent Touch Sensor Power Supply

Publication Year: 2012, Page(s):780 - 784
Cited by:  Papers (8)
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This brief presents a dual charge pump suitable for touch sensor power supply applications, where a calm standby voltage as well as quick recovery from disturbance is required. The proposed circuit adaptively controls the two parallel-connected charge pumps: a current driving Dickson's charge pump with a pumping capacitor of 95.4 pF and a low-ripple cross-couple charge pump with a capacitor of 10.... View full abstract»

• ### Imbalance-Based Self-Test for High-Speed Mixed-Signal Embedded Systems

Publication Year: 2012, Page(s):785 - 789
Cited by:  Papers (6)
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Precisely measuring specifications of differential analog and mixed-signal circuits is a difficult problem for self-test development because the imbalance introduced by the design-for-test circuitry on the differential signaling causes nonlinearity on the test stimulus, resulting in degrading device-under-test (DUT) performance. This problem triggers low test accuracy and serious yield loss. This ... View full abstract»

• ### A 45-nm Dual-Port SRAM Utilizing Write-Assist Cells Against Simultaneous Access Disturbances

Publication Year: 2012, Page(s):790 - 794
Cited by:  Papers (6)
| | PDF (1311 KB) | HTML

Eight-transistor (8T) dual-port static random access memory (DP-SRAM) suffers from read and write disturbances at low voltages when both ports are accessed simultaneously, and write disturbance dominates the VDDmin in high-speed applications. This brief proposes a write-assist 8T (WA8T) cell to suppress the write disturbance for DP-SRAM to achieve a lower VDDmin with low area overhead and power co... View full abstract»

• ### Efficient Polynomial Basis Multipliers for Type-II Irreducible Pentanomials

Publication Year: 2012, Page(s):795 - 799
Cited by:  Papers (2)
| | PDF (654 KB) | HTML

Bit-parallel polynomial basis multipliers over the finite field GF(2m) generated using type-II irreducible pentanomials are considered in this brief. The bit-parallel multipliers presented here have the lowest delay known to date for similar multipliers based on this type of irreducible pentanomials, with a very small increase of XOR gates. View full abstract»

• ### A Discrete Model for Correlation Between Quantization Noises

Publication Year: 2012, Page(s):800 - 804
| | PDF (311 KB) | HTML

The automation of fixed-point conversion requires fast methods to evaluate the numerical accuracy of the system. As an alternative to a simulation-based approach, most of the analytical methods use perturbation theory to provide the expression of the quantization noise at the output of a system. Most existing analytical methods do not consider a correlation between noise sources. This assumption i... View full abstract»

• ### Perfect Decomposition Narrow-Band FIR Filter Banks

Publication Year: 2012, Page(s):805 - 809
Cited by:  Papers (5)
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This brief introduces perfect decomposition filter banks based on narrow-band linear-phase finite impulse response (FIR) filters. They consist of inner and lateral FIR filters. The inner filters are optimal equiripple narrow-bandpass FIR filters based on isoextremal polynomials. The inner filters are supplemented by lateral narrow-band low- and high-pass FIR filters. The concept of such isoextrema... View full abstract»

• ### Further Properties and a Fast Realization of the Iterative Truncated Arithmetic Mean Filter

Publication Year: 2012, Page(s):810 - 814
Cited by:  Papers (8)
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The iterative truncated arithmetic mean (ITM) filter has been recently proposed. It possesses merits of both the mean and median filters. In this brief, the Cramer-Rao lower bound is employed to further analyze the ITM filter. It shows that this filter outperforms the median filter in attenuating not only the short-tailed Gaussian noise but also the long-tailed Laplacian noise. A fast realization ... View full abstract»

## Aims & Scope

Part I will now contain regular papers focusing on all matters related to fundamental theory, applications, analog and digital signal processing. Part II will report on the latest significant results across all of these topic areas.

Full Aims & Scope

## Meet Our Editors

Editor-in-Chief

Chi K. Michael Tse
Dept. of Electronic and Information Engineering
Hong Kong Polytechnic University
Hunghom, Hong Kong
cktse@ieee.org